Re: [Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD

2014-01-28 Thread Richard Henderson
On 01/26/2014 11:25 AM, Peter Maydell wrote: +/* Helper functions for pairwise 32 bit comparisons */ +static void gen_pmax_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) +{ +tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2); +} + +static void gen_pmax_u32(TCGv_i32 res, TCGv_i32

Re: [Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD

2014-01-28 Thread Peter Maydell
On 28 January 2014 17:21, Richard Henderson r...@twiddle.net wrote: On 01/26/2014 11:25 AM, Peter Maydell wrote: +/* Helper functions for pairwise 32 bit comparisons */ +static void gen_pmax_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) +{ +tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2,

[Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD

2014-01-26 Thread Peter Maydell
Implement the pairwise integer operations in the 3-reg-same SIMD group: ADDP, SMAXP, SMINP, UMAXP and UMINP. Signed-off-by: Peter Maydell peter.mayd...@linaro.org --- target-arm/translate-a64.c | 145 - 1 file changed, 144 insertions(+), 1 deletion(-)