Re: [Qemu-devel] [PATCH 15/25] spapr: notify the CPU when the XIVE interrupt priority is more privileged

2017-12-07 Thread Cédric Le Goater
>> +/* Convert a priority number to an Interrupt Pending Buffer (IPB) >> + * register, which indicates a pending interrupt at the priority >> + * corresponding to the bit number >> + */ >> +static uint8_t priority_to_ipb(uint8_t priority) >> +{ >> +return priority > XIVE_PRIORITY_MAX ? >> +

Re: [Qemu-devel] [PATCH 15/25] spapr: notify the CPU when the XIVE interrupt priority is more privileged

2017-12-04 Thread Benjamin Herrenschmidt
On Mon, 2017-12-04 at 12:17 +1100, David Gibson wrote: > On Sat, Dec 02, 2017 at 08:40:58AM -0600, Benjamin Herrenschmidt wrote: > > On Thu, 2017-11-30 at 16:00 +1100, David Gibson wrote: > > > > > > > static uint64_t spapr_xive_icp_accept(sPAPRXiveICP *icp) > > > > { > > > > -return 0; > >

Re: [Qemu-devel] [PATCH 15/25] spapr: notify the CPU when the XIVE interrupt priority is more privileged

2017-12-03 Thread David Gibson
On Sat, Dec 02, 2017 at 08:40:58AM -0600, Benjamin Herrenschmidt wrote: > On Thu, 2017-11-30 at 16:00 +1100, David Gibson wrote: > > > > > static uint64_t spapr_xive_icp_accept(sPAPRXiveICP *icp) > > > { > > > -return 0; > > > +uint8_t nsr = icp->tima_os[TM_NSR]; > > > + > > > +

Re: [Qemu-devel] [PATCH 15/25] spapr: notify the CPU when the XIVE interrupt priority is more privileged

2017-12-02 Thread Benjamin Herrenschmidt
On Thu, 2017-11-30 at 16:00 +1100, David Gibson wrote: > > > static uint64_t spapr_xive_icp_accept(sPAPRXiveICP *icp) > > { > > -return 0; > > +uint8_t nsr = icp->tima_os[TM_NSR]; > > + > > +qemu_irq_lower(icp->output); > > + > > +if (icp->tima_os[TM_NSR] & TM_QW1_NSR_EO) { > >

Re: [Qemu-devel] [PATCH 15/25] spapr: notify the CPU when the XIVE interrupt priority is more privileged

2017-11-30 Thread Cédric Le Goater
On 11/30/2017 05:00 AM, David Gibson wrote: > On Thu, Nov 23, 2017 at 02:29:45PM +0100, Cédric Le Goater wrote: >> The Pending Interrupt Priority Register (PIPR) contains the priority >> of the most favored pending notification. It is calculated from the >> Interrupt Pending Buffer (IPB) which

Re: [Qemu-devel] [PATCH 15/25] spapr: notify the CPU when the XIVE interrupt priority is more privileged

2017-11-29 Thread David Gibson
On Thu, Nov 23, 2017 at 02:29:45PM +0100, Cédric Le Goater wrote: > The Pending Interrupt Priority Register (PIPR) contains the priority > of the most favored pending notification. It is calculated from the > Interrupt Pending Buffer (IPB) which indicates a pending interrupt at > the priority

[Qemu-devel] [PATCH 15/25] spapr: notify the CPU when the XIVE interrupt priority is more privileged

2017-11-23 Thread Cédric Le Goater
The Pending Interrupt Priority Register (PIPR) contains the priority of the most favored pending notification. It is calculated from the Interrupt Pending Buffer (IPB) which indicates a pending interrupt at the priority corresponding to the bit number. If the PIPR is more favored (1) than the