On Fri, 12 Mar 2021 at 09:20, LIU Zhiwei wrote:
>
> Thanks very much. By the way, in my opinion, the signal line in GICv2
> solution is
> something like "QEMU-specific weirdness" .
No, for the GICv2 that really is how the hardware works -- the interrupt
controller talks to the CPU via the
On 2021/3/12 0:50, Peter Maydell wrote:
On Thu, 11 Mar 2021 at 16:40, LIU Zhiwei wrote:
On 2021/3/12 0:07, Peter Maydell wrote:
On Thu, 11 Mar 2021 at 16:01, LIU Zhiwei wrote:
I'm pretty sure that there is some interaction between the CPU and the
interrupt controller on a
On 2021/3/12 4:45, Alistair Francis wrote:
On Thu, Mar 11, 2021 at 11:21 AM LIU Zhiwei wrote:
On 2021/3/11 21:17, Peter Maydell wrote:
On Thu, 11 Mar 2021 at 12:59, LIU Zhiwei wrote:
From the specification, I find that software will not clean the pending bit
on interrupt controller
On Thu, Mar 11, 2021 at 11:21 AM LIU Zhiwei wrote:
>
>
>
> On 2021/3/11 21:17, Peter Maydell wrote:
> > On Thu, 11 Mar 2021 at 12:59, LIU Zhiwei wrote:
> >> From the specification, I find that software will not clean the pending
> >> bit on interrupt controller via a register write.
> >>
> >>
On Thu, 11 Mar 2021 at 16:40, LIU Zhiwei wrote:
>
>
>
> On 2021/3/12 0:07, Peter Maydell wrote:
> > On Thu, 11 Mar 2021 at 16:01, LIU Zhiwei wrote:
> > I'm pretty sure that there is some interaction between the CPU and the
> > interrupt controller on a return-from-interrupt that you are
> >
On 2021/3/12 0:07, Peter Maydell wrote:
On Thu, 11 Mar 2021 at 16:01, LIU Zhiwei wrote:
That's a case I can't understand.
1. An device causes an edge-triggered interrupt A.
2. The interrupt controller sample the interrupt A, and setting pending
bit for A.
3. The interrupt controller
On Thu, 11 Mar 2021 at 16:01, LIU Zhiwei wrote:
> That's a case I can't understand.
>
> 1. An device causes an edge-triggered interrupt A.
> 2. The interrupt controller sample the interrupt A, and setting pending
> bit for A.
> 3. The interrupt controller select the interrupt A to CPU and
On 2021/3/11 21:17, Peter Maydell wrote:
On Thu, 11 Mar 2021 at 12:59, LIU Zhiwei wrote:
From the specification, I find that software will not clean the pending bit on
interrupt controller via a register write.
"When a vectored interrupt is selected and serviced, the hardware will
On Thu, 11 Mar 2021 at 12:59, LIU Zhiwei wrote:
> From the specification, I find that software will not clean the pending bit
> on interrupt controller via a register write.
>
> "When a vectored interrupt is selected and serviced, the hardware will
> automatically clear the
>
> corresponding
On 2021/3/11 17:33, Peter Maydell wrote:
On Thu, 11 Mar 2021 at 02:59, LIU Zhiwei wrote:
Currently, I am writing an interrupt controller (CLIC) for RISC-V. I can't
find a good way to process edge-triggered interrupt.
According to edge-triggered definition, if I select an edge-triggered
On Thu, 11 Mar 2021 at 02:59, LIU Zhiwei wrote:
> Currently, I am writing an interrupt controller (CLIC) for RISC-V. I can't
> find a good way to process edge-triggered interrupt.
>
> According to edge-triggered definition, if I select an edge-triggered
> interrupt to serve , it will clean
Hi folks,
Currently, I am writing an interrupt controller (CLIC) for RISC-V. I
can't find a good way to process edge-triggered interrupt.
According to edge-triggered definition, if I select an edge-triggeredÂ
interrupt to serve , it will clean its pending status. However after
serving the
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