On Mon, Oct 02, 2023 at 01:39:16PM +0200, Marcin Juszkiewicz wrote:
> W dniu 8.09.2023 o 15:29, Marcin Juszkiewicz pisze:
> > W dniu 31.08.2023 o 12:05, Marcin Juszkiewicz pisze:
> > > W dniu 30.08.2023 o 23:48, Michael S. Tsirkin pisze:
> > > > current code sets PCI_SEC_LATENCY_TIMER to WO, but
W dniu 8.09.2023 o 15:29, Marcin Juszkiewicz pisze:
W dniu 31.08.2023 o 12:05, Marcin Juszkiewicz pisze:
W dniu 30.08.2023 o 23:48, Michael S. Tsirkin pisze:
current code sets PCI_SEC_LATENCY_TIMER to WO, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec which says:
W dniu 31.08.2023 o 12:05, Marcin Juszkiewicz pisze:
W dniu 30.08.2023 o 23:48, Michael S. Tsirkin pisze:
current code sets PCI_SEC_LATENCY_TIMER to WO, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec which says:
This register does not apply to PCI Express. It
W dniu 30.08.2023 o 23:48, Michael S. Tsirkin pisze:
current code sets PCI_SEC_LATENCY_TIMER to WO, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec which says:
This register does not apply to PCI Express. It must be read-only
and hardwired to 00h. For PCI
On 31/8/23 08:45, Michael S. Tsirkin wrote:
On Thu, Aug 31, 2023 at 08:22:34AM +0200, Philippe Mathieu-Daudé wrote:
Hi Michael,
On 30/8/23 23:48, Michael S. Tsirkin wrote:
current code sets PCI_SEC_LATENCY_TIMER to WO, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec
On Thu, Aug 31, 2023 at 08:22:34AM +0200, Philippe Mathieu-Daudé wrote:
> Hi Michael,
>
> On 30/8/23 23:48, Michael S. Tsirkin wrote:
> > current code sets PCI_SEC_LATENCY_TIMER to WO, but for
> > pcie to pcie bridges it must be RO 0 according to
> > pci express spec which says:
> > This
Hi Michael,
On 30/8/23 23:48, Michael S. Tsirkin wrote:
current code sets PCI_SEC_LATENCY_TIMER to WO, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec which says:
This register does not apply to PCI Express. It must be read-only
and hardwired to 00h. For PCI
