Commit b8002058 strengthened openat()'s /proc detection by calling
realpath(3) on the given path, which allows various paths and symlinks
that points to the /proc file system to be intercepted correctly.
Using realpath(3), though, has a side effect that it reads the symlinks
along the way, and
On Fri, 8 Dec 2023, Daniel P. Berrangé wrote:
> CC'ing the Xen folks
>
> On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> > Builds of qemu-8.2.0rc2 with xen-4.18.0 are currently failing
> > with errors like
> > ../hw/arm/xen_arm.c:74:5: error: ‘GUEST_VIRTIO_MMIO_SPI_LAST’
In 050a1ba, when moving the macros from preprocessor-guarding to
file-based definition, TARGET_O_LARGEFILE appeared to have been
accidentally left off.
This may have correctness implication, but so far I was only confused by
strace's output.
Fixes: 050a1ba69a ("linux-user: move arm/aarch64/m68k
Since v2:
- More robust handling of `readlink()`
Since v1:
- Eliminate static buffers in do_guest_openat()
Shu-Chun Weng (2):
linux-user: Define TARGET_O_LARGEFILE for aarch64
linux-user: Fix openat() emulation to not modify atime
linux-user/aarch64/target_fcntl.h | 1 +
On Fri, Dec 1, 2023 at 11:37 PM Laurent Vivier wrote:
> On 12/1/23 16:21, Markus Armbruster wrote:
> > Laurent Vivier writes:
> >
> >> On 11/21/23 08:58, Markus Armbruster wrote:
> >>> Laurent, there's a question for you at the end.
> >>>
> >>> Yong Huang writes:
> >>>
> On Thu, Nov 16,
On 12/7/23 18:39, BALATON Zoltan wrote:
On Thu, 7 Dec 2023, aziz tlili wrote:
Dear QEMU Team,
I hope this message finds you well. I've been a user of QEMU for well over
a year.
I wanted to share an idea for a potential enhancement that I believe could
benefit many users, including myself. It
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 69 ++---
1 file changed, 65 insertions(+), 4 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 915357ca71..2f953e4a03 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@
fdt adds pch msi controller, we use 'loongson,pch-msi-1.0'.
See:
drivers/irqchip/irq-loongson-pch-msi.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 33 -
include/hw/pci-host/ls7a.h | 1 +
2 files changed, 33 insertions(+), 1 deletion(-)
diff
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 31 +--
1 file changed, 1 insertion(+), 30 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 2f953e4a03..7dfad60368 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -415,34 +415,6
fdt adds cpu interrupt controller node,
we use 'loongson,cpu-interrupt-controller'.
See:
drivers/irqchip/irq-loongarch-cpu.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 11 +++
include/hw/loongarch/boot.h | 4
2 files changed, 15 insertions(+)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 991df2cc14..f2e13ad7e3 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@
rtc node need interrupts and interrupt-parent cells.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index bd1db2de4f..eb568c71cf 100644
--- a/hw/loongarch/virt.c
+++
uart node need interrupts and interrupt-parent cells.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 7dfad60368..bd1db2de4f 100644
--- a/hw/loongarch/virt.c
+++
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 45 +
hw/loongarch/virt.c | 11 ++---
include/hw/loongarch/boot.h | 27 ++
include/hw/loongarch/virt.h | 10 +
4 files changed, 84 insertions(+), 9 deletions(-)
Hi, All
We already support boot efi kernel with bios, but not support boot elf kernel.
This series adds boot elf kernel with FDT.
'LoongArch supports ACPI and FDT. The information that needs to be passed
to the kernel includes the memmap, the initrd, the command line, optionally
the ACPI/FDT
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 66 -
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index b3fbed2ea0..742a70b7f0 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@
According to the specification, the th.dcache.cvall1 can be executed
under all priviledges.
The specification about xtheadcmo located in,
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadcmo/dcache_cval1.adoc
Signed-off-by: LIU Zhiwei
---
On 11/18/2023 5:03 AM, Isaku Yamahata wrote:
On Wed, Nov 15, 2023 at 02:14:18AM -0500,
Xiaoyao Li wrote:
It's used for discarding opposite memory after memory conversion, for
confidential guest.
When page is converted from shared to private, the original shared
memory can be discarded via
Am 07.12.2023 um 16:22 hat Fiona Ebner geschrieben:
> Am 03.11.23 um 14:12 schrieb Fiona Ebner:
> > Hi,
> >
> > I ran into a strange issue where guest IO would get completely stuck
> > during certain block jobs a while ago and finally managed to find a
> > small reproducer [0]. I'm using a VM
On 05.12.2023 23:41, Alex Bennée wrote:
A lot of the hang I see are when we end up spinning in
rr_wait_io_event for an event that will never come in playback. As a
new check functions which can see if we are in PLAY mode and kick us
us the wait function so the event can be processed.
This fixes
Simply transform the VFIOIOMMUOps struct in an InterfaceClass and do
some initial name replacements. Next changes will start converting
VFIOIOMMUOps.
Signed-off-by: Cédric Le Goater
---
include/hw/vfio/vfio-container-base.h | 18 ++
hw/vfio/common.c | 2 +-
sPAPR IOMMU support is only needed for pseries machines. Compile out
support when CONFIG_PSERIES is not set. This saves ~7K of text.
Signed-off-by: Cédric Le Goater
---
hw/vfio/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/vfio/meson.build
As previously done for the sPAPR and legacy IOMMU backends, convert
the VFIOIOMMUOps struct to a QOM interface. The set of of operations
for this backend can be referenced with a literal typename instead of
a C struct.
Signed-off-by: Cédric Le Goater
---
include/hw/vfio/vfio-common.h |
This will help in converting the sPAPR IOMMU backend to a QOM interface.
Signed-off-by: Cédric Le Goater
---
include/hw/vfio/vfio-container-base.h | 1 +
hw/vfio/container.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/hw/vfio/vfio-container-base.h
Availability of the IOMMUFD backend can now be fully determined at
runtime and the ifdef check was a build time protection (for PPC not
supporting it mostly).
Signed-off-by: Cédric Le Goater
---
hw/vfio/common.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/hw/vfio/common.c
Hello,
The VFIO object hierarchy has some constraints because each VFIO type
has a dual nature: a VFIO nature for passthrough support and a bus
nature (PCI, AP, CCW, Platform) for its initial presentation. It
seemed the best approach made because multi-inheritance is not
feasible with QOM and
This allows to abstract a bit more the sPAPR IOMMU support in the
legacy IOMMU backend.
Signed-off-by: Cédric Le Goater
---
include/hw/vfio/vfio-container-base.h | 1 +
hw/vfio/container.c | 10 +++-
hw/vfio/spapr.c | 35 +++
This will help subsequent patches to unify the initialization of type1
and sPAPR IOMMU backends.
Signed-off-by: Cédric Le Goater
---
hw/vfio/container.c | 63 +
1 file changed, 35 insertions(+), 28 deletions(-)
diff --git a/hw/vfio/container.c
Move some boot functions to boot.c and struct
loongarch_boot_info into struct LoongArchMachineState.
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 125
hw/loongarch/meson.build| 1 +
hw/loongarch/virt.c | 110
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 29 +++--
include/hw/loongarch/boot.h | 9 +
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 60babe3a6e..991df2cc14 100644
---
Add init_systab and set boot_info->a2
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 39 +
include/hw/loongarch/boot.h | 50 +
2 files changed, 89 insertions(+)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
fdt adds Extend I/O Interrupt Controller,
we use 'loongson,ls2k2000-eiointc'.
See:
drivers/irqchip/irq-loongson-eiointc.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 30 +-
include/hw/intc/loongarch_extioi.h | 1 +
2 files changed, 30
The right fdt memory node like [1], not [2]
[1]
memory@0 {
device_type = "memory";
reg = <0x00 0x00 0x00 0x1000>;
};
[2]
memory@0 {
device_type = "memory";
reg = <0x02 0x00 0x02 0x1000>;
};
Pavel Dovgalyuk writes:
> On 05.12.2023 23:41, Alex Bennée wrote:
>> A lot of the hang I see are when we end up spinning in
>> rr_wait_io_event for an event that will never come in playback. As a
>> new check functions which can see if we are in PLAY mode and kick us
>> us the wait function so
CC'ing the Xen folks
On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> Builds of qemu-8.2.0rc2 with xen-4.18.0 are currently failing
> with errors like
> ../hw/arm/xen_arm.c:74:5: error: ‘GUEST_VIRTIO_MMIO_SPI_LAST’ undeclared
> (first use in this function)
>74 |
vfio_init_container() already defines the IOMMU type of the container.
Do the same for the VFIOIOMMUOps struct. This prepares ground for the
following patches that will deduce the associated VFIOIOMMUOps struct
from the IOMMU type.
Signed-off-by: Cédric Le Goater
---
hw/vfio/container.c | 6
Convert the legacy VFIOIOMMUOps struct to the new VFIOIOMMU QOM
interface. The set of of operations for this backend can be referenced
with a literal typename instead of a C struct. This will simplify
support of multiple backends.
Signed-off-by: Cédric Le Goater
---
fdt adds pch pic controller, we use 'loongson,pch-pic-1.0'
See:
drivers/irqchip/irq-loongson-pch-pic.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 30 +-
include/hw/pci-host/ls7a.h | 1 +
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git
Add init_cmline and set boot_info->a0, a1
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 21 +
include/hw/loongarch/virt.h | 2 ++
target/loongarch/cpu.h | 2 ++
3 files changed, 25 insertions(+)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index
we load initrd ramdisk after kernel_high address
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index bd20421745..40796d97bd 100644
--- a/hw/loongarch/boot.c
On Thu, Dec 07, 2023 at 11:30:45PM +0800, Hyman Huang wrote:
> Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
>
> SM4 (GBT.32907-2016) is a cryptographic standard issued by the
> Organization of State Commercial Administration of China (OSCCA)
> as an authorized cryptographic
On Thu, Dec 07, 2023 at 11:47:35PM +0800, Hyman Huang wrote:
> Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
>
> SM4 (GBT.32907-2016) is a cryptographic standard issued by the
> Organization of State Commercial Administration of China (OSCCA)
> as an authorized cryptographic
Ilya Leoshkevich writes:
> Preparation for moving perf.c to tcg/.
>
> This affects only profiling guest code, which has code in a non-0 based
> segment, e.g., 16-bit code, which is not particularly important.
I have no objection to removing the wart. Is it worth adding a note:: to
tcg.rst to
Move vfio_spapr_container_setup() to a VFIOIOMMUClass::setup handler
and convert the sPAPR VFIOIOMMUOps struct to a QOM interface. The
sPAPR QOM interface inherits from the legacy QOM interface because
because both have the same basic needs. The sPAPR interface is then
extended with the handlers
(Adding Xen maintainers)
On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> Builds of qemu-8.2.0rc2 with xen-4.18.0 are currently failing
> with errors like
> ../hw/arm/xen_arm.c:74:5: error: ‘GUEST_VIRTIO_MMIO_SPI_LAST’ undeclared
> (first use in this function)
>74 |
aziz tlili writes:
> Do u guys have some free time to develop kext files "drivers" for VirtIO
> devices (like virtio-gpu-pci and virtio-blk-pci and
> virtio-net-pci) for PowerPC MacOS X Tiger (10.4.11) and later (till
> Leopard 10.5)? Please, I need them as soon as possible!
I don't think open
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fourth release candidate for the QEMU 8.2 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-8.2.0-rc3.tar.xz
From: Conor Dooley
A few months ago I submitted a patch to various lists, deprecating
"riscv,isa" with a lengthy commit message [0] that is now commit
aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
kernel tree. Primarily, the goal was to replace "riscv,isa" with a new
set
On 11/22/23 17:30, Gerd Hoffmann wrote:
> Hi,
>
>> - in general, we should filter out surrogate code points, for any use.
>> any UCS2 string from the guest that contains a surrogate code point
>> should be considered invalid, and the request should be rejected based
>> just on that.
>
>
On Fri, Dec 08, 2023 at 08:47:07AM +, Richard W.M. Jones wrote:
> (Adding Xen maintainers)
>
> On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> > Builds of qemu-8.2.0rc2 with xen-4.18.0 are currently failing
> > with errors like
> > ../hw/arm/xen_arm.c:74:5: error:
On 7/12/23 23:12, Richard Henderson wrote:
On 12/7/23 07:45, Philippe Mathieu-Daudé wrote:
pmu_init() register its event checking the pm_event::supported()
handler. For INST_RETIRED, the event is only registered and the
bit enabled in the PMU Common Event Identification register when
icount is
On Fri, 2023-12-08 at 09:53 +, Alex Bennée wrote:
> Ilya Leoshkevich writes:
>
> > Preparation for moving perf.c to tcg/.
> >
> > This affects only profiling guest code, which has code in a non-0
> > based
> > segment, e.g., 16-bit code, which is not particularly important.
>
> I have no
Hi Richard,
On 8/12/23 01:35, Ilya Leoshkevich wrote:
v2: https://patchew.org/QEMU/20230630234230.596193-1-...@linux.ibm.com/
v2 -> v3: Rebased.
This series was lost and forgotten until Philippe reminded me
about it.
v1:
Hi Peter,
On 8/12/23 11:59, Peter Maydell wrote:
On Fri, 8 Dec 2023 at 10:36, Philippe Mathieu-Daudé wrote:
On 7/12/23 23:12, Richard Henderson wrote:
On 12/7/23 07:45, Philippe Mathieu-Daudé wrote:
pmu_init() register its event checking the pm_event::supported()
handler. For INST_RETIRED,
On Fri, Dec 08, 2023 at 05:56:11PM +0530, Ani Sinha wrote:
> Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allow
> up to 4096 vCPUs")
> Linux kernel can support upto a maximum number of 4096 vCPUS when MAXSMP is
> enabled in the kernel. So bump up the max_cpus value for
On Fri, 8 Dec 2023 at 09:25, Daniel P. Berrangé wrote:
>
> CC'ing the Xen folks
>
> On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> > diff --git a/include/hw/xen/xen_native.h b/include/hw/xen/xen_native.h
> > index 6f09c48823..04b1ef4d34 100644
> > ---
On 8/12/23 01:35, Ilya Leoshkevich wrote:
Currently qemu_target_page_mask() is usable only from the softmmu
code. Make it possible to use it from the *-user code as well.
Make use of it in perf.c.
Signed-off-by: Ilya Leoshkevich
---
accel/tcg/perf.c | 3 ++-
system/physmem.c |
On 7/12/23 23:38, Richard Henderson wrote:
On 12/7/23 07:45, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
stubs/icount.c | 6 --
system/vl.c | 6 +-
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/stubs/icount.c b/stubs/icount.c
index
We need to parse the accelerators first, to be able
to check whether TCG is enabled or not. Then we can
parse the -icount option.
This allows removing the icount_configure() stub.
Fixes: 7f8b6126e7 ("vl: move icount configuration earlier")
Reported-by: Richard Henderson
Signed-off-by: Philippe
pmu_init() register its event checking the pm_event::supported()
handler. For INST_RETIRED, the event is only registered and the
bit enabled in the PMU Common Event Identification register when
icount is enabled as ICOUNT_PRECISE.
PMU events are TCG-only, hardware accelerators handle them
Following the example documented since commit e3fe3988d7 ("error:
Document Error API usage rules"), have icount_configure()
return a boolean indicating whether an error is set or not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/cpu-timers.h | 10 --
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/icount-common.c | 4 +++-
stubs/icount.c| 2 +-
util/async.c | 16 +---
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c
index
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/cpu-timers.h | 2 +-
include/sysemu/replay.h | 11 ---
stubs/icount.c | 19 ---
3 files changed, 9 insertions(+), 23 deletions(-)
diff --git a/include/sysemu/cpu-timers.h
On 08.12.23 08:59, Xiaoyao Li wrote:
On 11/18/2023 5:03 AM, Isaku Yamahata wrote:
On Wed, Nov 15, 2023 at 02:14:18AM -0500,
Xiaoyao Li wrote:
It's used for discarding opposite memory after memory conversion, for
confidential guest.
When page is converted from shared to private, the original
On Fri, Dec 08, 2023 at 08:47:07AM +, Richard W.M. Jones wrote:
> (Adding Xen maintainers)
>
> On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> > Builds of qemu-8.2.0rc2 with xen-4.18.0 are currently failing
> > with errors like
> > ../hw/arm/xen_arm.c:74:5: error:
On Fri, 8 Dec 2023 at 10:36, Philippe Mathieu-Daudé wrote:
>
> On 7/12/23 23:12, Richard Henderson wrote:
> > On 12/7/23 07:45, Philippe Mathieu-Daudé wrote:
> >> pmu_init() register its event checking the pm_event::supported()
> >> handler. For INST_RETIRED, the event is only registered and the
Rather than having to lookup for what the 0, 1, 2, ...
icount values are, use a enum definition.
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/cpu-timers.h | 20 +---
accel/tcg/icount-common.c | 16 +++-
stubs/icount.c | 2 +-
Slightly simplify non-TCG and user emulation code.
This series still adds assertions in ARM INST_RETIRED
PMU events, in order to bypass a linking failure. Better
would be to restrict ARM PMU events to TCG. Left for
another series.
Since v2:
- Have icount_configure() return bool
- Addressed rth's
Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allow up
to 4096 vCPUs")
Linux kernel can support upto a maximum number of 4096 vCPUS when MAXSMP is
enabled in the kernel. So bump up the max_cpus value for q35 machines versions
8.3 and newer to 4096. Older q35 machines
On 8/12/23 12:35, Philippe Mathieu-Daudé wrote:
Rather than having to lookup for what the 0, 1, 2, ...
icount values are, use a enum definition.
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/cpu-timers.h | 20 +---
accel/tcg/icount-common.c | 16 +++-
On Fri, Dec 08, 2023 at 10:59:03AM +, Peter Maydell wrote:
> On Fri, 8 Dec 2023 at 09:25, Daniel P. Berrangé wrote:
> >
> > CC'ing the Xen folks
> >
> > On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> > > diff --git a/include/hw/xen/xen_native.h b/include/hw/xen/xen_native.h
The AioContext must be unlocked before calling blk_co_unref(), because
it takes the AioContext lock internally in blk_unref_bh(), which is
scheduled in the main thread. If we don't unlock, the AioContext is
locked twice and nested event loops such as in bdrv_graph_wrlock() will
deadlock.
Cc:
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
pervasive chiplet model where chiplet
A POWER10 chip is divided into logical units called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet-specific registers. All nest
chiplets
Fabiano Rosas writes:
> We can run the migration tests with two different QEMU binaries to
> test migration compatibility between QEMU versions. This means we'll
> be running the tests with an older QEMU in either source or
> destination.
>
> We need to avoid trying to test functionality that is
On 8/12/23 12:23, Philippe Mathieu-Daudé wrote:
Hi Peter,
On 8/12/23 11:59, Peter Maydell wrote:
On Fri, 8 Dec 2023 at 10:36, Philippe Mathieu-Daudé
wrote:
On 7/12/23 23:12, Richard Henderson wrote:
On 12/7/23 07:45, Philippe Mathieu-Daudé wrote:
pmu_init() register its event checking the
This patch enables mode sense for zbc devices.
Signed-off-by: Daejun Park
---
hw/scsi/scsi-disk.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
index 6691f5edb8..f1ecb77317 100644
--- a/hw/scsi/scsi-disk.c
+++
This patch enables zoned ufs support.
By setting the LU parameter, each LU can be a host-managed zoned device.
This patch manages the zone condition and write pointer of each zone for
a zoned LU. It supports the report zones and reset write pointer commands
for Zoned LUs.
Signed-off-by: Daejun
This patch includes the following tests
Test VPD page and report zones
Test write and unaligned write error
Signed-off-by: Daejun Park
---
tests/qtest/ufs-test.c | 178 +
1 file changed, 178 insertions(+)
diff --git a/tests/qtest/ufs-test.c
Hello everyone,
I am currently working on adding MSI support to virtio-pci on ARM with Xen.
As far as I understand QEMU Xen ARM machine that is used for virtio-pci device
emulation does not initialize any interrupt controllers. And that makes it
somewhat unclear what is the best approach to
This patch enables zoned support for UFS devices.
By applying this patch, a QEMU run can use parameters to configure whether
each LU of each UFS is zoned, and the capacity, size, and max open zones.
Zoned UFS is implemented by referencing ZBC2.
(https://www.t10.org/members/w_zbc2.htm)
Daejun
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
pervasive chiplet model where chiplet
> On 08-Dec-2023, at 6:27 PM, Daniel P. Berrangé wrote:
>
> On Fri, Dec 08, 2023 at 05:56:11PM +0530, Ani Sinha wrote:
>> Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allow
>> up to 4096 vCPUs")
>> Linux kernel can support upto a maximum number of 4096 vCPUS when
Hello,
Thank you for the review and suggestions on V7.
There are no major design/logic changes done in revision 8 from revision 7.
Addressed the minor comments.
The qom-tree looks like below.
(qemu) info qom-tree
/machine (powernv10-machine)
/chip[0] (power10_v2.0-pnv-chip)
/n1-chiplet
A POWER10 chip is divided into logical units called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet-specific registers. All nest
chiplets
On Wed, 2023-12-06 at 11:42 -0600, Michael Roth wrote:
> On Wed, Dec 06, 2023 at 07:20:14PM +0200, Maxim Levitsky wrote:
> > On Tue, 2023-12-05 at 16:28 -0600, Michael Roth wrote:
> > > Commit 7191f24c7fcf ("accel/kvm/kvm-all: Handle register access errors")
> > > added error checking for
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
Steve Sistare writes:
> If the outgoing machine was previously suspended, propagate that to the
> incoming side via global_state, so a subsequent vm_start restores the
> suspended state. To maintain backward and forward compatibility, reclaim
> some space from the runstate member.
>
>
Steve Sistare writes:
> Add a test case to verify that the suspended state is handled correctly
> during live migration precopy. The test suspends the src, migrates, then
> wakes the dest.
>
> Signed-off-by: Steve Sistare
Reviewed-by: Fabiano Rosas
On Fri, Oct 27, 2023 at 11:44 PM Louai Al-Khanji
wrote:
> Hi,
>
> I'm interested in having the guestfwd option work for udp. My
> understanding is that currently it's restricted to only tcp.
>
> I'm not familiar with libslirp internals. What would need to be changed to
> implement this? I'm
On 12/8/23 03:35, Philippe Mathieu-Daudé wrote:
Following the example documented since commit e3fe3988d7 ("error:
Document Error API usage rules"), have icount_configure()
return a boolean indicating whether an error is set or not.
Signed-off-by: Philippe Mathieu-Daudé
---
On 12/8/23 03:35, Philippe Mathieu-Daudé wrote:
We need to parse the accelerators first, to be able
to check whether TCG is enabled or not. Then we can
parse the -icount option.
This allows removing the icount_configure() stub.
Fixes: 7f8b6126e7 ("vl: move icount configuration earlier")
On 12/8/2023 11:37 AM, Fabiano Rosas wrote:
> Steve Sistare writes:
>
>> If the outgoing machine was previously suspended, propagate that to the
>> incoming side via global_state, so a subsequent vm_start restores the
>> suspended state. To maintain backward and forward compatibility, reclaim
On 12/8/23 03:35, Philippe Mathieu-Daudé wrote:
pmu_init() register its event checking the pm_event::supported()
handler. For INST_RETIRED, the event is only registered and the
bit enabled in the PMU Common Event Identification register when
icount is enabled as ICOUNT_PRECISE.
PMU events are
On 12/7/23 18:06, LIU Zhiwei wrote:
For ram memory region the iotlb(which will be filled into the xlat_section
of CPUTLBEntryFull) is calculated as:
iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1) xlat here is the offset_within_region of a MemoryRegionSection, which maybe
not
On 12/8/23 03:35, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/icount-common.c | 4 +++-
stubs/icount.c| 2 +-
util/async.c | 16 +---
3 files changed, 13 insertions(+), 9 deletions(-)
Reviewed-by: Richard
On 12/8/23 03:35, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/cpu-timers.h | 2 +-
include/sysemu/replay.h | 11 ---
stubs/icount.c | 19 ---
3 files changed, 9 insertions(+), 23 deletions(-)
Reviewed-by:
kvm_riscv_reg_id() returns an id encoded with an ulong size, i.e. an u32
size when running TARGET_RISCV32 and u64 when running TARGET_RISCV64.
Rename it to kvm_riscv_reg_id_ulong() to enhance code readability. It'll
be in line with the existing kvm_riscv_reg_id_() helpers.
Signed-off-by: Daniel
Hi,
While working in a follow-up for the Vector KVM regs, where we would
read 'vlenb' and then all other vregs [1], Drew noticed that we're using
kvm_riscv_reg_id() in registers that are u32 and u64.
The helper is returning ulong regs for all cases, meaning that we return
the wrong size for u32
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