On Thu, Apr 18, 2024 at 04:10:58PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> Add dynamic capacity extent list representative to the definition of
> CXLType3Dev and implement get DC extent list mailbox command per
> CXL.spec.3.1:.8.2.9.9.9.2.
>
> Reviewed-by: Jonathan Cameron
>
On Fri, 19 Apr 2024 at 18:36, Ard Biesheuvel wrote:
>
> On Fri, 19 Apr 2024 at 18:09, Jonathan Cameron via groups.io
> wrote:
> >
> > On Fri, 19 Apr 2024 13:52:07 +0200
> > Gerd Hoffmann wrote:
> >
> > > Hi,
> > >
> > > > Gerd, any ideas? Maybe I needs something subtly different in my
> > >
In previous versions of the Arm architecture, the frequency of the
generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
In Armv8.6, the architecture standardized this frequency to 1GHz.
Because there is no ID
The generic timer frequency is settable by board code via a QOM
property "cntfrq", but otherwise defaults to 62.5MHz. The way this
is done includes some complication resulting from how this was
originally a fixed value with no QOM property. Clean it up:
* always set cpu->gt_cntfrq_hz to some
On Thu, Apr 18, 2024 at 04:10:57PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> Add (file/memory backed) host backend for DCD. All the dynamic capacity
> regions will share a single, large enough host backend. Set up address
> space for DC regions to support read/write operations to
From: Dongwon Kim
This commit updates all instances where fields within the QemuDmaBuf
struct are directly accessed, replacing them with calls to these new
helper functions.
v6: fix typos in helper names in ui/spice-display.c
v7: removed prefix, "dpy_gl_" from all helpers
v8: Introduction of
From: Dongwon Kim
This commit updates all occurrences where these fields were
set directly have been updated to utilize helper functions.
v7: removed prefix, "dpy_gl_" from all helpers
v8: Introduction of helpers was removed as those were already added
by the previous commit
Suggested-by:
Hi,
I am new here, so I found some issues suitable for beginners at [1]. I
am currently looking at the API Conversion task of replacing
`qemu_mutex_lock()` and `qemu_mutex_unlock()` with `QEMU_LOCK_GUARD()`
After reading the macro definition of `QEMU_LOCK_GUARD()` and
`WITH_QEMU_LOCK_GUARD()`, I
On Thu, Apr 18, 2024 at 04:11:00PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> To simulate FM functionalities for initiating Dynamic Capacity Add
> (Opcode 5604h) and Dynamic Capacity Release (Opcode 5605h) as in CXL spec
> r3.1 7.6.7.6.5 and 7.6.7.6.6, we implemented two QMP interfaces
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Tue, 16 Apr 2024 at 19:11, Don Porter wrote:
> >
> > On 4/16/24 13:03, Peter Maydell wrote:
> > > On Tue, 16 Apr 2024 at 17:53, Don Porter wrote:
> > >> There is still a lot I am learning about the code base, but it seems
> > >> that
On 19/04/2024 09:48, Thomas Huth wrote:
Add some words about how to enable or disable boolean features,
and remove the note about a Linux kernel being available on the
QEMU website (they have been removed long ago already), and the
note about NetBSD and OpenBSD still having issues (they should
From: Paolo Bonzini
Add 9.1 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Cc: Cornelia Huck
Cc: Thomas Huth
Cc: Harsh Prateek Bora
Cc: Gavin Shan
Signed-off-by: Paolo Bonzini
Acked-by: Thomas Huth
Reviewed-by: Cornelia Huck
Reviewed-by: Harsh Prateek Bora
Reviewed-by: Zhao Liu
In previous versions of the Arm architecture, the frequency of the
generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
In Armv8.6, the architecture standardized this frequency to 1GHz.
Because there is no ID
On Thu, Apr 18, 2024 at 04:11:02PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> With the change, we extend the extent release mailbox command processing
> to allow more flexible release. As long as the DPA range of the extent to
> release is covered by accepted extent(s) in the device,
On Thu, Apr 18, 2024 at 04:11:03PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> Before the change, the QMP interface used for add/release DC extents
> only allows to release an extent whose DPA range is contained by a single
> accepted extent in the device.
>
> With the change, we relax
On Fri, 19 Apr 2024 at 09:49, Thomas Huth wrote:
>
> Add some words about how to enable or disable boolean features,
> and remove the note about a Linux kernel being available on the
> QEMU website (they have been removed long ago already), and the
> note about NetBSD and OpenBSD still having
On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote:
> On Thu, Apr 18, 2024 at 04:10:51PM -0700, nifan@gmail.com wrote:
> > A git tree of this series can be found here (with one extra commit on top
> > for printing out accepted/pending extent list):
> >
Some ARM CPUs advertise themselves as SMT by having the MT[24] bit set
to 1 in the MPIDR register. These CPUs have the thread id in Aff0[7:0]
bits, CPU id in Aff1[15:8] bits and cluster id in Aff2[23:16] bits in
MPIDR.
On the other hand, ARM CPUs without SMT have the MT[24] bit set to 0,
CPU id
From: Dongwon Kim
This commit introduces utility functions for the creation and deallocation
of QemuDmaBuf instances. Additionally, it updates all relevant sections
of the codebase to utilize these new utility functions.
v7: remove prefix, "dpy_gl_" from all helpers
qemu_dmabuf_free()
From: Dongwon Kim
New header and source files are added for containing QemuDmaBuf struct
definition and newly introduced helpers for creating/freeing the struct
and accessing its data.
Suggested-by: Marc-André Lureau
Cc: Philippe Mathieu-Daudé
Cc: Daniel P. Berrangé
Cc: Vivek Kasireddy
From: Dongwon Kim
'fence_fd' needs to be validated always before being referenced
And the passing condition should include '== 0' as 0 is a valid
value for the file descriptor.
Suggested-by: Marc-André Lureau
Cc: Philippe Mathieu-Daudé
Cc: Daniel P. Berrangé
Cc: Vivek Kasireddy
From: Dongwon Kim
This series introduces privacy enhancements to the QemuDmaBuf struct
and its contained data to bolster security. it accomplishes this by
introducing of helper functions for allocating, deallocating, and
accessing individual fields within the struct and replacing all direct
From: Dongwon Kim
To complete privatizing process of QemuDmaBuf, QemuDmaBuf struct def
is moved to dmabuf.c
Suggested-by: Marc-André Lureau
Cc: Philippe Mathieu-Daudé
Cc: Daniel P. Berrangé
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
include/ui/dmabuf.h | 19 +--
The various Intel CPU manuals claim that SGDT and SIDT can write either 24-bits
or 32-bits depending upon the operand size, but this is incorrect. Not only do
the Intel CPU manuals give contradictory information between processor
revisions, but this information doesn't even match real-life
On Thu, Apr 18, 2024 at 04:10:59PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> Per CXL spec 3.1, two mailbox commands are implemented:
> Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.9.9.3, and
> Release Dynamic Capacity (Opcode 4803h) 8.2.9.9.9.4.
>
> For the process of the above
On Thu, Apr 18, 2024 at 04:10:53PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> Per cxl spec r3.1, add dynamic capacity region representative based on
> Table 8-165 and extend the cxl type3 device definition to include DC region
> information. Also, based on info in 8.2.9.9.9.1, add 'Get
On Thu, Apr 18, 2024 at 04:10:54PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> Rename mem_size as static_mem_size for type3 memdev to cover static RAM and
> pmem capacity, preparing for the introduction of dynamic capacity to support
> dynamic capacity devices.
>
> Reviewed-by:
On Thu, Apr 18, 2024 at 04:11:01PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> All DPA ranges in the DC regions are invalid to access until an extent
> covering the range has been successfully accepted by the host. A bitmap
> is added to each region to record whether a DC block in the
On Thu, Apr 18, 2024 at 04:10:51PM -0700, nifan@gmail.com wrote:
> A git tree of this series can be found here (with one extra commit on top
> for printing out accepted/pending extent list):
> https://github.com/moking/qemu/tree/dcd-v7
>
> v6->v7:
>
> 1. Fixed the dvsec range register issue
On Thu, Apr 18, 2024 at 04:10:55PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> With the change, when setting up memory for type3 memory device, we can
> create DC regions.
> A property 'num-dc-regions' is added to ct3_props to allow users to pass the
> number of DC regions to create. To
On Fri, Apr 19, 2024 at 12:38 AM John Snow wrote:
>
> This commit, finally, adds cross-referencing support to various field
> lists; modeled tightly after Sphinx's own Python domain code.
>
> Cross-referencing support is added to type names provided to :arg:,
> :memb:, :returns: and :choice:.
>
>
On Wed, Apr 17, 2024 at 7:58 PM Daniel P. Berrangé wrote:
> > > However, one question remains unanswered pointing the issue with the
> > > location of "/var/local/run/qemu-vmsr-helper.sock", created by
> > > compute_default_paths(). QEMU is not allowed to reach the socket here.
> >
> > If I
On Thu, 18 Apr 2024 at 16:20, Peter Maydell wrote:
>
> As of version DDI0487K.a of the Arm ARM, some architectural features
> which previously didn't have official names have been named. Add
> these to the list of features which QEMU's TCG emulation supports.
> Mostly these are features which we
On 2024-04-18 4:27 p.m., Mark Cave-Ayland wrote:
On 07/03/2024 17:43, Thomas Huth wrote:
Add some words about how to enable or disable boolean features,
and remove the note about a Linux kernel being available on the
QEMU website (they have been removed long ago already).
Signed-off-by:
From: Dongwon Kim
This commit introduces utility functions for the creation and deallocation
of QemuDmaBuf instances. Additionally, it updates all relevant sections
of the codebase to utilize these new utility functions.
v7: remove prefix, "dpy_gl_" from all helpers
qemu_dmabuf_free()
From: Dongwon Kim
New header and source files are added for containing QemuDmaBuf struct
definition and newly introduced helpers for creating/freeing the struct
and accessing its data.
Suggested-by: Marc-André Lureau
Cc: Philippe Mathieu-Daudé
Cc: Daniel P. Berrangé
Cc: Vivek Kasireddy
From: Dongwon Kim
This commit updates all instances where fields within the QemuDmaBuf
struct are directly accessed, replacing them with calls to these new
helper functions.
v6: fix typos in helper names in ui/spice-display.c
v7: removed prefix, "dpy_gl_" from all helpers
v8: Introduction of
From: Dongwon Kim
To complete privatizing process of QemuDmaBuf, QemuDmaBuf struct def
is moved to dmabuf.c
Suggested-by: Marc-André Lureau
Cc: Philippe Mathieu-Daudé
Cc: Daniel P. Berrangé
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
include/ui/dmabuf.h | 19 +--
From: Dongwon Kim
This commit updates all occurrences where these fields were
set directly have been updated to utilize helper functions.
v7: removed prefix, "dpy_gl_" from all helpers
v8: Introduction of helpers was removed as those were already added
by the previous commit
Suggested-by:
From: Dongwon Kim
'fence_fd' needs to be validated always before being referenced
And the passing condition should include '== 0' as 0 is a valid
value for the file descriptor.
Suggested-by: Marc-André Lureau
Cc: Philippe Mathieu-Daudé
Cc: Daniel P. Berrangé
Cc: Vivek Kasireddy
From: Dongwon Kim
This series introduces privacy enhancements to the QemuDmaBuf struct
and its contained data to bolster security. it accomplishes this by
introducing of helper functions for allocating, deallocating, and
accessing individual fields within the struct and replacing all direct
On 20/04/2024 00:14, Brad Smith wrote:
On 2024-04-18 4:27 p.m., Mark Cave-Ayland wrote:
On 07/03/2024 17:43, Thomas Huth wrote:
Add some words about how to enable or disable boolean features,
and remove the note about a Linux kernel being available on the
QEMU website (they have been removed
On 20/04/2024 02:21, Richard Henderson wrote:
On 4/19/24 12:51, Mark Cave-Ayland wrote:
The various Intel CPU manuals claim that SGDT and SIDT can write either 24-bits
or 32-bits depending upon the operand size, but this is incorrect. Not only do
the Intel CPU manuals give contradictory
Printing an "s390x" in front of each CPU name is not helpful at all:
It is confusing for the users since they don't know whether they
have to specify these letters for the "-cpu" parameter, too, and
it also takes some precious space in the dense output of the CPU
entries. Let's simply remove this
Printing an "x86" in front of each CPU name is not helpful at all:
It is confusing for the users since they don't know whether they
have to specify these letters for the "-cpu" parameter, too, and
it also takes some precious space in the dense output of the CPU
entries. Let's simply remove this
Printing an architecture prefix in front of each CPU name is not helpful
at all: It is confusing for the users since they don't know whether they
have to specify these letters for the "-cpu" parameter, too, and it also
takes some precious space in the dense output of the CPU entries. Let's
simply
On 4/19/24 12:51, Mark Cave-Ayland wrote:
The various Intel CPU manuals claim that SGDT and SIDT can write either 24-bits
or 32-bits depending upon the operand size, but this is incorrect. Not only do
the Intel CPU manuals give contradictory information between processor
revisions, but this
On 4/19/2024 1:29 AM, Eugenio Perez Martin wrote:
On Thu, Apr 18, 2024 at 10:46 PM Si-Wei Liu wrote:
On 4/10/2024 3:03 AM, Eugenio Pérez wrote:
IOVA tree is also used to track the mappings of virtio-net shadow
virtqueue. This mappings may not match with the GPA->HVA ones.
This causes a
Printing a "PowerPC" in front of each CPU name is not helpful at all:
It is confusing for the users since they don't know whether they
have to specify these letters for the "-cpu" parameter, too, and
it also takes some precious space in the dense output of the CPU
entries. Let's simply remove this
Commit b447378e12 ("qom/object: Limit type names to alphanumerical ...")
cut down the amount of allowed characters for QOM types to a saner set.
The "+" character was meant to be included in this set, so we had to
add a hack there to still allow the legacy names of POWER and Sparc64
CPUs. However,
Add some words about how to enable or disable boolean features,
and remove the note about a Linux kernel being available on the
QEMU website (they have been removed long ago already), and the
note about NetBSD and OpenBSD still having issues (they should
work fine nowadays).
Fixes:
The Sparc CPU naming and the corresponding help text is somewhat
confusing for the users. We should avoid spaces in the Names and
provide clear information to the users what can be passed to the
"-cpu" option.
While we're at it, also remove the "+" from two of the CPU names
since this character is
For consistency we should drop the names with a "+" in it in the
long run.
Reviewed-by: Mark Cave-Ayland
Signed-off-by: Thomas Huth
---
docs/about/deprecated.rst | 9 +
1 file changed, 9 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index
The output of "-cpu help" is currently rather confusing to the users:
It might not be fully clear which part of the output defines the CPU
names since the CPU names contain white spaces (which we later have to
convert into dashes internally). At best it's at least a nuisance since
the users might
Since the calls are elided when KVM is not available,
we can remove the stubs (which are never compiled).
Inspired-by: Thomas Huth >
Signed-off-by: Philippe Mathieu-Daudé
---
RFC: untested =) Inspired by
https://lore.kernel.org/qemu-devel/0ae778e1-b4aa-4021-bdbc-4c6a663db...@redhat.com/
---
On 19/4/24 10:44, Zhao Liu wrote:
Hi Thomas,
On Fri, Apr 19, 2024 at 09:50:46AM +0200, Thomas Huth wrote:
Date: Fri, 19 Apr 2024 09:50:46 +0200
From: Thomas Huth
Subject: Re: [PATCH 3/6] target/s390x/cpu_models: Make
kvm_s390_get_host_cpu_model() return boolean
On 19/04/2024 08.57, Zhao
Hi Richard,
On 4/16/24 23:26, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
mulli : D-form
mul{lw, lwo, hw, hwu}[.] : XO-form
The changes were verified by validating that the tcg
On 19/4/24 11:06, Philippe Mathieu-Daudé wrote:
Since the calls are elided when KVM is not available,
we can remove the stubs (which are never compiled).
Inspired-by: Thomas Huth >
Signed-off-by: Philippe Mathieu-Daudé
---
RFC: untested =)
Now tested!
Inspired by
Hi Richard,
On 4/17/24 00:50, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i : D-form
isel : A-form
The changes were verified by validating
On 2024/04/19 4:00, Dmitry Osipenko wrote:
From: Antonio Caggiano
Enable resource UUID feature and implement command resource assign UUID.
UUID feature availability is mandatory for Vulkan Venus context.
UUID is intended for sharing dmabufs between virtio devices on host. Qemu
doesn't have
> > > On 4/18/24 03:27, Zhiwei Jiang wrote:
> > > > Sometimes, when the address of the passed TCGTemp *ts variable is the
> > > > same as tcg_ctx,
> > >
> > > Pardon? When would TCGTemp *ts == TCGContext *tcg_ctx?
> > >
> > >
> > > > the index calculated in the temp_idx function, i.e., ts -
> >
On 2024/04/19 4:00, Dmitry Osipenko wrote:
From: Antonio Caggiano
Request Venus when initializing VirGL and if vulkan=true flag is set for
virtio-gpu device.
Signed-off-by: Antonio Caggiano
Signed-off-by: Huang Rui
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-virgl.c | 14
On 19/4/24 00:05, dongwon@intel.com wrote:
From: Dongwon Kim
This series introduces privacy enhancements to the QemuDmaBuf struct
and its contained data to bolster security. it accomplishes this by
introducing of helper functions for allocating, deallocating, and
accessing individual
Hi Cedric,
> On 4/16/24 11:18, Jamin Lin wrote:
> > Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35
> CPU).
> >
> > AST2700 SOC and its interrupt controller are too complex to handle in
> > the common Aspeed SoC framework. We introduce a new ast2700 class with
> >
On 19/04/2024 08.57, Zhao Liu wrote:
From: Zhao Liu
Use @errp to fetech error information directly and drop the local
virable @err.
With the typos fixed:
Reviewed-by: Thomas Huth
On 19/04/2024 08.57, Zhao Liu wrote:
From: Zhao Liu
As error.h suggested, the best practice for callee is to return
something to indicate success / failure.
So make kvm_s390_apply_cpu_model() return boolean and check the
returned boolean in apply_cpu_model() instead of accessing @err.
On Thu, Apr 18, 2024 at 10:46 PM Si-Wei Liu wrote:
>
>
>
> On 4/10/2024 3:03 AM, Eugenio Pérez wrote:
> > IOVA tree is also used to track the mappings of virtio-net shadow
> > virtqueue. This mappings may not match with the GPA->HVA ones.
> >
> > This causes a problem when overlapped regions
We are running this test since almost a year; it is
safe to remove its debug statements, which clutter
CI jobs output:
▶ 88/100 /nested-aio-poll OK
io_read 0x16bb26158
io_poll_true 0x16bb26158
> io_poll_ready
io_read 0x16bb26164
< io_poll_ready
io_poll_true
On 4/16/24 23:55, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
neg[o][.] : XO-form
mod{sw, uw}, darn : X-form
The changes were verified by validating that the tcg ops generated by
those
On 4/16/24 23:49, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by
those
instructions remain the same,
On Fri, 19 Apr 2024 at 04:49, 姜智伟 wrote:
>
> > On 4/18/24 03:27, Zhiwei Jiang wrote:
> > > Sometimes, when the address of the passed TCGTemp *ts variable is the
> > > same as tcg_ctx,
> >
> > Pardon? When would TCGTemp *ts == TCGContext *tcg_ctx?
> >
> >
> > > the index calculated in the
Hi Eric,
On Thu, Apr 18, 2024 at 08:11:06PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/8/24 16:08, Mostafa Saleh wrote:
> > Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs
> > but not nested instances.
> > This patch series adds support for nested translation in SMMUv3,
>
On 4/17/24 01:05, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s] : D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d}[.],
Hi,
On macOS, the fuzz-virtio-scsi-test triggers
virtio_error(vdev, "Cannot map used") from
virtio_init_region_cache():
QTEST_QEMU_BINARY=./qemu-system-x86_64 tests/qtest/fuzz-virtio-scsi-test
# Start of x86_64 tests
# Start of fuzz tests
# starting QEMU: exec ./qemu-system-x86_64 ...
-M
On 4/17/24 00:08, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
divd[u, e, eu][o][.] : XO-form
mod{sd, ud} : X-form
With this patch, all the fixed-point arithmetic instructions have been
moved to
Hi Thomas,
On Fri, Apr 19, 2024 at 09:50:46AM +0200, Thomas Huth wrote:
> Date: Fri, 19 Apr 2024 09:50:46 +0200
> From: Thomas Huth
> Subject: Re: [PATCH 3/6] target/s390x/cpu_models: Make
> kvm_s390_get_host_cpu_model() return boolean
>
> On 19/04/2024 08.57, Zhao Liu wrote:
> > From: Zhao
On Fri, Apr 19, 2024 at 09:39:53AM +0200, Thomas Huth wrote:
> Date: Fri, 19 Apr 2024 09:39:53 +0200
> From: Thomas Huth
> Subject: Re: [PATCH 2/6] target/s390x/cpu_model: Drop local @err in
> s390_realize_cpu_model()
>
> On 19/04/2024 08.57, Zhao Liu wrote:
> > From: Zhao Liu
> >
> > Use
On 2024/04/19 4:00, Dmitry Osipenko wrote:
Add new "suspended" flag to virtio_gpu_ctrl_command telling cmd
processor that it should stop processing commands and retry again
next time until flag is unset.
Signed-off-by: Dmitry Osipenko
This flag shouldn't be added to virtio_gpu_ctrl_command.
On 19/4/24 10:48, Thomas Huth wrote:
For consistency we should drop the names with a "+" in it in the
long run.
Reviewed-by: Mark Cave-Ayland
Signed-off-by: Thomas Huth
---
docs/about/deprecated.rst | 9 +
1 file changed, 9 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 16/04/2024 21:56, Andrey Drobyshev wrote:
On 10/27/23 14:10, Jean-Louis Dupond wrote:
[...]
I've checked all the code paths, and as far as I see it nowhere breaks
the discard_no_unref option.
It's important that we don't introduce new code paths that can make
holes in the qcow2 image when
Hi Richard,
On 4/16/24 23:27, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
The handler methods for divw[u] instructions internally use
Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if
we move
the above said instructions to decodetree, as
On 2024/04/19 4:00, Dmitry Osipenko wrote:
From: Antonio Caggiano
Support BLOB resources creation, mapping and unmapping by calling the
new stable virglrenderer 0.10 interface. Only enabled when available and
via the blob config. E.g. -device virtio-vga-gl,blob=true
Signed-off-by: Antonio
Hi Richard,
On 4/17/24 00:06, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
+static bool trans_MADDHDU(DisasContext *ctx, arg_MADDHDU *a)
...
+ tcg_gen_movi_i64(t1, 0);
Drop the movi.
+ tcg_gen_add2_i64(t1, cpu_gpr[a->vrt], lo, hi, cpu_gpr[a->rc], t1);
Use
On 2024/04/19 4:00, Dmitry Osipenko wrote:
From: Pierre-Eric Pelloux-Prayer
virtio_gpu_virgl_get_num_capsets will return "num_capsets", but we can't
assume that capset_index 1 is always VIRGL2 once we'll support more capsets,
like Venus and DRM capsets. Register capsets dynamically to avoid
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do
>compatibility check with host IOMMU cap/ecap
>
>Hello Zhenzhong,
>
>On 4/18/24 10:42, Duan, Zhenzhong wrote:
>> Hi Cédric,
>>
>>> -Original Message-
>>> From: Cédric Le
Hi Cedric,
>
> Hello Jamin,
>
> On 4/16/24 11:18, Jamin Lin wrote:
> > AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM
> Side
> > Address High Part(0x7C)"
> > register to support 64 bits dma dram address.
> > Add helper routines functions to compute the dma dram address, new
>
From: Zhao Liu
As error.h suggested, the best practice for callee is to return
something to indicate success / failure.
So make kvm_s390_apply_cpu_model() return boolean and check the
returned boolean in apply_cpu_model() instead of accessing @err.
Signed-off-by: Zhao Liu
---
From: Zhao Liu
As error.h suggested, the best practice for callee is to return
something to indicate success / failure.
With returned boolean, there's no need to check @err.
Suggested-by: Thomas Huth
Signed-off-by: Zhao Liu
---
target/s390x/cpu_models.c | 14 +++---
1 file changed,
From: Zhao Liu
As error.h suggested, the best practice for callee is to return
something to indicate success / failure.
So make kvm_s390_get_host_cpu_model() return boolean and check the
returned boolean in get_max_cpu_model() instead of accessing @err.
Additionally, since now
From: Zhao Liu
Use @errp to fetech error information directly and drop the local
virable @err.
Signed-off-by: Zhao Liu
---
target/s390x/cpu_models.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index
> > diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
> > index 052540a866ac..a0e4acb707d7 100644
> > --- a/target/s390x/cpu_models.c
> > +++ b/target/s390x/cpu_models.c
> > @@ -560,16 +560,15 @@ S390CPUModel *get_max_cpu_model(Error **errp)
> > }
> > if
Hello Zhenzhong,
On 4/18/24 10:42, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do
compatibility check with host IOMMU cap/ecap
Hello Zhenzhong
On 4/17/24 11:24, Duan, Zhenzhong wrote:
On 19/4/24 08:57, Zhao Liu wrote:
From: Zhao Liu
As error.h suggested, the best practice for callee is to return
something to indicate success / failure.
So make kvm_s390_get_host_cpu_model() return boolean and check the
returned boolean in get_max_cpu_model() instead of accessing @err.
On 19/04/2024 08.57, Zhao Liu wrote:
From: Zhao Liu
Use @errp to fetech error information directly and drop the local
virable @err.
Copy-n-paste of the same typos as in patch 2 ;-)
Signed-off-by: Zhao Liu
---
target/s390x/cpu_models.c | 4 +---
1 file changed, 1 insertion(+), 3
From: Zhao Liu
Hi list,
This series is the followup of Thomas' suggestion in previous
ERRP_GUARD() cleanup[1]. And based on Thomas' thoughts, I tried to clean
up as many of the other related places (in s390x/cpu_models.c).
[1]:
From: Zhao Liu
Use @errp to fetech error information directly and drop the local
virable @err.
Suggested-by: Thomas Huth
Signed-off-by: Zhao Liu
---
target/s390x/cpu_models.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/s390x/cpu_models.c
From: Zhao Liu
Use @errp to fetech error information directly and drop the local
virable @err.
Signed-off-by: Zhao Liu
---
target/s390x/cpu_models_sysemu.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/s390x/cpu_models_sysemu.c
On 19/4/24 08:57, Zhao Liu wrote:
From: Zhao Liu
---
Zhao Liu (6):
target/s390x/cpu_model: Make check_compatibility() return boolean
target/s390x/cpu_model: Drop local @err in s390_realize_cpu_model()
target/s390x/cpu_models: Make kvm_s390_get_host_cpu_model() return
boolean
On 4/16/24 11:18, Jamin Lin wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
On 19/04/2024 08.57, Zhao Liu wrote:
From: Zhao Liu
Use @errp to fetech error information directly and drop the local
s/fetech/fetch/
virable @err.
s/virable/variable/
Suggested-by: Thomas Huth
Signed-off-by: Zhao Liu
---
target/s390x/cpu_models.c | 4 +---
1 file changed, 1
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