On Fri, 3 May 2024 at 12:10, Paolo Bonzini wrote:
>
> Depending on the phase of the moon, this seems to be causing CI failures on
> FreeBSD.
> Fortunately, valgrind catches it too, and in a fully deterministic way:
>
> ==210026== Invalid write of size 4
> ==210026==at 0x5222F3:
在 2024/4/24 2:40, Dan Williams 写道:
Shiyang Ruan wrote:
Currently driver only traces cxl events, poison creation (for both vmem
and pmem type) on cxl memdev is silent.
As it should be.
OS needs to be notified then it could handle poison pages in time.
No, it was always the case that
On 2/5/24 16:29, Peter Maydell wrote:
We only support the most recent two versions of macOS (currently
macOS 13 Ventura and macOS 14 Sonoma), and our ui/cocoa.m code
already assumes at least macOS 12 Monterey or better, because it uses
NSScreen safeAreaInsets, which is 12.0-or-newer.
Remove the
On 5/3/24 01:51, Paolo Bonzini wrote:
Together with the series at
https://patchew.org/QEMU/20240423131612.28362-1-pbonz...@redhat.com/,
this allows adding sparc-softmmu to the target list of the
build-without-defaults CI job.
Signed-off-by: Paolo Bonzini
---
tests/qtest/m48t59-test.c | 11
On 5/3/24 02:03, Paolo Bonzini wrote:
Migration code needs no private fields of the coroutine backend.
Include the "regular" coroutine.h header.
Signed-off-by: Paolo Bonzini
---
migration/migration.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On Thu, 2 May 2024 13:00:34 -0700 Richard Henderson
wrote:
>
> On 5/2/24 12:20, Matheus Tavares Bernardino wrote:
> >
> > +
> > +void test_multi_cof(void)
> > +{
> > +asm volatile(
> > +"p0 = cmp.eq(r0, r0)\n"
> > +"{\n"
> > +"if (p0) jump
On Fri, May 03, 2024, Mickaël Salaün wrote:
> Add an interface for user space to be notified about guests' Heki policy
> and related violations.
>
> Extend the KVM_ENABLE_CAP IOCTL with KVM_CAP_HEKI_CONFIGURE and
> KVM_CAP_HEKI_DENIAL. Each one takes a bitmask as first argument that can
>
Hello Jamin,
On 4/30/24 09:56, Jamin Lin wrote:
Hi Cedric,
-Original Message-
From: Cédric Le Goater
Sent: Tuesday, April 30, 2024 3:26 PM
To: Jamin Lin ; Peter Maydell
; Andrew Jeffery ;
Joel Stanley ; Alistair Francis ; Cleber
Rosa ; Philippe Mathieu-Daudé ;
Wainer dos Santos
On 5/3/24 07:58, Philippe Mathieu-Daudé wrote:
On 24/4/24 19:09, Richard Henderson wrote:
For cpus using PMSA, when the MPU is disabled, the default memory
type is Normal, Non-cachable.
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation
disabled")
Reported-by:
From: Peter Maydell
We only support the most recent two versions of macOS (currently
macOS 13 Ventura and macOS 14 Sonoma), and our ui/cocoa.m code
already assumes at least macOS 12 Monterey or better, because it uses
NSScreen safeAreaInsets, which is 12.0-or-newer.
Remove the ifdefs that were
The documentation says:
SUBV Rm, RnRn - Rm -> Rn, underflow -> T
The overflow / underflow can be calculated as:
T = ((Rn ^ Rm) & (Result ^ Rn)) >> 31
However we were using the incorrect:
T = ((Rn ^ Rm) & (Result ^ Rm)) >> 31
Fix by using the Rn register instead of Rm.
Add
Keep all user emulation headers under the same user/ directory.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240428221450.26460-2-phi...@linaro.org>
---
MAINTAINERS | 1 -
bsd-user/qemu.h | 2 +-
include/{exec =>
The documentation says:
ADDV Rm, RnRn + Rm -> Rn, overflow -> T
But QEMU implementation was:
ADDV Rm, RnRn + Rm -> Rm, overflow -> T
Fix by filling the correct Rm register.
Add tests provided by Paul Cercueil.
Cc: qemu-sta...@nongnu.org
Fixes: ad8d25a11f ("target-sh4:
Commit 1ad2134f91 ("Hardware convenience library") extracted
"cpu-common.h" from "cpu-all.h", which uses the LGPL-2.1+ license.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240427155714.53669-5-phi...@linaro.org>
---
include/exec/cpu-common.h | 9
Keep all user emulation headers under the same user/ directory.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240503125202.35667-1-phi...@linaro.org>
---
bsd-user/qemu.h| 2 +-
include/exec/cpu-all.h | 2 +-
From: Anthony PERARD
Signed-off-by: Anthony PERARD
Acked-by: Paul Durrant
Acked-by: Stefano Stabellini
Message-ID: <20240429154938.19340-1-anthony.per...@citrix.com>
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
When mechanically moving the @dirty field to AccelCPUState
in commit 9ad49538c7, we neglected cpu->accel is still NULL
when we want to dereference it.
Fixes: 9ad49538c7 ("accel/whpx: Use accel-specific per-vcpu @dirty field")
Reported-by: Volker Rümelin
Suggested-by: Volker Rümelin
The following changes since commit fd87be1dada5672f877e03c2ca8504458292c479:
Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging
(2024-04-26 15:28:13 -0700)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/accel-sh4-ui-20240503
for you
When mechanically moving the @dirty field to AccelCPUState
in commit 79f1926b2d, we neglected cpu->accel is still NULL
when we want to dereference it.
Reported-by: Volker Rümelin
Suggested-by: Volker Rümelin
Fixes: 79f1926b2d ("accel/nvmm: Use accel-specific per-vcpu @dirty field")
"exec/ram_addr.h" shouldn't be used with user emulation.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Richard Henderson
Message-Id: <20240427155714.53669-4-phi...@linaro.org>
---
plugins/api.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/plugins/api.c b/plugins/api.c
All user emulation headers are now under include/user/.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240428221450.26460-3-phi...@linaro.org>
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Fri, Apr 26, 2024 at 11:20:36AM -0300, Fabiano Rosas wrote:
> When doing file migration, QEMU accepts an offset that should be
> skipped when writing the migration stream to the file. The purpose of
> the offset is to allow the management layer to put its own metadata at
> the start of the
The Hexagon Programmer's Reference Manual says that the exception 0x1e
should be raised upon an unaligned program counter. Let's implement that
and also add some tests.
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Richard Henderson
Reviewed-by: Taylor Simpson
---
Changes in v6:
- The
在 2024/5/1 5:00, Alison Schofield 写道:
On Wed, Apr 17, 2024 at 03:50:52PM +0800, Shiyang Ruan wrote:
The length of Physical Address in General Media Event Record/DRAM Event
Record is 64-bit, so the field mask should be defined as such length.
Otherwise, this causes cxl_general_media and
On Fri, May 03, 2024 at 02:15:09PM +0200, Paolo Bonzini wrote:
> sparc-softmmu is able to run a subset of qtests when compiled
> --without-default-devices,
> so use it instead of x86_64-softmmu for the msys2 run.
>
> Signed-off-by: Paolo Bonzini
> ---
> .gitlab-ci.d/windows.yml | 5 +
> 1
Reserve an id to be used by the RISC-V IOMMU PCI device.
Cc: Gerd Hoffmann
Signed-off-by: Daniel Henrique Barboza
---
docs/specs/pci-ids.rst | 2 ++
include/hw/pci/pci.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst
index
Keep all user emulation headers under the same user/ directory.
Signed-off-by: Philippe Mathieu-Daudé
---
Forgot to include this patch in "exec: Rework around CPUState user fields"
https://lore.kernel.org/qemu-devel/20240428221450.26460-1-phi...@linaro.org/
---
bsd-user/qemu.h
Add an interface for user space to be notified about guests' Heki policy
and related violations.
Extend the KVM_ENABLE_CAP IOCTL with KVM_CAP_HEKI_CONFIGURE and
KVM_CAP_HEKI_DENIAL. Each one takes a bitmask as first argument that can
contains KVM_HEKI_EXIT_REASON_CR0 and KVM_HEKI_EXIT_REASON_CR4.
The new CONFIG_HEKI_KUNIT_TEST option enables to run tests in a a kernel
module. The minimal required configuration is listed in the
virt/heki-test/.kunitconfig file.
test_cr_disable_smep checks control-register pinning by trying to
disable SMEP. This test should then failed on a non-protected
On Fri, May 03, 2024 at 04:08:45PM +0200, Markus Armbruster wrote:
> If there's still time, suggest to tweak the subject to
>
> hmp/migration: Fix "migrate" command's documentation
Yes there is. :)
>
> Peter Xu writes:
>
> > On Fri, May 03, 2024 at 08:58:09AM +0200, Markus Armbruster
On 24/4/24 19:09, Richard Henderson wrote:
For cpus using PMSA, when the MPU is disabled, the default memory
type is Normal, Non-cachable.
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation
disabled")
Reported-by: Clément Chigot
Signed-off-by: Richard Henderson
Because the three alternatives are monotonic, we don't need
to keep a couple of bitmasks, just identify the strongest
alternative at startup.
Generalize test_buffer_is_zero_next_accel and init_accel
by always defining an accel_table array.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by:
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/util/bufferiszero.c b/util/bufferiszero.c
index c9a7ded016..f9af7841ba 100644
--- a/util/bufferiszero.c
+++
From: Alexander Monakov
Thanks to early checks in the inline buffer_is_zero wrapper, the SIMD
routines are invoked much more rarely in normal use when most buffers
are non-zero. This makes use of AVX512 unprofitable, as it incurs extra
frequency and voltage transition periods during which the
Benchmark each acceleration function vs an aligned buffer of zeros.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tests/bench/bufferiszero-bench.c | 47
tests/bench/meson.build | 1 +
2 files changed, 48 insertions(+)
From: Alexander Monakov
Use of prefetching in bufferiszero.c is quite questionable:
- prefetches are issued just a few CPU cycles before the corresponding
line would be hit by demand loads;
- they are done for simple access patterns, i.e. where hardware
prefetchers can perform better;
-
Split less-than and greater-than 256 cases.
Use unaligned accesses for head and tail.
Avoid using out-of-bounds pointers in loop boundary conditions.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 85 +++--
On 3/5/24 15:49, Paolo Bonzini wrote:
target/ppc/kvm.c calls out to code in hw/ppc/spapr*.c; that code is
not present and fails to link if CONFIG_PSERIES is not enabled.
Adjust kvm.c to depend on CONFIG_PSERIES instead of TARGET_PPC64,
and compile out anything that requires cap_papr, because
On Fri, May 3, 2024 at 10:28 PM Peter Maydell wrote:
>
> On Fri, 19 Apr 2024 at 19:31, Dorjoy Chowdhury wrote:
> >
> > Some ARM CPUs advertise themselves as SMT by having the MT[24] bit set
> > to 1 in the MPIDR register. These CPUs have the thread id in Aff0[7:0]
> > bits, CPU id in Aff1[15:8]
Since v2:
- Introduce softmmu_specific_ss[]
- Fix broken rebased meson in patch 2
Since v1:
- Dropped patch #1 (use meson subdir_done)
Fix a bug introduced during a refactor in commit bb6cf6f016
("accel/tcg: Factor tcg_cpu_reset_hold() out"), affecting
user emulation. (cpu_reset is called during
On Mon, 15 May 2023 at 17:07, Stefan Hajnoczi wrote:
>
> From: Sam Li
>
> Add zoned device option to host_device BlockDriver. It will be presented only
> for zoned host block devices. By adding zone management operations to the
> host_block_device BlockDriver, users can use the new block layer
On 5/3/24 05:51, Fabiano Rosas wrote:
Markus Armbruster writes:
Fabiano Rosas writes:
From: Peter Xu
Peter missed the Sphinx HMP document for the "resume/-r" flag in commit
7a4da28b26 ("qmp: hmp: add migrate "resume" option"). Add it. Avoid
adding a Fixes to make life easier for the
On Fri, May 03, 2024 at 04:04:25PM +0200, Cédric Le Goater wrote:
> However, have you considered another/complementary approach which
> would be to create an host IOMMU (iommufd) backend object and a vIOMMU
> device object together for each vfio-pci device being plugged in the
> machine ?
>
>
In case of migration, during restore operation, qemu checks config space of the
pci device with the config space in the migration stream captured during save
operation. In case of config space data mismatch, restore operation is failed.
config space check is done in function
On 5/3/24 06:38, Matheus Tavares Bernardino wrote:
On Thu, 2 May 2024 13:00:34 -0700 Richard Henderson
wrote:
On 5/2/24 12:20, Matheus Tavares Bernardino wrote:
+
+void test_multi_cof(void)
+{
+asm volatile(
+"p0 = cmp.eq(r0, r0)\n"
+"{\n"
+"if (p0) jump
The following changes since commit 4977ce198d2390bff8c71ad5cb1a5f6aa24b56fb:
Merge tag 'pull-tcg-20240501' of https://gitlab.com/rth7680/qemu into staging
(2024-05-01 15:15:33 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-misc-20240503
From: Alexander Monakov
The SSE4.1 variant is virtually identical to the SSE2 variant, except
for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing
if an SSE register is all zeroes. The PTEST instruction decodes to two
uops, so it can be handled only by the complex decoder,
From: Alexander Monakov
Test for length >= 256 inline, where is is often a constant.
Before calling into the accelerated routine, sample three bytes
from the buffer, which handles most non-zero buffers.
Signed-off-by: Alexander Monakov
Signed-off-by: Mikhail Romanov
Message-Id:
Because non-embedded aarch64 is expected to have AdvSIMD enabled, merely
double-check with the compiler flags for __ARM_NEON and don't bother with
a runtime check. Otherwise, model the loop after the x86 SSE2 function.
Use UMAXV for the vector reduction. This is 3 cycles on cortex-a76 and
2
From: Alexander Monakov
Increase unroll factor in SIMD loops from 4x to 8x in order to move
their bottlenecks from ALU port contention to load issue rate (two loads
per cycle on popular x86 implementations).
Avoid using out-of-bounds pointers in loop boundary conditions.
Follow SSE2
On Thu, 2 May 2024 at 15:16, Alexandra Diupina wrote:
>
> Add xlnx_dpdma_read_descriptor() and
> xlnx_dpdma_write_descriptor() functions.
> xlnx_dpdma_read_descriptor() combines reading a
> descriptor from desc_addr by calling dma_memory_read()
> and swapping the desc fields from guest memory
On Mon, 26 Jun 2023 at 13:28, Michael S. Tsirkin wrote:
>
> From: Jonathan Cameron
>
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
Hi; Coverity has just spotted what looks like a bug in this
function (CID
On Fri, May 3, 2024 at 2:29 PM Daniel P. Berrangé wrote:
> We have compile coverage of x86_64-softmmu on the cross-win64 mingw
> job. So we're not loosing any compile coverage in aggregate with
> this change, in fact we improve it by compiling sparc here.
>
> The msys2-64bit job currently takes
On Fri, May 03, 2024 at 08:58:09AM +0200, Markus Armbruster wrote:
> Peter Xu writes:
>
> > Peter missed the Sphinx HMP document for the "resume/-r" flag in commit
> > 7a4da28b26 ("qmp: hmp: add migrate "resume" option"). Add it. Avoid
> > adding a Fixes to make life easier for the stable
On 5/3/24 16:10, Jason Gunthorpe wrote:
On Fri, May 03, 2024 at 04:04:25PM +0200, Cédric Le Goater wrote:
However, have you considered another/complementary approach which
would be to create an host IOMMU (iommufd) backend object and a vIOMMU
device object together for each vfio-pci device
"plugin_mask" was renamed as "event_mask" in commit c006147122
("plugins: create CPUPluginState and migrate plugin_mask").
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240427155714.53669-3-phi...@linaro.org>
---
plugins/core.c | 2 +-
1 file changed, 1
To easily compare with the SH4 manual, rename:
REG(B11_8) -> Rn
REG(B7_4) -> Rm
t0 -> result
Mention how overflow is calculated.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Yoshinori Sato
Message-Id: <20240430163125.77430-4-phi...@linaro.org>
---
To easily compare with the SH4 manual, rename:
REG(B11_8) -> Rn
REG(B7_4) -> Rm
t0 -> result
Mention how underflow is calculated.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20240430163125.77430-5-phi...@linaro.org>
---
target/sh4/translate.c | 16
On 5/1/24 20:27, Daniel P. Berrangé wrote:
Thomas proposed a new deprecation and removal policy for versioned
machine types that would see them liable for deletion after 6 years:
https://lists.nongnu.org/archive/html/qemu-devel/2024-04/msg04683.html
This suggest was met with broad approval,
In commit 1b5120d74b ("accel: Introduce cpu_exec_reset_hold()")
we defined the user emulation backend cpu_exec_reset_hold() as
a stub. This was a mistake, since common fields are set in
CPU reset, and user emulation needs these fields to be resetted.
Move cpu_exec_reset_hold() back.
On Fri, May 03, 2024 at 01:14:27PM +0100, Peter Maydell wrote:
> On Wed, 1 May 2024 at 19:28, Daniel P. Berrangé wrote:
> > I wonder, however, whether we would benefit from changing how we
> > update the VERSION file.
> >
> > eg instead of re-using the micro digit to indicate a dev or rc
> >
Some files are specific to system emulation. Move them under
their own sysemu/ directory. This might help to notice what
is affected (user, system or both) when doing global refactors.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/{ => sysemu}/tcg-accel-ops-icount.h | 0
accel/tcg/{ =>
In commit bb6cf6f016 ("accel/tcg: Factor tcg_cpu_reset_hold() out")
we unfortunately restricted the tcg_flush_jmp_cache() to system
emulation. Move it to the common tcg_exec_cpu_reset_hold() handler
so user emulation gets the jmp_cache initialized when threads
are created.
Remove the NULL check
Currently these files are only used in system emulation,
but could eventually be used by user emulation. Use the
"softmmu_specific_ss" to express they are related to
SoftMMU.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/meson.build | 7 +--
1 file changed, 5 insertions(+), 2
On Fri, 16 Jun 2023 at 11:03, Song Gao wrote:
>
> From: Tianrui Zhao
>
> 1. Implement some functions for LoongArch numa support;
> 2. Implement fdt_add_memory_node() for fdt;
> 3. build_srat() fills node_id and adds build numa memory.
>
> Reviewed-by: Song Gao
> Signed-off-by: Tianrui Zhao
>
Markus Armbruster writes:
> Fabiano Rosas writes:
>
>> From: Peter Xu
>>
>> Peter missed the Sphinx HMP document for the "resume/-r" flag in commit
>> 7a4da28b26 ("qmp: hmp: add migrate "resume" option"). Add it. Avoid
>> adding a Fixes to make life easier for the stable maintainer.
>>
>>
From: Madhavan T. Venkataraman
Hypervisor Enforced Kernel Integrity (Heki) is a feature that will use
the hypervisor to enhance guest virtual machine security.
Implement minimal code to introduce Heki:
- Define the config variables.
- Define a kernel command line parameter "heki" to turn the
This enables guests to lock their CR0 and CR4 registers with a subset of
X86_CR0_WP, X86_CR4_SMEP, X86_CR4_SMAP, X86_CR4_UMIP, X86_CR4_FSGSBASE
and X86_CR4_CET flags.
The new KVM_HC_LOCK_CR_UPDATE hypercall takes three arguments. The
first is to identify the control register, the second is a bit
Hi,
This patch series implements control-register (CR) pinning for KVM and
provides an hypervisor-agnostic API to protect guests. It includes the
guest interface, the host interface, and the KVM implementation.
It's not ready for mainline yet (see the current limitations), but we
think the
The hypervisor needs to provide some functions to support Heki. These
form the Heki-Hypervisor API.
Define a heki_hypervisor structure to house the API functions. A
hypervisor that supports Heki must instantiate a heki_hypervisor
structure and pass it to the Heki common code. This allows the
target/ppc/kvm.c calls out to code in hw/ppc/spapr*.c; that code is
not present and fails to link if CONFIG_PSERIES is not enabled.
Adjust kvm.c to depend on CONFIG_PSERIES instead of TARGET_PPC64,
and compile out anything that requires cap_papr, because only
the pseries machine will call
On Fri, May 03, 2024, Mickaël Salaün wrote:
> Hi,
>
> This patch series implements control-register (CR) pinning for KVM and
> provides an hypervisor-agnostic API to protect guests. It includes the
> guest interface, the host interface, and the KVM implementation.
>
> It's not ready for
On 4/29/24 08:50, Zhenzhong Duan wrote:
Hi,
The most important change in this version is instroducing a common
HostIOMMUDeviceCaps structure in HostIOMMUDevice and a new interface
between vIOMMU and HostIOMMUDevice.
HostIOMMUDeviceClass::realize() is introduced to initialize
If there's still time, suggest to tweak the subject to
hmp/migration: Fix "migrate" command's documentation
Peter Xu writes:
> On Fri, May 03, 2024 at 08:58:09AM +0200, Markus Armbruster wrote:
>> Peter Xu writes:
>>
>> > Peter missed the Sphinx HMP document for the "resume/-r" flag in
On 4/30/24 10:51, Jamin Lin wrote:
Hi Cedric,
On 4/19/24 15:41, Cédric Le Goater wrote:
On 4/16/24 11:18, Jamin Lin wrote:
DMA length is from 1 byte to 32MB for AST2600 and AST10x0 and DMA
length is from 4 bytes to 32MB for AST2500.
In other words, if "R_DMA_LEN" is 0, it should move at
On 24/4/24 19:09, Richard Henderson wrote:
This may be treated as a 32-bit EQ/NE comparison against 0,
which is in turn treated as a LTU/GEU comparison against 1.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 17 +++--
1 file changed, 15 insertions(+), 2
We wrongly encoded ID_AA64PFR1_EL1 using {3,0,0,4,2} in hvf_sreg_match[] so
we fail to get the expected ARMCPRegInfo from cp_regs hash table with the
wrong key.
Fix it with the correct encoding {3,0,0,4,1}. With that fixed, the Linux
guest can properly detect FEAT_SSBS2 on my M1 HW.
All
Hi Philippe,
> From: Philippe Mathieu-Daudé
> Sent: Friday, May 3, 2024 10:40 AM
> Subject: Re: [PATCH V8 1/8] accel/kvm: Extract common KVM vCPU
> {creation,parking} code
>
> Hi Salil,
>
> On 12/3/24 02:59, Salil Mehta wrote:
> > KVM vCPU creation is done once during the vCPU
On Fri, 19 Apr 2024 at 19:31, Dorjoy Chowdhury wrote:
>
> Some ARM CPUs advertise themselves as SMT by having the MT[24] bit set
> to 1 in the MPIDR register. These CPUs have the thread id in Aff0[7:0]
> bits, CPU id in Aff1[15:8] bits and cluster id in Aff2[23:16] bits in
> MPIDR.
>
> On the
On Fri, May 3, 2024 at 11:17 AM Philippe Mathieu-Daudé
wrote:
>
> If CONFIG_TCG is not defined, skip this directory calling
> subdir_done(). Then since we know CONFIG_TCG is defined,
> we don't need to check for it.
You can only remove the check if you assume that TCG (unlike e.g. KVM)
is
sparc-softmmu is able to run a subset of qtests when compiled
--without-default-devices,
so use it instead of x86_64-softmmu for the msys2 run.
Signed-off-by: Paolo Bonzini
---
.gitlab-ci.d/windows.yml | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
On 3/5/24 13:16, Paolo Bonzini wrote:
On Fri, May 3, 2024 at 11:17 AM Philippe Mathieu-Daudé
wrote:
If CONFIG_TCG is not defined, skip this directory calling
subdir_done(). Then since we know CONFIG_TCG is defined,
we don't need to check for it.
You can only remove the check if you assume
On 3/5/24 14:25, Philippe Mathieu-Daudé wrote:
Some files are specific to system emulation. Move them under
their own sysemu/ directory. This might help to notice what
is affected (user, system or both) when doing global refactors.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/{ =>
On 30/4/24 18:31, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (4):
target/sh4: Fix ADDV opcode
target/sh4: Fix SUBV opcode
target/sh4: Rename TCGv variables as manual for ADDV opcode
target/sh4: Rename TCGv variables as manual for SUBV opcode
Series queued, thanks.
Peter missed the Sphinx HMP document for the "resume/-r" flag in commit
7a4da28b26 ("qmp: hmp: add migrate "resume" option"). Add it.
When at it, slightly cleanup the lines around:
- Move "detach/-d" to a separate section rather than appending it at the
end of the command description. Add a
On Fri, Apr 26, 2024 at 11:20:35AM -0300, Fabiano Rosas wrote:
> When the migration using the "file:" URI was implemented, I don't
> think any of us noticed that if you pass in a file name with the
> format "/dev/fdset/N", this allows a file descriptor to be passed in
> to QEMU and that behaves
Hi Vishnu,
> From: Vishnu Pajjuri
> Sent: Thursday, April 4, 2024 3:00 PM
> Subject: Re: [PATCH V8 1/8] accel/kvm: Extract common KVM vCPU
> {creation,parking} code
>
> Hi Salil,
>> On 12-03-2024 07:29, Salil Mehta wrote:
>> KVM vCPU creation is done once during the vCPU realization
qga/commands-posix.c does not compile on FreeBSD due to a confusion
between "chpasswdata" (wrong) and "chpasswddata" (used in the #else
branch).
Signed-off-by: Paolo Bonzini
---
qga/commands-posix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qga/commands-posix.c
Depending on the phase of the moon, this seems to be causing CI failures on
FreeBSD.
Fortunately, valgrind catches it too, and in a fully deterministic way:
==210026== Invalid write of size 4
==210026==at 0x5222F3: stm32l4x5_lpuart_class_init (stm32l4x5_usart.c:611)
==210026==by
On Fri, May 03, 2024 at 08:40:03AM +0200, Jinpu Wang wrote:
> I had a brief check in the rsocket changelog, there seems some
> improvement over time,
> might be worth revisiting this. due to socket abstraction, we can't
> use some feature like
> ODP, it won't be a small and easy task.
It'll be
On 25/4/24 01:31, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
accel/tcg/plugin-gen.c | 1 +
2 files changed, 2 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On Wed, 1 May 2024 at 19:28, Daniel P. Berrangé wrote:
> I wonder, however, whether we would benefit from changing how we
> update the VERSION file.
>
> eg instead of re-using the micro digit to indicate a dev or rc
> snapshot, represent those explicitly. eg "9.1.0-dev" and
> "9.1.0-rc1",
Introduce a method called by cpu_reset(), common
to both system and user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-common.h | 2 ++
accel/tcg/cpu-exec.c | 4
accel/tcg/sysemu/tcg-accel-ops.c | 3 ++-
accel/tcg/user-exec.c| 1 +
4
On 5/3/24 05:52, Philippe Mathieu-Daudé wrote:
Keep all user emulation headers under the same user/ directory.
Signed-off-by: Philippe Mathieu-Daudé
---
Forgot to include this patch in "exec: Rework around CPUState user fields"
On Fri, Apr 26, 2024 at 11:20:34AM -0300, Fabiano Rosas wrote:
> We're enabling using the fdset interface to pass file descriptors for
> use in the migration code. Since migrations can happen more than once
> during the VMs lifetime, we need a way to remove an fd from the fdset
> at the end of
On 03/05/2024 19.13, Paolo Bonzini wrote:
qga/commands-posix.c does not compile on FreeBSD due to a confusion
between "chpasswdata" (wrong) and "chpasswddata" (used in the #else
branch).
Signed-off-by: Paolo Bonzini
---
qga/commands-posix.c | 2 +-
1 file changed, 1 insertion(+), 1
On Fri, May 03, 2024 at 01:39:32PM GMT, Aleksei Filippov wrote:
>
>
> On 25.04.2024 12:21, Andrew Jones wrote:
> > On Mon, Apr 22, 2024 at 02:31:36PM +0200, Andrew Jones wrote:
> > > On Mon, Apr 22, 2024 at 02:42:54PM +0300, Alexei Filippov wrote:
> > > > kvm_riscv_handle_sbi() may return not
In commit 1b5120d74b ("accel: Introduce cpu_exec_reset_hold()")
we defined the user emulation backend cpu_exec_reset_hold() as
a stub. This was a mistake, since common fields are set in
CPU reset, and user emulation needs these fields to be resetted.
Move cpu_exec_reset_hold() back.
Some files are specific to system emulation. Move them under
their own sysemu/ directory. This might help to notice what
is affected (user, system or both) when doing global refactors.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/{ => sysemu}/tcg-accel-ops-icount.h | 0
accel/tcg/{ =>
Introduce a method called by cpu_reset(), common
to both system and user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-common.h | 2 ++
accel/tcg/cpu-exec.c | 4
accel/tcg/sysemu/tcg-accel-ops.c | 3 ++-
accel/tcg/user-exec.c| 1 +
4
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