[PATCH 51/57] target/arm: Convert SRHADD, URHADD to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 2 ++ target/arm/tcg/translate-a64.c | 11 +++ 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 80c4c650c9..fc8a5ca14f 100644 ---

[PATCH 34/57] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 11 target/arm/tcg/translate-a64.c | 100 +++-- 2 files changed, 68 insertions(+), 43 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH 23/57] target/arm: Use gvec for neon faddp, fmaxp, fminp

Signed-off-by: Richard Henderson --- target/arm/helper.h | 7 - target/arm/tcg/translate-neon.c | 55 ++--- target/arm/tcg/vec_helper.c | 45 --- 3 files changed, 3 insertions(+), 104 deletions(-) diff --git

Re: [PATCH v3 1/5] hw/loongarch: Rename LOONGARCH_MACHINE with VIRT_MACHINE

On 06/05/2024 05.02, Bibo Mao wrote: On LoongArch system, there is only virt machine type now, name LOONGARCH_MACHINE is confused, rename it with VIRT_MACHINE. Machine name about Other real hw boards can be added in future. Signed-off-by: Bibo Mao --- ... @@ -1245,7 +1244,7 @@ static void

Re: More doc updates needed for new migrate argument @channels

Peter Xu writes: [...] > I also copied qemu-devel starting from now. My bad, I messed that up!

[PULL 01/15] Hexagon (target/hexagon) Analyze reads before writes

From: Taylor Simpson We divide gen_analyze_funcs.py into 3 phases Declare the operands Analyze the register reads Analyze the register writes We also create special versions of ctx_log_*_read for new operands Check that the operand is written before the read This is a precursor

[PULL 03/15] Hexagon (target/hexagon) Enable more short-circuit packets (HVX)

From: Taylor Simpson Look for read-after-write instead of overlap of reads and writes HVX instructions with helpers have pass-by-reference semantics, so we check for overlaps of reads and writes within the same instruction. Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Message-Id:

[PULL 12/15] Hexagon (target/hexagon) Remove uses of op_regs_generated.h.inc

From: Taylor Simpson Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Message-Id: <20240307032327.4799-7-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/decode.c | 55 +++-- target/hexagon/mmvec/decode_ext_mmvec.c | 34

[PULL 13/15] Hexagon (target/hexagon) Remove gen_op_regs.py

From: Taylor Simpson Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Message-Id: <20240307032327.4799-8-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/README | 1 - target/hexagon/gen_op_regs.py | 125 --

[PULL 04/15] Hexagon (target/hexagon) Pass P0 explicitly to helpers that need it

From: Taylor Simpson Rather than reading P0 from the env, pass it explicitly Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Tested-by: Anton Johansson Reviewed-by: Brian Cain Message-Id: <20240214042726.19290-2-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain ---

[PULL 00/15] Hexagon: simplify gen for packets w/o read-after-write

The following changes since commit 248f6f62df073a3b4158fd0093863ab885feabb5: Merge tag 'pull-axp-20240504' of https://gitlab.com/rth7680/qemu into staging (2024-05-04 08:39:46 -0700) are available in the Git repository at: https://github.com/quic/qemu tags/pull-hex-20240505 for you

[PULL 08/15] Hexagon (target/hexagon) Mark new_read_idx in trans functions

From: Taylor Simpson Check that the value matches opcode_reginfo Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Message-Id: <20240307032327.4799-3-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/decode.c | 2 ++

[PULL 02/15] Hexagon (target/hexagon) Enable more short-circuit packets (scalar core)

From: Taylor Simpson Look for read-after-write instead of overlap of reads and writes Here is an example with overalp but no read-after-write: 0x000200fc: 0x38103876 { R0 = add(R0,R1); R6 = add(R6,R7) } BEFORE: 000200fc mov_i32 loc2,$0x0 mov_i32 loc2,r0 add_i32

[PULL 09/15] Hexagon (target/hexagon) Mark dest_idx in trans functions

From: Taylor Simpson Check that the value matches opcode_reginfo/opcode_wregs Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Message-Id: <20240307032327.4799-4-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/decode.c | 2 ++

Re: [PATCH 0/3] virtio-net: Convert feature properties to OnOffAuto

On Wed, May 1, 2024 at 3:20 PM Akihiko Odaki wrote: > > On 2024/04/29 16:05, Michael S. Tsirkin wrote: > > On Sun, Apr 28, 2024 at 04:21:06PM +0900, Akihiko Odaki wrote: > >> Based-on: <20240428-rss-v10-0-73cbaa91a...@daynix.com> > >> ("[PATCH v10 00/18] virtio-net RSS/hash report fixes and

Re: [PATCH 1/3] qapi/vfio: Add VFIO device migration state change QAPI event

Avihai Horon writes: > On 02/05/2024 14:19, Markus Armbruster wrote: >> External email: Use caution opening links or attachments >> >> >> Avihai Horon writes: >> >>> Add a new QAPI event for VFIO device migration state change. This event >>> will be emitted when a VFIO device changes its

Re: [PATCH 1/3] qapi/vfio: Add VFIO device migration state change QAPI event

Avihai Horon writes: > On 01/05/2024 14:50, Joao Martins wrote: >> External email: Use caution opening links or attachments >> >> >> On 30/04/2024 06:16, Avihai Horon wrote: >>> Add a new QAPI event for VFIO device migration state change. This event >>> will be emitted when a VFIO device changes

[PATCH 33/57] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB

This eliminates the last uses of these neon helpers. Incorporate the MO_64 expanders as an option to the vector expander. Signed-off-by: Richard Henderson --- target/arm/helper.h| 17 target/arm/tcg/translate.h | 15 +++ target/arm/tcg/gengvec.c | 116

[PATCH 21/57] target/arm: Convert FADDP to decodetree

This fixes a bug in which scalar half-precision did not diagnose sz == 1 as UNDEFINED. Signed-off-by: Richard Henderson --- target/arm/helper.h| 4 ++ target/arm/tcg/a64.decode | 12 + target/arm/tcg/translate-a64.c | 87 ++

[PATCH 41/57] target/arm: Convert SQRSHL and UQRSHL (register) to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 8 ++ target/arm/tcg/translate.h | 4 +++ target/arm/tcg/neon-dp.decode | 17 ++-- target/arm/tcg/gengvec.c| 24 target/arm/tcg/neon_helper.c| 24

[PATCH 26/57] target/arm: Convert SMAXP, SMINP, UMAXP, UMINP to decodetree

These are the last instructions within handle_simd_3same_pair so remove it. Signed-off-by: Richard Henderson --- target/arm/helper.h| 16 + target/arm/tcg/translate.h | 8 +++ target/arm/tcg/a64.decode | 4 ++ target/arm/tcg/gengvec.c | 48 +

[PATCH 53/57] target/arm: Convert SABA, SABD, UABA, UABD to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 target/arm/tcg/translate-a64.c | 22 ++ 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 9b68444595..e1667775f6 100644

[PATCH 42/57] target/arm: Convert SQRSHL, UQRSHL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 +++ target/arm/tcg/translate-a64.c | 48 -- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH 48/57] target/arm: Convert SHSUB, UHSUB to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 6 -- target/arm/tcg/translate.h | 4 + target/arm/tcg/gengvec.c| 144 target/arm/tcg/neon_helper.c| 27 -- target/arm/tcg/translate-a64.c | 17 ++--

[PULL 10/15] Hexagon (target/hexagon) Mark has_pred_dest in trans functions

From: Taylor Simpson Check that the value matches opcode_wregs Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Message-Id: <20240307032327.4799-5-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/decode.c | 3 +++ target/hexagon/gen_trans_funcs.py | 5

Re: [PATCH v2 11/15] hw/riscv/riscv-iommu: add DBG support

Hi Daniel, Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:05寫道： > > From: Tomasz Jeznach > > DBG support adds three additional registers: tr_req_iova, tr_req_ctl and > tr_response. > > The DBG cap is always enabled. No on/off toggle is provided for it. > > Signed-off-by: Tomasz Jeznach >

Re: [PATCH] Fixes: Indentation using TABs and improve formatting

On 04/05/2024 22.34, Michael Tokarev wrote: 04.05.2024 21:58, Tanmay wrote: Hi, I have attached a patch file that fixes indentation and formatting for some files as listed in https://gitlab.com/qemu-project/qemu/-/issues/373 . it is sort

[PATCH 01/57] target/arm: Split out gengvec.c

Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h |5 + target/arm/tcg/gengvec.c | 1612 target/arm/tcg/translate.c | 1588 --- target/arm/tcg/meson.build |1 + 4 files changed, 1618 insertions(+), 1588

[PATCH 50/57] target/arm: Convert SRHADD, URHADD to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 7 -- target/arm/tcg/translate.h | 4 + target/arm/tcg/gengvec.c| 144 target/arm/tcg/neon_helper.c| 27 -- target/arm/tcg/translate-a64.c | 48 ++-

Re: [PATCH 2/3] vfio/migration: Emit VFIO device migration state change QAPI event

Peter, Fabiano, I'd like to hear your opinion on the issue discussed below. Avihai Horon writes: > On 02/05/2024 13:22, Joao Martins wrote: >> External email: Use caution opening links or attachments >> >> >> On 01/05/2024 13:28, Avihai Horon wrote: >>> On 01/05/2024 14:50, Joao Martins wrote:

[PATCH 57/57] target/arm: Convert SQDMULH, SQRDMULH to decodetree

These are the last instructions within disas_simd_three_reg_same and disas_simd_scalar_three_reg_same, so remove them. Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 ++ target/arm/tcg/a64.decode | 18 +++ target/arm/tcg/translate-a64.c | 276

[PATCH 52/57] target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 target/arm/tcg/translate-a64.c | 22 ++ 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index fc8a5ca14f..9b68444595 100644

[PATCH 40/57] target/arm: Convert SQSHL, UQSHL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 ++ target/arm/tcg/translate-a64.c | 74 ++ 2 files changed, 53 insertions(+), 25 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 6f55e0e300..9f5ea9223d

[PATCH 47/57] target/arm: Convert SHADD, UHADD to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 2 ++ target/arm/tcg/translate-a64.c | 11 +++ 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index d97390cacb..0881f00ecf 100644 ---

[PATCH 08/57] target/arm: Convert Cryptographic 4-register to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 8 ++ target/arm/tcg/translate-a64.c | 132 +++-- 2 files changed, 51 insertions(+), 89 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH 04/57] target/arm: Convert Cryptographic 3-register SHA to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 11 + target/arm/tcg/translate-a64.c | 78 +- 2 files changed, 21 insertions(+), 68 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH 55/57] target/arm: Convert MLA, MLS to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 8 target/arm/tcg/translate-a64.c | 77 ++ 2 files changed, 31 insertions(+), 54 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH 49/57] target/arm: Convert SHSUB, UHSUB to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 2 ++ target/arm/tcg/translate-a64.c | 11 +++ 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 0881f00ecf..80c4c650c9 100644 ---

[PATCH 46/57] target/arm: Convert SHADD, UHADD to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 6 -- target/arm/tcg/translate.h | 5 ++ target/arm/tcg/gengvec.c| 144 target/arm/tcg/neon_helper.c| 27 -- target/arm/tcg/translate-a64.c | 17 ++--

[PATCH 56/57] target/arm: Tidy SQDMULH, SQRDMULH (vector)

We already have a gvec helper for the operations, but we aren't using it on the aa32 neon side. Create a unified expander for use by both aa32 and aa64 translators. Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 4 target/arm/tcg/gengvec.c| 20

[PATCH 44/57] target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 12 +++ target/arm/tcg/translate-a64.c | 132 - 2 files changed, 60 insertions(+), 84 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH 27/57] target/arm: Use gvec for neon pmax, pmin

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-neon.c | 78 ++--- 1 file changed, 4 insertions(+), 74 deletions(-) diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c index 6c5a7a98e1..18b048611b 100644 ---

RE: [PATCH intel_iommu 0/7] FLTS for VT-d

Hi Clement, Sorry for late response, just back from vacation. I saw your rebased version and thanks for your work. I'll schedule a timeslot to review them. Thanks Zhenzhong >-Original Message- >From: CLEMENT MATHIEU--DRIF >Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d > >Hi

Re: [PATCH 4/4] tests/qtest: Check STM32L4x5 clock connections

On 05/05/2024 16.05, Inès Varhol wrote: For USART, GPIO and SYSCFG devices, check that clock frequency before and after enabling the peripheral clock in RCC is correct. Signed-off-by: Inès Varhol --- Hello, Should these tests be regrouped in stm32l4x5_rcc-test.c ? Hi, sounds mostly like a

RE: [PATCH v1 0/2] Upgrade ACPI SPCR table to support SPCR table version 4 format

> -Original Message- > From: Peter Maydell > Sent: Thursday, May 2, 2024 5:19 PM > To: JeeHeng Sia > Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; qemu-ri...@nongnu.org; > m...@redhat.com; imamm...@redhat.com; > anisi...@redhat.com; shannon.zha...@gmail.com;

[PATCH 14/57] target/arm: Convert FMAX, FMIN, FMAXNM, FMINNM to decodetree

Signed-off-by: Richard Henderson --- target/arm/helper.h| 4 + target/arm/tcg/a64.decode | 17 target/arm/tcg/translate-a64.c | 168 + target/arm/tcg/vec_helper.c| 4 + 4 files changed, 113 insertions(+), 80 deletions(-) diff --git

[PATCH 37/57] target/arm: Convert SRSHL and URSHL (register) to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 10 + target/arm/tcg/translate.h | 4 target/arm/tcg/neon-dp.decode | 10 ++--- target/arm/tcg/gengvec.c| 22 +++ target/arm/tcg/neon_helper.c| 38

[PATCH 13/57] target/arm: Convert FADD, FSUB, FDIV, FMUL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/helper-a64.h| 4 + target/arm/tcg/translate.h | 5 + target/arm/tcg/a64.decode | 27 + target/arm/tcg/translate-a64.c | 205 + target/arm/tcg/vec_helper.c| 4 + 5 files changed, 143

[PATCH v5] target/riscv: Implement dynamic establishment of custom decoder

In this patch, we modify the decoder to be a freely composable data structure instead of a hardcoded one. It can be dynamically builded up according to the extensions. This approach has several benefits: 1. Provides support for heterogeneous cpu architectures. As we add decoder in RISCVCPU,

[PATCH 32/57] target/arm: Inline scalar SUQADD and USQADD

This eliminates the last uses of these neon helpers. Incorporate the MO_64 expanders as an option to the vector expander. Signed-off-by: Richard Henderson --- target/arm/helper.h| 8 -- target/arm/tcg/translate-a64.h | 8 ++ target/arm/tcg/gengvec64.c | 71 ++

[PATCH 31/57] target/arm: Convert SUQADD and USQADD to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h| 16 + target/arm/tcg/translate-a64.h | 6 ++ target/arm/tcg/gengvec64.c | 106 +++ target/arm/tcg/translate-a64.c | 113 ++--- target/arm/tcg/vec_helper.c|

[PATCH 30/57] target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB

No need for a full comparison; xor produces non-zero bits for QC just fine. Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c

[PATCH 07/57] target/arm: Convert Cryptographic 2-register SHA512 to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 5 target/arm/tcg/translate-a64.c | 50 ++ 2 files changed, 8 insertions(+), 47 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH 19/57] target/arm: Convert FABD to decodetree

Signed-off-by: Richard Henderson --- target/arm/helper.h| 1 + target/arm/tcg/a64.decode | 6 target/arm/tcg/translate-a64.c | 60 ++ target/arm/tcg/vec_helper.c| 6 4 files changed, 53 insertions(+), 20 deletions(-) diff --git

[PATCH 35/57] target/arm: Convert SUQADD, USQADD to decodetree

These are faux 2-operand instructions, reading from rd. Sort them next to the other three-operand same insns for clarity. Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 8 + target/arm/tcg/translate-a64.c | 64 -- 2 files changed, 14

[PATCH 45/57] target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32,i64}

Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index 51e66ccf5f..1d6bc6021d 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg/gengvec.c @@ -933,14

[PATCH 18/57] target/arm: Convert FCMEQ, FCMGE, FCMGT, FACGE, FACGT to decodetree

Signed-off-by: Richard Henderson --- target/arm/helper.h| 5 + target/arm/tcg/a64.decode | 30 ++ target/arm/tcg/translate-a64.c | 188 +++-- target/arm/tcg/vec_helper.c| 30 ++ 4 files changed, 174 insertions(+), 79 deletions(-) diff

[PATCH 02/57] target/arm: Split out gengvec64.c

Split some routines out of translate-a64.c and translate-sve.c that are used by both. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.h | 4 + target/arm/tcg/gengvec64.c | 190 + target/arm/tcg/translate-a64.c | 26 -

[PATCH v3 5/5] tests: Add migration test for loongarch64

This patch adds migration test support for loongarch64. The test code comes from aarch64 mostly, only that it booted as bios in qemu since kernel requires elf format and bios uses binary format. In addition to providing the binary, this patch also includes the source code and the build script in

[PATCH v3 2/5] hw/loongarch: Rename LoongArchMachineState with VirtMachineState

Rename LoongArchMachineState with VirtMachineState, and change variable name LoongArchMachineState *lams with VirtMachineState *vms, and rename function loongarch_xxx() with virt_xxx() also. Signed-off-by: Bibo Mao --- hw/loongarch/acpi-build.c | 80 +- hw/loongarch/boot.c |

[PATCH v3 3/5] hw/loongarch: Add compat machine for 9.0

Since migration test case requires compat machine type support, compat machine is added for qemu 9.0 here. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 60 +++-- 1 file changed, 47 insertions(+), 13 deletions(-) diff --git a/hw/loongarch/virt.c

[PATCH v3 1/5] hw/loongarch: Rename LOONGARCH_MACHINE with VIRT_MACHINE

On LoongArch system, there is only virt machine type now, name LOONGARCH_MACHINE is confused, rename it with VIRT_MACHINE. Machine name about Other real hw boards can be added in future. Signed-off-by: Bibo Mao --- hw/loongarch/acpi-build.c | 8 hw/loongarch/boot.c | 2 +-

[PATCH v3 4/5] hw/loongarch: Set minimium memory size as 256M

The minimum memory size for LoongArch UEFI bios is 256M, also some test cases such as migration and qos use 256M memory by default. Here set minimum memory size for Loongarch VirtMachine with 256M rather than 1G, so that test cases with 256M memory can pass to run. Signed-off-by: Bibo Mao ---

[PATCH 03/57] target/arm: Convert Cryptographic AES to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 21 +++-- target/arm/tcg/translate-a64.c | 86 +++--- 2 files changed, 54 insertions(+), 53 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH 28/57] target/arm: Convert FMLAL, FMLSL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 10 +++ target/arm/tcg/translate-a64.c | 144 ++--- 2 files changed, 51 insertions(+), 103 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH v4] target/loongarch: Add TCG macro in structure CPUArchState

In structure CPUArchState some struct elements are only used in TCG mode, and it is not used in KVM mode. Macro CONFIG_TCG is added to make it simpiler in KVM mode, also there is the same modification in c code when these structure elements are used. When VM runs in KVM mode, TLB entries are not

RE: [PATCH v3 00/19] Add a host IOMMU device abstraction to check with vIOMMU

Hi Cédric, >-Original Message- >From: Cédric Le Goater >Sent: Friday, May 3, 2024 10:04 PM >To: Duan, Zhenzhong ; qemu- >de...@nongnu.org >Cc: alex.william...@redhat.com; eric.au...@redhat.com; m...@redhat.com; >pet...@redhat.com; jasow...@redhat.com; j...@nvidia.com;

[PULL 15/15] Hexagon (target/hexagon) Remove hex_common.read_attribs_file

From: Taylor Simpson The attribinfo data structure is not used Adjust the command-line arguments to the python scripts Add hex_common.read_common_files for TCG/helper generation scripts Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Reviewed-by: Philippe Mathieu-Daudé Message-Id:

[PULL 05/15] Hexagon (target/hexagon) Pass SP explicitly to helpers that need it

From: Taylor Simpson Rather than reading SP from the env, pass it explicitly Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Tested-by: Anton Johansson Reviewed-by: Brian Cain Message-Id: <20240214042726.19290-3-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain ---

[PULL 06/15] Hexagon (target/hexagon) Only pass env to generated helper when needed

From: Taylor Simpson Currently, we pass env to every generated helper. When the semantics of the instruction only depend on the arguments, this is unnecessary and adds extra overhead to the helper call. We add the TCG_CALL_NO_RWG_SE flag to any non-HVX helpers that don't get the ptr to env.

Re: [PATCH 6/6] target/i386/confidential-guest: Fix comment of x86_confidential_guest_kvm_type()

Hi Xiaoyao, On Sat, Apr 27, 2024 at 07:05:41AM +0800, Xiaoyao Li wrote: > Date: Sat, 27 Apr 2024 07:05:41 +0800 > From: Xiaoyao Li > Subject: Re: [PATCH 6/6] target/i386/confidential-guest: Fix comment of > x86_confidential_guest_kvm_type() > > On 4/26/2024 6:07 PM, Zhao Liu wrote: > > Update

[PULL 14/15] Hexagon (target/hexagon) Remove gen_shortcode.py

From: Taylor Simpson This data structure is not used Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240307032327.4799-9-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/README | 1 -

[PULL 11/15] Hexagon (tests/tcg/hexagon) Test HVX .new read from high half of pair

From: Taylor Simpson Make sure the decoding of HVX .new is correctly handling this case Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Message-Id: <20240307032327.4799-6-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain --- tests/tcg/hexagon/hvx_misc.c | 16 +++- 1 file

[PULL 07/15] Hexagon (target/hexagon) Add is_old/is_new to Register class

From: Taylor Simpson Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Brian Cain Message-Id: <20240307032327.4799-2-ltaylorsimp...@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 12 1 file changed, 12 insertions(+) diff

[PATCH v3 0/5] Add migration test for loongarch64

Migration test case is added for loongarch64 here. Since compat machine type is required for migration test case, also compat machine qemu 9.0 is added for loongarch virt machine. Migration test case passes to run in both tcg and kvm mode with the patch, 54 migration subtests passes in 188

[PATCH 25/57] target/arm: Use gvec for neon padd

Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/tcg/neon_helper.c| 5 - target/arm/tcg/translate-neon.c | 3 +-- 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index d3579a101f..51ed49aa50

[PATCH 22/57] target/arm: Convert FMAXP, FMINP, FMAXNMP, FMINNMP to decodetree

These are the last instructions within disas_simd_three_reg_same_fp16, so remove it. Signed-off-by: Richard Henderson --- target/arm/helper.h| 16 ++ target/arm/tcg/a64.decode | 24 +++ target/arm/tcg/translate-a64.c | 296 ++---

[PATCH 12/57] target/arm: Convert FMULX to decodetree

Convert all forms (scalar, vector, scalar indexed, vector indexed), which allows us to remove switch table entries elsewhere. Signed-off-by: Richard Henderson --- target/arm/tcg/helper-a64.h| 8 ++ target/arm/tcg/a64.decode | 45 +++ target/arm/tcg/translate-a64.c | 221

[PATCH 43/57] target/arm: Convert ADD, SUB (vector) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 6 ++ target/arm/tcg/translate-a64.c | 34 +++--- 2 files changed, 17 insertions(+), 23 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH 09/57] target/arm: Convert Cryptographic 3-register, imm2 to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 10 target/arm/tcg/translate-a64.c | 43 ++ 2 files changed, 22 insertions(+), 31 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

[PATCH 54/57] target/arm: Convert MUL, PMUL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 5 target/arm/tcg/translate-a64.c | 51 +- 2 files changed, 25 insertions(+), 31 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index

RE: [PATCH v3 11/19] backends/iommufd: Implement HostIOMMUDeviceClass::check_cap() handler

>-Original Message- >From: Cédric Le Goater >Subject: Re: [PATCH v3 11/19] backends/iommufd: Implement >HostIOMMUDeviceClass::check_cap() handler > >> +static int hiod_iommufd_check_cap(HostIOMMUDevice *hiod, int >cap, > Error **errp) >> +{ >> +switch (cap) { >> +

Re: [PATCH 1/6] target/i386/kvm: Add feature bit definitions for KVM CPUID

Hi Zide, On Fri, Apr 26, 2024 at 10:23:27AM -0700, Chen, Zide wrote: > Date: Fri, 26 Apr 2024 10:23:27 -0700 > From: "Chen, Zide" > Subject: Re: [PATCH 1/6] target/i386/kvm: Add feature bit definitions for > KVM CPUID > > On 4/26/2024 3:07 AM, Zhao Liu wrote: > > Add feature definiations for

Re: [PATCH] hvf: arm: Fix encodings for ID_AA64PFR1_EL1 and debug System registers

On 03.05.24 19:34, Zenghui Yu wrote: We wrongly encoded ID_AA64PFR1_EL1 using {3,0,0,4,2} in hvf_sreg_match[] so we fail to get the expected ARMCPRegInfo from cp_regs hash table with the wrong key. Fix it with the correct encoding {3,0,0,4,1}. With that fixed, the Linux guest can properly

[PATCH 4/4] tests/qtest: Check STM32L4x5 clock connections

For USART, GPIO and SYSCFG devices, check that clock frequency before and after enabling the peripheral clock in RCC is correct. Signed-off-by: Inès Varhol --- Hello, Should these tests be regrouped in stm32l4x5_rcc-test.c ? Best regards, Inès Varhol tests/qtest/stm32l4x5_gpio-test.c | 39

[PATCH 1/4] hw/misc: Create STM32L4x5 SYSCFG clock

Signed-off-by: Inès Varhol --- include/hw/misc/stm32l4x5_syscfg.h | 1 + hw/arm/stm32l4x5_soc.c | 2 ++ hw/misc/stm32l4x5_syscfg.c | 26 ++ 3 files changed, 29 insertions(+) diff --git a/include/hw/misc/stm32l4x5_syscfg.h

[PATCH 3/4] hw/char: Add QOM property for STM32L4x5 USART clock frequency

Signed-off-by: Inès Varhol --- hw/char/stm32l4x5_usart.c | 12 1 file changed, 12 insertions(+) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index fc5dcac0c4..ee7727481c 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char/stm32l4x5_usart.c @@ -26,6 +26,7 @@

Re: [PATCH] hvf: arm: Fix encodings for ID_AA64PFR1_EL1 and debug System registers

On 2024/5/5 21:18, Alexander Graf wrote: On 03.05.24 19:34, Zenghui Yu wrote: We wrongly encoded ID_AA64PFR1_EL1 using {3,0,0,4,2} in hvf_sreg_match[] so we fail to get the expected ARMCPRegInfo from cp_regs hash table with the wrong key. Fix it with the correct encoding {3,0,0,4,1}. With

Re: [PATCH] hvf: arm: Fix encodings for ID_AA64PFR1_EL1 and debug System registers

W dniu 3.05.2024 o 17:34, Zenghui Yu pisze: We wrongly encoded ID_AA64PFR1_EL1 using {3,0,0,4,2} in hvf_sreg_match[] so we fail to get the expected ARMCPRegInfo from cp_regs hash table with the wrong key. Fix it with the correct encoding {3,0,0,4,1}. With that fixed, the Linux guest can

Re: PCIE Memory Information

Hi Ashraf, On 04/05/24 12:45, Muzammil Ashraf wrote: Hi All, I am debugging a PCI subsystem. I saw callbacks registered here to catch the pcie config read/write request at hw/pci/pci_host.c:201. How can I make my subregion to overlap this area and How to receive those pcie config read/write

[PATCH 0/4] Check clock connection between STM32L4x5 RCC and peripherals

Among implemented STM32L4x5 devices, USART, GPIO and SYSCFG have a clock source, but none has a corresponding test in QEMU. This patch makes sure that all 3 devices create a clock, have a QOM property to access the clock frequency, and adds QTests checking that clock enable in RCC has the

[PATCH 2/4] hw/gpio: Handle clock migration in STM32L4x5 gpios

Signed-off-by: Inès Varhol --- hw/gpio/stm32l4x5_gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c index 71bf5fddb2..14e6618d30 100644 --- a/hw/gpio/stm32l4x5_gpio.c +++ b/hw/gpio/stm32l4x5_gpio.c @@ -20,6 +20,7 @@ #include

[PATCH] hw/char: Correct STM32L4x5 usart register CR2 field ADD_0 size

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/char/stm32l4x5_usart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index 02f666308c..fc5dcac0c4 100644 --- a/hw/char/stm32l4x5_usart.c +++

Re: [PATCH v8 07/11] virtio-gpu: Support suspension of commands processing

On 2024/05/02 4:02, Dmitry Osipenko wrote: On 4/27/24 08:48, Akihiko Odaki wrote: The VIRTIO_GPU_FILL_CMD() macro returns void and this macro is used by every function processing commands. Changing process_cmd() to return bool will require to change all those functions. Not worthwhile to

Re: [PATCH 2/3] vfio/migration: Emit VFIO device migration state change QAPI event

On 02/05/2024 13:22, Joao Martins wrote: External email: Use caution opening links or attachments On 01/05/2024 13:28, Avihai Horon wrote: On 01/05/2024 14:50, Joao Martins wrote: External email: Use caution opening links or attachments On 30/04/2024 06:16, Avihai Horon wrote: Emit VFIO

Re: [PATCH v8 08/11] virtio-gpu: Handle resource blob commands

On 2024/05/02 4:20, Dmitry Osipenko wrote: On 4/27/24 08:52, Akihiko Odaki wrote: On 2024/04/24 19:30, Dmitry Osipenko wrote: On 4/19/24 12:18, Akihiko Odaki wrote: @@ -61,6 +61,10 @@ struct virtio_gpu_simple_resource {    int dmabuf_fd;    uint8_t *remapped;    +    MemoryRegion

[PATCH] include/exec/cpu-common.h: Rename PAGE_BITS macro to PAGE_RWX

This macro can be used to abbreviate PAGE_READ | PAGE_WRITE | PAGE_EXEC for which PAGE_RWX is a better name and renaming it also shows it is not related to TARGET_PAGE_BITS. Signed-off-by: BALATON Zoltan --- accel/tcg/user-exec.c | 2 +- bsd-user/mmap.c| 6 +++---

Re: [PATCH] Fixes: Indentation using TABs and improve formatting

Hi, I completely agree! This was more of a "NEWCOMERS" issue to help us understand how the patch flow works. I'll take up a trivial issue and work on it instead. Thanks, Tanmay On Sun, 5 May 2024 at 02:05, Michael Tokarev wrote: > 04.05.2024 21:58, Tanmay wrote: > > Hi, > > > > I have

[PATCH v2] MAINTAINERS: Update my email address

From: Bin Meng The old Wind River email address (bin.m...@windriver.com) is no longer available due to an internal infrastructure change within the company. While a new email address (bin.meng...@windriver.com) has been assigned to me, I am unable to find a way to send this patch directly from

Re: [PATCH 1/3] qapi/vfio: Add VFIO device migration state change QAPI event

On 02/05/2024 14:19, Markus Armbruster wrote: External email: Use caution opening links or attachments Avihai Horon writes: Add a new QAPI event for VFIO device migration state change. This event will be emitted when a VFIO device changes its migration state, for example, during migration

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