Re: 回复: Fw: 来自Leo Hou的邮件

On 2023/11/2 12:46, leohou wrote: On 2023/11/2 11:33, leohou1...@gmail.com wrote: On 31/10/23 16:13:32 Philippe Mathieu-Daudé wrote: Hi Leo, On 31/10/23 04:10, Leo Hou wrote: hi , all      Does qemu plan to support CPU heterogeneity? Short answer is yes. When will this be available is

Re: [PATCH v4 33/33] hw/riscv/shakti_c: Check CPU type in machine_run_board_init()

On 11/1/23 17:25, Gavin Shan wrote: Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/shakti_c.c | 11 +-- 1 file

Re: [PATCH v4 32/33] hw/arm: Check CPU type in machine_run_board_init()

On 11/1/23 17:24, Gavin Shan wrote: Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan --- hw/arm/bananapi_m2u.c | 12 ++-- hw/arm/cubieboard.c | 12 ++--

Re: [PATCH v4 31/33] hw/arm/sbsa-ref: Check CPU type in machine_run_board_init()

On 11/1/23 17:24, Gavin Shan wrote: Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Leif Lindholm --- hw/arm/sbsa-ref.c |

Re: [PATCH v4 30/33] hw/arm/virt: Hide host CPU model for tcg

On 11/1/23 17:24, Gavin Shan wrote: The 'host' CPU model isn't available until KVM or HVF is enabled. For example, the following error messages are seen when the guest is started with option '-cpu cortex-a8' on tcg. ERROR:../hw/core/machine.c:1423:is_cpu_type_supported: \ assertion

Re: [PATCH v4 29/33] hw/arm/virt: Check CPU type in machine_run_board_init()

On 11/1/23 17:24, Gavin Shan wrote: Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do the check by ourselves. Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 21 +++--

Re: [PATCH v4 28/33] machine: Print CPU model name instead of CPU type name

On 11/1/23 17:24, Gavin Shan wrote: The names of supported CPU models instead of CPU types should be printed when the user specified CPU type isn't supported, to be consistent with the output from '-cpu ?'. Correct the error messages to print CPU model names instead of CPU type names.

Re: [PATCH v4 27/33] machine: Introduce helper is_cpu_type_supported()

On 11/1/23 17:24, Gavin Shan wrote: The logic, to check if the specified CPU type is supported in machine_run_board_init(), is independent enough. Factor it out into helper is_cpu_type_supported(). machine_run_board_init() looks a bit clean with this. Since we're here, @machine_class is renamed

Re: [PATCH v4 26/33] machine: Use error handling when CPU type is checked

On 11/1/23 17:24, Gavin Shan wrote: QEMU will be terminated if the specified CPU type isn't supported in machine_run_board_init(). The list of supported CPU type names is tracked by mc->valid_cpu_types. The error handling can be used to propagate error messages, to be consistent how the errors

Re: 回复: Fw: 来自Leo Hou的邮件

On 2023/11/2 11:33, leohou1...@gmail.com wrote: On 31/10/23 16:13:32 Philippe Mathieu-Daudé wrote: Hi Leo, On 31/10/23 04:10, Leo Hou wrote: hi , all     Does qemu plan to support CPU heterogeneity? Short answer is yes. When will this be available is yet to be determined, as a lot of

Re: [RFC PATCH 00/18] Map memory at destination .load_setup in vDPA-net migration

On Thu, Oct 19, 2023 at 10:35 PM Eugenio Pérez wrote: > > Current memory operations like pinning may take a lot of time at the > destination. Currently they are done after the source of the migration is > stopped, and before the workload is resumed at the destination. This is a > period where

Re: [PATCH v4 25/33] machine: Constify MachineClass::valid_cpu_types[i]

On 11/1/23 17:24, Gavin Shan wrote: Constify MachineClass::valid_cpu_types[i], as suggested by Richard Henderson. Suggested-by: Richard Henderson Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé --- hw/m68k/q800.c | 2 +- include/hw/boards.h | 2 +- 2 files changed, 2

回复: Fw: 来自Leo Hou的邮件

On 31/10/23 16:13:32 Philippe Mathieu-Daudé wrote: >Hi Leo, > >On 31/10/23 04:10, Leo Hou wrote: >> hi , all >>    Does qemu plan to support CPU heterogeneity? > >Short answer is yes. When will this be available is yet to >be determined, as a lot of work is required. >I'm going to talk

Re: [PATCH] file-posix: fix over-writing of returning zone_append offset

On Mon, Oct 30, 2023 at 04:38:53PM +0900, Naohiro Aota wrote: > raw_co_zone_append() sets "s->offset" where "BDRVRawState *s". This pointer > is used later at raw_co_prw() to save the block address where the data is > written. > > When multiple IOs are on-going at the same time, a later IO's >

Re: [PATCH v6 06/12] target/riscv/tcg: add user flag for profile support

On Tue, Oct 31, 2023 at 3:19 AM Daniel Henrique Barboza wrote: > > > > On 10/30/23 10:28, Daniel Henrique Barboza wrote: > > > > > > On 10/28/23 05:54, Daniel Henrique Barboza wrote: > >> The TCG emulation implements all the extensions described in the > >> RVA22U64 profile, both mandatory and

Re: [PATCH v8 02/19] target/riscv/tcg: do not use "!generic" CPU checks

On Thu, Nov 2, 2023 at 8:13 AM Daniel Henrique Barboza wrote: > > Our current logic in get/setters of MISA and multi-letter extensions > works because we have only 2 CPU types, generic and vendor, and by using > "!generic" we're implying that we're talking about vendor CPUs. When adding > a third

Re: [PATCH v8 01/19] target/riscv: create TYPE_RISCV_VENDOR_CPU

On Thu, Nov 2, 2023 at 7:53 AM Daniel Henrique Barboza wrote: > > We want to add a new CPU type for bare CPUs that will inherit specific > traits of the 2 existing types: > > - it will allow for extensions to be enabled/disabled, like generic > CPUs; > > - it will NOT inherit defaults, like

[PATCH v3 67/88] target/hppa: Implement HSHLADD, HSHRADD

Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/insns.decode | 12 ++-- target/hppa/op_helper.c | 32 target/hppa/translate.c | 32 4 files changed, 76 insertions(+), 2 deletions(-)

回复: 来自Leo Hou的邮件

hi , all   Does qemu plan to support CPU heterogeneity?

[PATCH v3 73/88] include/hw/elf: Remove truncating signed casts

There's nothing about elf that specifically requires signed vs unsigned. This is very much a target-specific preference. In the meantime, casting low and high from uint64_t back to Elf_SWord to uint64_t discards high bits that might have been set by translate_fn. Signed-off-by: Richard Henderson

[PATCH v3 86/88] hw/hppa: Turn on 64-bit CPU for C3700 machine

From: Helge Deller Signed-off-by: Helge Deller --- hw/hppa/machine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 43c7afb89d..da9ca85806 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -696,7 +696,7 @@ static void

[PATCH v3 58/88] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections

Remove all but those intended to change type to or from i64. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 910 ++-- 1 file changed, 406 insertions(+), 504 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index

[PATCH v3 88/88] hw/hppa: Map PDC ROM and I/O memory area into lower memory

From: Helge Deller When running a 64-bit CPU in 32-bit mode (e.g. when using a 32-bit kernel) the PDC ROM and I/O area has to be accessible in the 0xf000 memory region. Signed-off-by: Helge Deller --- hw/hppa/machine.c | 15 +++ 1 file changed, 15 insertions(+) diff --git

Re: [PATCH 1/1] MAINTAINERS: update mail address for Weiwei Li

On Mon, Oct 30, 2023 at 6:17 PM Weiwei Li wrote: > > My Iscas mail account will be disabled soon, change to my personal > gmail account. > > Signed-off-by: Weiwei Li Thanks! I hope you can continue working on QEMU :) Applied to riscv-to-apply.next Alistair > --- > MAINTAINERS | 2 +- > 1

[PATCH v3 45/88] target/hppa: Decode d for bb instructions

Manipulate the shift count so that the bit to be tested is always placed at the MSB. Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 4 ++-- target/hppa/translate.c | 6 ++ 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/hppa/insns.decode

[PATCH v3 71/88] target/hppa: Precompute zero into DisasContext

Reduce the number of times we look for the constant 0. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 34 ++ 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/target/hppa/translate.c

[PATCH v3 61/88] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 162 1 file changed, 82 insertions(+), 80 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ce8d812e04..59d172f355 100644 --- a/target/hppa/translate.c +++

[PATCH v3 70/88] target/hppa: Fix interruption based on default PSW

From: Helge Deller The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson ---

[PATCH v3 35/88] target/hppa: Pass d to do_sed_cond

Hoist the resolution of d up one level above do_sed_cond. The MOVB comparison and the existing shift/extract/deposit are all 32-bit. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git

[PATCH v3 06/88] target/hppa: Populate an interval tree with valid tlb entries

Complete the data structure conversion started earlier. This reduces the perf overhead of hppa_get_physical_address from ~5% to ~0.25%. Signed-off-by: Richard Henderson --- target/hppa/cpu.h| 24 +- target/hppa/cpu.c| 2 + target/hppa/machine.c| 51 -

[PATCH v3 68/88] target/hppa: Implement MIXH, MIXW

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 5 target/hppa/translate.c | 55 2 files changed, 60 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 87db726d9e..22ec07f892 100644 ---

Re: [PATCH v5 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT

On Mon, Oct 30, 2023 at 11:23 PM Sunil V L wrote: > > This series primarily enables external interrupt controllers (AIA and PLIC) > in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and > MMU related information. > > Below ECRs for these changes are approved by ASWG and will

[PATCH v3 80/88] target/hppa: Add unwind_breg to CPUHPPAState

Fill in the insn_start value during form_gva, and copy it out to the env field in hppa_restore_state_to_opc. The value is not yet consumed. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 8 +++- target/hppa/cpu.c | 1 + target/hppa/translate.c | 13 - 3

[PATCH v3 85/88] hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory

From: Helge Deller The CPU HPA is in the high F-region on PA2.0 CPUs, so use F_EXTEND() to trigger interrupt request at the right CPU HPA address. Note that the cpu_hpa value comes out of the IRT, which doesn't store the higher addresss bits. Signed-off-by: Helge Deller ---

[PATCH v3 53/88] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 2 ++ target/hppa/translate.c | 6 ++ 2 files changed, 8 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 6f0c3f6ea5..ba7731b517 100644 --- a/target/hppa/insns.decode +++

[PATCH v3 43/88] target/hppa: Decode d for add instructions

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 16 target/hppa/translate.c | 21 +++-- 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index d4a03b0299..0f29869949 100644 ---

[PATCH v3 64/88] target/hppa: Implement HSUB

Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/insns.decode | 4 target/hppa/op_helper.c | 32 target/hppa/translate.c | 15 +++ 4 files changed, 53 insertions(+) diff --git a/target/hppa/helper.h

Re: [PATCH v2 00/14] Update RISC-V vector crypto to ratified v1.0.0

On Fri, Oct 27, 2023 at 1:19 AM Max Chou wrote: > > This patchset updates the RISC-V vector cryptography support to the > ratified version v1.0.0 (commit 1769c26, released on 2023/10). > > v2: > > - Fixed the instruction order at disassembler part. > - Fixed the vror.vi disassembler format. > -

[PATCH v3 56/88] hw/hppa: Use uint32_t instead of target_ureg

The size of target_ureg is going to change. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- hw/hppa/machine.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 85682e6bab..1f09b4b490 100644 ---

[PATCH v3 76/88] target/hppa: Implement pa2.0 data prefetch instructions

These are aliased onto the normal integer loads to %g0. Since we don't emulate caches, prefetch is a nop. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c

[PATCH v3 59/88] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections

The conversions to/from i64 can be eliminated entirely, folding computation into adjacent operations. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 46 - 1 file changed, 13 insertions(+), 33 deletions(-) diff --git

[PATCH v3 47/88] target/hppa: Decode CMPIB double-word

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 10 -- target/hppa/translate.c | 11 ++- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index fc327e2bb3..48f09c9b06 100644 ---

[PATCH v3 83/88] target/hppa: Improve interrupt logging

Signed-off-by: Richard Henderson --- target/hppa/int_helper.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 54875442e7..467ee7daf5 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@

[PATCH v3 57/88] target/hppa: Remove TARGET_REGISTER_BITS

Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20. Signed-off-by: Richard Henderson --- target/hppa/cpu-param.h | 1 - target/hppa/cpu.h| 50 --- target/hppa/helper.h | 51 +-- target/hppa/cpu.c| 2 +- target/hppa/helper.c | 32 +++

[PATCH v3 03/88] target/hppa: Use IntervalTreeNode in HPPATLBEntry

Replace the va_b and va_b fields with the interval tree node. The actual interval tree is not yet used. Signed-off-by: Richard Henderson --- target/hppa/cpu.h| 5 +++-- target/hppa/machine.c| 6 +++--- target/hppa/mem_helper.c | 31 +-- 3 files changed,

[PATCH v3 48/88] target/hppa: Decode ADDB double-word

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7f767fea64..1b4fa401ba 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3143,6 +3143,17 @@

[PATCH v3 05/88] target/hppa: Split out hppa_flush_tlb_range

Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 39 --- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 60cae646cc..828cceb29c 100644 --- a/target/hppa/mem_helper.c +++

[PATCH v3 34/88] target/hppa: Pass d to do_log_cond

Hoist the resolution of d up one level above do_log_cond. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 48 - 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index

[PATCH v3 72/88] target/hppa: Return zero for r0 from load_gpr

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5d780bcf56..3d8240ea7d 100644 --- a/target/hppa/translate.c +++

[PATCH v3 87/88] hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only

From: Helge Deller Prevent that users try to boot a 64-bit only C3700 machine with a 32-bit CPU, and to boot a 32-bit only B160L machine with a 64-bit CPU. Signed-off-by: Helge Deller --- hw/hppa/machine.c | 24 1 file changed, 24 insertions(+) diff --git

[PATCH v3 49/88] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 15 +++ target/hppa/translate.c | 4 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 48f09c9b06..33eec3f4c3 100644 ---

[PATCH v3 41/88] target/hppa: Decode d for unit instructions

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 14 +++--- target/hppa/translate.c | 25 - 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 26ca9f1063..03b1a11cac 100644 ---

[PATCH v3 82/88] target/hppa: Update IIAOQ, IIASQ for pa2.0

These registers have a different format for pa2.0. Signed-off-by: Richard Henderson --- target/hppa/int_helper.c | 46 target/hppa/sys_helper.c | 10 + 2 files changed, 38 insertions(+), 18 deletions(-) diff --git a/target/hppa/int_helper.c

[PATCH v3 81/88] target/hppa: Create raise_exception_with_ior

Handle pa2.0 logic for filling in ISR+IOR. Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 64 1 file changed, 51 insertions(+), 13 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index

[PATCH v3 75/88] linux-user/hppa: Drop EXCP_DUMP from handled exceptions

Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 4 1 file changed, 4 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 8ab1335106..d5232f37fe 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -147,12 +147,10

[PATCH v3 42/88] target/hppa: Decode d for cmpclr instructions

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 6 -- target/hppa/translate.c | 11 +-- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 03b1a11cac..d4a03b0299 100644 ---

[PATCH v3 54/88] target/hppa: Implement STDBY

Signed-off-by: Richard Henderson --- target/hppa/helper.h | 5 ++ target/hppa/insns.decode | 1 + target/hppa/op_helper.c | 178 +-- target/hppa/translate.c | 31 +++ 4 files changed, 210 insertions(+), 5 deletions(-) diff --git

[PATCH v3 44/88] target/hppa: Decode d for sub instructions

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 12 ++-- target/hppa/translate.c | 22 +++--- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 0f29869949..ad454adcbb 100644 ---

[PATCH v3 37/88] linux-user/hppa: Fixes for TARGET_ABI32

Avoid target_ulong and use abi_* types. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/hppa/signal.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/linux-user/hppa/signal.c b/linux-user/hppa/signal.c index 17920e9ceb..d08a97dae6

[PATCH v3 46/88] target/hppa: Decode d for cmpb instructions

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 9 +++-- target/hppa/translate.c | 12 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index b185523021..fc327e2bb3 100644 ---

[PATCH v3 55/88] target/hppa: Implement IDTLBT, IITLBT

Rename the existing insert tlb helpers to emphasize that they are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0. Still missing is the new 'P' tlb bit. Signed-off-by: Richard Henderson --- target/hppa/helper.h | 6 ++-- target/hppa/insns.decode | 4 +++ target/hppa/mem_helper.c |

[PATCH v3 50/88] target/hppa: Implement DEPD, DEPDI

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 19 -- target/hppa/translate.c | 80 +++- 2 files changed, 69 insertions(+), 30 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 33eec3f4c3..12684b590e

[PATCH v3 74/88] hw/hppa: Translate phys addresses for the cpu

Hack the machine to use pa2.0 physical layout when required, using the PSW.W=0 absolute to physical mapping. Signed-off-by: Richard Henderson --- hw/hppa/machine.c | 117 -- 1 file changed, 71 insertions(+), 46 deletions(-) diff --git

[PATCH v3 63/88] target/hppa: Implement HADD

Signed-off-by: Richard Henderson --- target/hppa/helper.h | 3 +++ target/hppa/insns.decode | 8 +++- target/hppa/op_helper.c | 32 target/hppa/translate.c | 37 + 4 files changed, 79 insertions(+), 1 deletion(-)

[PATCH v3 69/88] target/hppa: Implement PERMH

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 2 ++ target/hppa/translate.c | 29 + 2 files changed, 31 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 22ec07f892..19e537df24 100644 ---

[PATCH v3 79/88] target/hppa: Clear upper bits in mtctl for pa1.x

From: Helge Deller Signed-off-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/translate.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d9595c5c7c..f7621590e4 100644 ---

[PATCH v3 60/88] target/hppa: Adjust vmstate_env for pa2.0 tlb

Split out the tlb to a subsection so that it can be separately versioned -- the format is only partially following the architecture and is partially guided by the qemu implementation. Signed-off-by: Richard Henderson --- target/hppa/machine.c | 93 ++- 1

[PATCH v3 39/88] target/hppa: Remove TARGET_HPPA64

Allow both user-only and system mode to run pa2.0 cpus. Avoid creating a separate qemu-system-hppa64 binary; force the qemu-hppa binary to use TARGET_ABI32. Signed-off-by: Richard Henderson --- configs/targets/hppa-linux-user.mak | 1 + target/hppa/cpu-param.h | 23

[PATCH v3 77/88] target/hppa: Add pa2.0 cpu local tlb flushes

From: Helge Deller The previous decoding misnamed the bit it called "local". Other than the name, the implementation was correct for pa1.x. Rename this field to "tlbe". PA2.0 adds (a real) local bit to PxTLB, and also adds a range of pages to flush in GR[b]. Signed-off-by: Helge Deller

[PATCH v3 40/88] target/hppa: Decode d for logical instructions

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 10 ++ target/hppa/translate.c | 15 +++ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index aebe03ccfd..26ca9f1063 100644 ---

[PATCH v3 51/88] target/hppa: Implement EXTRD

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 7 +-- target/hppa/translate.c | 42 +--- 2 files changed, 36 insertions(+), 13 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 12684b590e..7b51f39b9e

[PATCH v3 16/88] target/hppa: Fix do_add, do_sub for hppa64

Select the proper carry bit for input to the arithmetic and for output for the condition. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 50 ++--- 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/target/hppa/translate.c

[PATCH v3 84/88] hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region

From: Helge Deller Map Astro into high F-region and add alias for 32-bit OS in low region. Signed-off-by: Helge Deller --- hw/pci-host/astro.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 4b2d7caf2d..df61386bd9

[PATCH v3 32/88] target/hppa: Pass d to do_cond

Hoist the resolution of d up one level above do_cond. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 82 +++-- 1 file changed, 54 insertions(+), 28 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index

[PATCH v3 00/88] target/hppa: Implement hppa64 cpu

This is the pa2.0 cpu that should populate Helge's C3700 workstation. I have adjusted both user and system binaries to always support the 64-bit cpu but default to the 32-bit cpu. Changes for v3: * Rebased. * Improve TLB lookups and flushing: - Separate PSW.P mmu_idx, so that we don't

[PATCH v3 01/88] target/hppa: Include PSW_P in tb flags and mmu index

Use a separate mmu index for PSW_P enabled vs disabled. This means we can elide the tlb flush in cpu_hppa_put_psw when PSW_P changes. This turns out to be the majority of all tlb flushes. Signed-off-by: Richard Henderson --- target/hppa/cpu.h| 36

[PATCH v3 13/88] target/hppa: Fix load in do_load_32

The destination is TCGv_i32, so use tcg_gen_qemu_ld_i32 not tcg_gen_qemu_ld_reg. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c

[PATCH v3 02/88] target/hppa: Rename hppa_tlb_entry to HPPATLBEntry

Rename to CamelCase per coding style. Signed-off-by: Richard Henderson --- target/hppa/cpu.h| 8 target/hppa/machine.c| 6 +++--- target/hppa/mem_helper.c | 30 +++--- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git

[PATCH v3 78/88] target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system

Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 7132ea221c..602e6c809f 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -480,6

[PATCH v3 52/88] target/hppa: Implement SHRPD

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 6 ++- target/hppa/translate.c | 97 2 files changed, 72 insertions(+), 31 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 7b51f39b9e..6f0c3f6ea5 100644

[PATCH v3 33/88] target/hppa: Pass d to do_sub_cond

Hoist the resolution of d up one level above do_sub_cond. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 77 ++--- 1 file changed, 49 insertions(+), 28 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index

[PATCH v3 62/88] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 59d172f355..f570b17ecd 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1338,10

[PATCH v3 19/88] target/hppa: Introduce TYPE_HPPA64_CPU

Prepare for the qemu binary supporting both pa10 and pa20 at the same time. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/cpu-qom.h | 1 + target/hppa/cpu.h | 5 + target/hppa/cpu.c | 33 ++---

[PATCH v3 18/88] target/hppa: Fix extrw and depw with sar for hppa64

These are 32-bit operations regardless of processor. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ffa367b91f..ed88f724ce 100644 ---

[PATCH v3 30/88] target/hppa: Mask inputs in copy_iaoq_entry

Ensure that the destination is always a valid GVA offset. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c2db2782f4..cf05d8b6e4 100644 ---

[PATCH v3 66/88] target/hppa: Implement HSHL, HSHR

Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 5 + target/hppa/translate.c | 35 +++ 2 files changed, 40 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 6959555bf3..bb5cd267b0 100644 ---

[PATCH v3 20/88] target/hppa: Make HPPA_BTLB_ENTRIES variable

Depend on hppa_is_pa20. Signed-off-by: Richard Henderson --- target/hppa/cpu.h| 19 +++ hw/hppa/machine.c| 9 +++-- target/hppa/machine.c| 3 ++- target/hppa/mem_helper.c | 40 ++-- 4 files changed, 38 insertions(+),

[PATCH v3 26/88] target/hppa: Fix hppa64 addressing

In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0. In space_select, the bits that choose the space depend on PSW_W. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 7 +++ target/hppa/translate.c | 22 +- 2 files changed, 16

[PATCH v3 15/88] target/hppa: Fix trans_ds for hppa64

This instruction always uses the input carry from bit 32, but produces all 16 output carry bits. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 48 +++-- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/target/hppa/translate.c

[PATCH v3 65/88] target/hppa: Implement HAVG

Signed-off-by: Richard Henderson --- target/hppa/helper.h | 1 + target/hppa/insns.decode | 2 ++ target/hppa/op_helper.c | 14 ++ target/hppa/translate.c | 5 + 4 files changed, 22 insertions(+) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index

[PATCH v3 29/88] target/hppa: Use copy_iaoq_entry for link in do_ibranch

We need to make sure the link is masked properly along the use_nullify_skip path. The other three settings of a link register already use this. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH v3 38/88] target/hppa: Drop attempted gdbstub support for hppa64

There is no support for hppa64 in gdb. Any attempt to provide the data for the larger hppa64 registers results in an error from gdb. Mask CR_SAR writes to the width of the register: 5 or 6 bits. Signed-off-by: Richard Henderson --- target/hppa/gdbstub.c | 32 +--- 1

[PATCH v3 21/88] target/hppa: Implement cpu_list

Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 5 + target/hppa/cpu.c | 24 2 files changed, 29 insertions(+) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 48ddcffb8a..301c82114a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -396,4

[PATCH v3 09/88] target/hppa: Remove get_temp

Replace with tcg_temp_new without recording into ctx. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 76 + 1 file changed, 31 insertions(+), 45 deletions(-) diff --git a/target/hppa/translate.c

[PATCH v3 08/88] tcg: Improve expansion of deposit into a constant

Generalize tcg_gen_deposit_z_* from 0 to any constant. Use this to automatically simplify tcg_gen_deposit_*. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 295 ++- 1 file changed, 174 insertions(+), 121 deletions(-) diff --git

[PATCH v3 17/88] target/hppa: Fix bb_sar for hppa64

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b0cd12a2d0..ffa367b91f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@

[PATCH v3 36/88] target/hppa: Pass d to do_unit_cond

Hoist the resolution of d up one level above do_unit_cond. All computations are logical, and are simplified by using a mask of the correct width, after which the result may be compared with zero. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 20 +++- 1 file

[PATCH v3 23/88] target/hppa: Update cpu_hppa_get/put_psw for hppa64

With 64-bit registers, there are 16 carry bits in the PSW. Clear reserved bits based on cpu revision. Signed-off-by: Richard Henderson --- target/hppa/helper.c | 63 1 file changed, 52 insertions(+), 11 deletions(-) diff --git a/target/hppa/helper.c

[PATCH v3 28/88] target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]

This will be how we ensure that the IAOQ is always valid per PSW.W, therefore all stores to these two variables must be done with this function. Use third argument -1 if the destination is always dynamic, and fourth argument NULL if the destination is always static. Signed-off-by: Richard

[PATCH v3 31/88] target/hppa: sar register allows only 5 bits on 32-bit CPU

From: Helge Deller The sar shift amount register is limited to 5 bits when running a 32-bit CPU. Strip off the remaining bits. The interesting part is, that this register allows to detect at runtime if a physical CPU is capable to execute PA2.0 (64-bit) instructions. Signed-off-by: Helge

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