On Mon, Mar 04, 2024 at 01:28:32PM +0100, Cédric Le Goater wrote:
> @@ -2936,15 +2975,22 @@ void memory_global_dirty_log_start(unsigned int flags)
> trace_global_dirty_changed(global_dirty_tracking);
>
> if (!old_flags) {
> -MEMORY_LISTENER_CALL_GLOBAL(log_global_start,
On 3/5/24 04:32, Peter Xu wrote:
On Mon, Mar 04, 2024 at 01:28:28PM +0100, Cédric Le Goater wrote:
This will help preserving the error set by .save_setup() handlers.
Signed-off-by: Cédric Le Goater
IIUC this is about the next patch. I got fully confused before reading
into the next one.
On Mon, Mar 4, 2024 at 3:45 PM Konstantin Kostiuk wrote:
>
> From: Philippe Mathieu-Daudé
>
> Most of the code base use the 'const' qualifier *before*
> the type being qualified. Use the same style to unify.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Message-ID:
On Mon, Mar 4, 2024 at 3:45 PM Konstantin Kostiuk wrote:
>
> From: Dehan Meng
>
> Add support of Windows Server 2025 in get-osinfo command
>
> Signed-off-by: Dehan Meng
> Message-ID: <20240222152835.72095-4-phi...@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Konstantin
On Mon, Mar 4, 2024 at 3:45 PM Konstantin Kostiuk wrote:
>
> From: Philippe Mathieu-Daudé
>
> ga_get_win_name() iterates over all elements in the arrays by
> checking the 'version' field is non-NULL. Since the arrays are
> guarded by a NULL terminating element, we don't need to specify
> their
On Mon, 4 Mar 2024 at 19:38, Cédric Le Goater wrote:
> This will prepare ground for futur changes adding an Error** argument
* futur -> furure
>
> -static int vmstate_save(QEMUFile *f, SaveStateEntry *se, JSONWriter *vmdesc)
> +static int vmstate_save(QEMUFile *f, SaveStateEntry *se, JSONWriter
"Ho-Ren (Jack) Chuang" writes:
> On Mon, Mar 4, 2024 at 10:36 PM Huang, Ying wrote:
>>
>> "Ho-Ren (Jack) Chuang" writes:
>>
>> > On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote:
>> >>
>> >> "Ho-Ren (Jack) Chuang" writes:
>> >>
>> >> > The memory tiering component in the kernel is
Let fill_context() continue even if it fails to fill contexts of some
CPUs. A dump may still contain valuable information even if it lacks
contexts of some CPUs due to dump corruption or a failure before
starting CPUs.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
This makes elf2dmp more robust against corrupted inputs.
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/addrspace.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/contrib/elf2dmp/addrspace.c b/contrib/elf2dmp/addrspace.c
index e01860d15b07..81295a11534a 100644
---
Not checking PA resolution failure can result in NULL deference.
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/addrspace.c | 46 -
1 file changed, 29 insertions(+), 17 deletions(-)
diff --git a/contrib/elf2dmp/addrspace.c
This resolved UBSan warnings.
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/pdb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
index 1c5051425185..492aca4434c8 100644
--- a/contrib/elf2dmp/pdb.c
+++
Destroy PA space even if paging base couldn't be found, fixing memory
leak.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
contrib/elf2dmp/main.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
index
This removes the need to enumarate QEMUCPUState twice and saves code.
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/qemu_elf.c | 25 -
1 file changed, 8 insertions(+), 17 deletions(-)
diff --git a/contrib/elf2dmp/qemu_elf.c b/contrib/elf2dmp/qemu_elf.c
index
This fixes crashes with truncated dumps.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2202
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/qemu_elf.c | 87 +-
1 file changed, 55 insertions(+), 32 deletions(-)
diff --git
elf2dmp assumes little endian host in many places.
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/contrib/elf2dmp/meson.build b/contrib/elf2dmp/meson.build
index 6707d43c4fa5..046569861f7a 100644
---
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 65dfdc9677e4..d25403f3709b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3583,6 +3583,7 @@ F: util/iova-tree.c
elf2dmp
M: Viktor
rol64() is roubust against too large shift values and fixes UBSan
warnings.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
---
contrib/elf2dmp/main.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
index
They are always evaluated to 1.
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/pdb.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
index 40991f5f4c34..abf17c2e7c12 100644
--- a/contrib/elf2dmp/pdb.c
+++
A common construct in contrib/elf2dmp is to set "err" flag and goto
in error paths. In such a construct, there is only one successful path
while there are several error paths, so it will be more simpler to
initialize "err" flag set, and clear it in the successful path.
Signed-off-by: Akihiko
include/qapi/error.h says:
> We recommend
> * bool-valued functions return true on success / false on failure,
> ...
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/addrspace.h | 6 +--
contrib/elf2dmp/download.h | 2 +-
contrib/elf2dmp/pdb.h | 2 +-
contrib/elf2dmp/qemu_elf.h |
elf2dmp sometimes fails to work with partially corrupted dumps, and also
emits warnings when sanitizers are in use. This series are collections
of changes to improve the situation.
Signed-off-by: Akihiko Odaki
---
Changes in v2:
- Added patch "contrib/elf2dmp: Remove unnecessary err flags".
-
Hi Prasad,
> On Mon, 4 Mar 2024 at 12:19, Zhao Liu wrote:
> > > unsigned maxcpus = config->has_maxcpus ? config->maxcpus : 0;
> >
> > This indicates the default maxcpus is initialized as 0 if user doesn't
> > specifies it.
>
> * 'has_maxcpus' should be set only if maxcpus > 0. If maxcpus == 0,
On 04/03/2024 16.10, Jonathan Cameron wrote:
On Mon, 4 Mar 2024 11:44:06 +0100
Thomas Huth wrote:
When setting GLIB_VERSION_MAX_ALLOWED to GLIB_VERSION_2_58 or higher,
glib adds type safety checks to the g_steal_pointer() macro. This
triggers errors in the ct3_build_cdat_entries_for_mr()
Wire the new NMI and VNMI interrupt line from the GIC to each CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Also add VNMI wire.
---
hw/arm/virt.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c
Enable FEAT_NMI on the 'max' CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Sorted to last.
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst
In vCPU Interface, if the vIRQ has the superpriority property, report
vNMI to the corresponding vPE.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v6:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_cpuif.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff
On 3/4/24 21:49, Fabiano Rosas wrote:
Cédric Le Goater writes:
This will prepare ground for futur changes adding an Error** argument
to the save_setup() handler. We need to make sure that on failure,
set_migrationmode() always sets a new error. See the Rules section in
qapi/error.h.
Cc:
Add the NMIAR CPU interface registers which deal with acknowledging NMI.
When introduce NMI interrupt, there are some updates to the semantics for the
register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it
should return 1022 if the intid has super priority. And for ICC_NMIAR1_EL1
On Mon, Mar 4, 2024 at 10:36 PM Huang, Ying wrote:
>
> "Ho-Ren (Jack) Chuang" writes:
>
> > On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote:
> >>
> >> "Ho-Ren (Jack) Chuang" writes:
> >>
> >> > The memory tiering component in the kernel is functionally useless for
> >> > CPUless
Augment the GICv3's QOM device interface by adding one
new set of sysbus IRQ line, to signal NMI to each CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Add support for VNMI.
---
hw/intc/arm_gicv3_common.c | 6 ++
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
arm_phys_excp_target_el().
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
v3:
- Remove nmi_is_irq flag in
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so the NMI exception trap entry
behave like IRQ. And VNMI(vIRQ with Superpriority) can be raised from the
GIC or come from the hcrx_el2.HCRX_VINMI bit.
Signed-off-by: Jinjie Ruan
On 3/5/24 06:59, Ankit Agrawal wrote:
One thing I forgot.
Please add a test. tests/qtest/bios-tables-test.c
+ relevant table dumps.
Here I need to add a test that creates a vfio-pci device and numa
nodes and link using the acpi-generic-initiator object. One thing
here is that the -device
FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and
HCRX_VFNMI. When the feature is enabled, allow these bits to be written in
HCRX_EL2.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Update the comment for FEAT_NMI in hcrx_write().
- Update the
A PE that implements FEAT_NMI and FEAT_GICv3 also implements
FEAT_GICv3_NMI. A PE that does not implement FEAT_NMI, does not implement
FEAT_GICv3_NMI
So included support FEAT_GICv3_NMI feature as part of virt platform
GIC initialization if FEAT_NMI and FEAT_GICv3 supported.
Signed-off-by: Jinjie
Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for
ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.
If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICH_AP1R_EL2.NMI
bit. In icv_activate_irq() and icv_eoir_write(), the ICH_AP1R_EL2.NMI bit
should be set or clear
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
unconditional write to pc and use raise_exception_ra to unwind.
Signed-off-by:
Add GICR_INMIR0 register and support access GICR_INMIR0.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v6:
- Add Reviewed-by.
v4:
- Make the GICR_INMIR0 implementation more clearer.
---
hw/intc/arm_gicv3_redist.c | 19 +++
hw/intc/gicv3_internal.h | 1 +
2
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
CPU_INTERRUPT_VNMI, both CPSR_I and ISR_IS must be set. With
CPU_INTERRUPT_VFIQ and HCRX_EL2.VFNMI set, both CPSR_F and ISR_FS must be set.
Signed-off-by: Jinjie Ruan
---
v6:
- Verify that HCR_EL2.VF is set before
Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Make the GICD_INMIR implementation more clearer.
- Udpate the commit message.
v3:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_dist.c | 34
In CPU Interface, if the IRQ has the superpriority property, report
NMI to the corresponding PE.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v6:
- Add Reviewed-by.
v4:
- Swap the ordering of the IFs.
v3:
- Remove handling nmi_is_irq flag.
---
hw/intc/arm_gicv3_cpuif.c | 4
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to
ELx, with or without superpriority is masked.
As Richard suggested, place ALLINT bit in PSTATE in env->pstate.
With the change to pstate_read/write, exception entry
and return are automatically handled.
Signed-off-by: Jinjie
Support ALLINT msr access as follow:
mrs , ALLINT// read allint
msr ALLINT, // write allint with imm
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v5:
- Add Reviewed-by.
v4:
- Remove arm_is_el2_enabled() check in allint_check().
- Change to
Added properties to enable FEAT_GICv3_NMI feature, setup distributor
and redistributor registers to indicate NMI support.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v4:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_dist.c | 2 ++
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the
SCTLR_ELx.SPINTMASK bit.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c
A SPI, PPI or SGI interrupt can have a superpriority property. So
maintain superpriority information in PendingIrq and GICR/GICD.
Signed-off-by: Jinjie Ruan
Acked-by: Richard Henderson
---
v3:
- Place this ahead of implement GICR_INMIR.
- Add Acked-by.
---
include/hw/intc/arm_gicv3_common.h |
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
is higher than 0x80, otherwise it is higher than 0x0. And save NMI
super prioirty information in hppi.superprio to deliver NMI exception.
Since both GICR and GICD can deliver NMI, it is both necessary to check
whether the
Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in
ARMv8.8-A and ARM v9.3-A.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Adjust to before the MSR patches.
---
target/arm/internals.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
This only implements the external delivery method via the GICv3.
Signed-off-by: Jinjie Ruan
---
v6:
- env->cp15.hcr_el2 -> arm_hcr_el2_eff().
- env->cp15.hcrx_el2 -> arm_hcrx_el2_eff().
- Not include VF && VFNMI in CPU_INTERRUPT_VNMI.
v4:
- Accept NMI unconditionally for arm_cpu_has_work() but
On 2024/2/29 2:51, Atish Patra wrote:
mhpmeventhX CSRs are available for RV32. The predicate function
should check that first before checking sscofpmf extension.
Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support")
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair
On 2024/2/29 2:51, Atish Patra wrote:
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3
On 05/03/2024 04.21, Xinying Yu wrote:
One more thing, I would ask how do I get the full series patch? Do I copy
the RFC line by line from this link[1]?
For getting patches that you might have missed on the mailing list, I
recommend lore.kernel.org :
On 2024/2/29 2:51, Atish Patra wrote:
Privilege mode filtering can also be emulated for cycle/instret by
tracking host_ticks/icount during each privilege mode switch. This
patch implements that for both cycle/instret and mhpmcounters. The
first one requires Smcntrpmf while the other one
"Ho-Ren (Jack) Chuang" writes:
> On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote:
>>
>> "Ho-Ren (Jack) Chuang" writes:
>>
>> > The memory tiering component in the kernel is functionally useless for
>> > CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the nodes
>> > are lumped
In structure CPUArchState some struct elements are only used in TCG
mode, and it is not used in KVM mode. Macro CONFIG_TCG is added to
make it simpiler in KVM mode, also there is the same modification
in c code when these struct elements are used.
When VM runs in KVM mode, TLB entries are not
On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote:
>
> "Ho-Ren (Jack) Chuang" writes:
>
> > The memory tiering component in the kernel is functionally useless for
> > CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the nodes
> > are lumped together in the DRAM tier.
> >
Hi Richard:
On 3/4/24 17:51, Xianglai Li wrote:
When we use qemu tcg simulation, the page size of bios is 4KB.
When using the level 2 super large page (page size is 1G) to create
the page table,
it is found that the content of the corresponding address space is
abnormal,
resulting in the bios
On 3/4/24 23:32, Paolo Bonzini wrote:
On 1/25/24 23:48, Glenn Miles wrote:
Specs are available here:
https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf
This is a simple model supporting the basic registers for GPIO
mode. The device also supports an interrupt output line but the
On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote:
>
> "Ho-Ren (Jack) Chuang" writes:
>
> > The memory tiering component in the kernel is functionally useless for
> > CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the
nodes
> > are lumped together in the DRAM tier.
> >
> On 27-Feb-2024, at 21:17, Igor Mammedov wrote:
>
> QEMU for some time now uses SMBIOS 3.0 for PC/Q35 machines by
> default, however Windows has a bug in locating SMBIOS 3.0
> entrypoint and fails to find tables when booted on SeaBIOS
> (on UEFI SMBIOS 3.0 tables work fine since firmware
> One thing I forgot.
>
> Please add a test. tests/qtest/bios-tables-test.c
> + relevant table dumps.
Here I need to add a test that creates a vfio-pci device and numa
nodes and link using the acpi-generic-initiator object. One thing
here is that the -device vfio-pci needs a host= argument. I
On 3/5/2024 3:43 AM, Daniel Henrique Barboza wrote:
>
>
> On 3/4/24 07:25, Fei Wu wrote:
>> The harts requirements of RISC-V server platform [1] require RVA23 ISA
>> profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides
>> a virt CPU type (rvsp-ref) as compliant as possible.
>>
On 3/5/2024 3:35 AM, Daniel Henrique Barboza wrote:
>
>
> On 3/4/24 07:25, Fei Wu wrote:
>> The RISC-V Server Platform specification[1] defines a standardized set
>> of hardware and software capabilities, that portable system software,
>> such as OS and hypervisors can rely on being present in a
On 04/03/2024 20.37, Alex Bennée wrote:
We "fixed" a bug with LTO builds with 100c459f194 (tests/qtest: bump
up QOS_PATH_MAX_ELEMENT_SIZE) but it seems it has triggered again.
Lets be more assertive raising QOS_PATH_MAX_ELEMENT_SIZE to make it go
away again.
Resolves:
each qpl job is used to (de)compress a normal page and it can
be processed independently by the IAA hardware. All qpl jobs
are submitted to the hardware at once, and wait for all jobs
completion.
Signed-off-by: Yuan Liu
Reviewed-by: Nanhai Zou
---
migration/multifd-qpl.c | 219
the qpl initialization includes memory allocation for compressed
data and the qpl job initialization.
the qpl initialization will check whether the In-Memory Analytics
Accelerator(IAA) hardware is available, if the platform does not
have IAA hardware or the IAA hardware is not available, the QPL
the new function get_iov_count is used to get the number of
IOVs required by a specified multifd method
Different multifd methods may require different numbers of IOVs.
Based on streaming compression of zlib and zstd, all pages will be
compressed to a data block, so an IOV is required to send
add qpl to compression method test for multifd migration
the migration with qpl compression needs to access IAA hardware
resource, please run "check-qtest" with sudo or root permission,
otherwise migration test will fail
Signed-off-by: Yuan Liu
Reviewed-by: Nanhai Zou
---
add the Query Processing Library (QPL) compression method
Although both qpl and zlib support deflate compression, qpl will
only use the In-Memory Analytics Accelerator(IAA) for compression
and decompression, and IAA is not compatible with the Zlib in
migration, so qpl is used as a new compression
add --enable-qpl and --disable-qpl options to enable and disable
the QPL compression method for multifd migration.
the Query Processing Library (QPL) is an open-source library
that supports data compression and decompression features.
The QPL compression is based on the deflate compression
add zlib and zstd compression levels in multifd parameter
testing and application and add compression level tests
Signed-off-by: Yuan Liu
Reviewed-by: Nanhai Zou
Reported-by: Xiaohui Li
---
migration/options.c | 12
tests/qtest/migration-test.c | 16
2
add QPL compression method introduction
Signed-off-by: Yuan Liu
Reviewed-by: Nanhai Zou
---
docs/devel/migration/features.rst| 1 +
docs/devel/migration/qpl-compression.rst | 231 +++
2 files changed, 232 insertions(+)
create mode 100644
Before v2.12, serial_hds used MAX_SERIAL_PORTS(4) for
resources of serials.The limitaion description of "-serial"
option: "This option can be used several times to simulate
up to 4 serial ports."
In latest qemu, serial_hds have been replaced by "Chardev **"
and now is dynamically allocated through
Of course, I am glad to do. And I need to clarify that our use case only
support VIRTIO_F_NOTIFICATION_DATA transport feature on DPDK vDPA framework
which the backend type is NET_CLIENT_DRIVER_VHOST_USER and use
user_feature_bits. So the new feature add on vdpa_feature_bits will not under
On Mon, 4 Mar 2024 at 18:01, Cédric Le Goater wrote:
> This will prepare ground for futur changes adding an Error** argument
* futur -> future
> +ret = qemu_fflush(f);
> +if (ret) {
* if (ret) -> if (ret < 0)
Thank you.
---
- Prasad
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, March 4, 2024 11:40 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PATCH v2
On 3/4/24 17:51, Xianglai Li wrote:
When we use qemu tcg simulation, the page size of bios is 4KB.
When using the level 2 super large page (page size is 1G) to create the page
table,
it is found that the content of the corresponding address space is abnormal,
resulting in the bios can not start
On 2024/3/4 20:18, Jinjie Ruan wrote:
>
>
> On 2024/3/1 7:50, Richard Henderson wrote:
>> On 2/29/24 03:10, Jinjie Ruan via wrote:
>>> If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
>>> is higher than 0x80, otherwise it is higher than 0x0. And save NMI
>>> super
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Thursday, February 29, 2024 5:38 PM
> To: Jamin Lin ; Cédric Le Goater ;
> Peter Maydell ; Andrew Jeffery
> ; Joel Stanley ; Alistair
> Francis ; open list:ASPEED BMCs
> ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin
On 2024/03/05 2:52, Peter Maydell wrote:
On Sun, 3 Mar 2024 at 10:53, Akihiko Odaki wrote:
This makes elf2dmp more robust against corrupted inputs.
Signed-off-by: Akihiko Odaki
---
contrib/elf2dmp/addrspace.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
When we use qemu tcg simulation, the page size of bios is 4KB.
When using the level 2 super large page (page size is 1G) to create the page
table,
it is found that the content of the corresponding address space is abnormal,
resulting in the bios can not start the operating system and graphical
When we use qemu tcg simulation, the page size of bios is 4KB.
When using the level 2 super large page (page size is 1G) to create the page
table,
it is found that the content of the corresponding address space is abnormal,
resulting in the bios can not start the operating system and graphical
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, March 4, 2024 11:54 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PATCH v2
On Mon, Mar 04, 2024 at 01:28:28PM +0100, Cédric Le Goater wrote:
> This will help preserving the error set by .save_setup() handlers.
>
> Signed-off-by: Cédric Le Goater
IIUC this is about the next patch. I got fully confused before reading
into the next one. IMHO we can squash it into where
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, March 4, 2024 10:36 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PATCH v2
On Mon, Mar 4, 2024 at 6:11 PM Xu Liu wrote:
>
> Hey Alex and Paolo,
>
> I saw there is some code related to AVX
> https://elixir.bootlin.com/linux/latest/source/arch/x86/kvm/emulate.c#L668
>
> Does that mean in some special cases, kvm supports AVX instructions ?
> I didn’t really know the big
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, March 4, 2024 10:32 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PATCH v2
On 3/4/2024 10:58 PM, Gerd Hoffmann wrote:
On Mon, Mar 04, 2024 at 09:54:40AM +0800, Xiaoyao Li wrote:
On 3/1/2024 6:17 PM, Gerd Hoffmann wrote:
query kvm for supported guest physical address bits using
KVM_CAP_VM_GPA_BITS. Expose the value to the guest via cpuid
(leaf 0x8008, eax, bits
The while the 8-bit input elements are sequential in the input vector,
the 32-bit output elements are not sequential in the output matrix.
Do not attempt to compute 2 32-bit outputs at the same time.
Cc: qemu-sta...@nongnu.org
Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product")
On Mon, Mar 04, 2024 at 05:42:03PM +0300, Maksim Davydov wrote:
> If a migration stream is broken, the address and flag reading can return
> zero. Thus, an irrelevant flag error will be returned instead of EIO.
> It can be fixed by additional check after the reading.
>
> Signed-off-by: Maksim
On Mon, Mar 04, 2024 at 12:53:36PM +0200, Avihai Horon wrote:
> Hi,
>
> This small series is v2 of the single patch I previously sent [1].
>
> It removes device serialization in qemu_savevm_state_iterate() and does
> some VFIO migration touch ups. More info provided in the commit
> messages.
>
Hey Alex and Paolo,
I saw there is some code related to AVX
https://elixir.bootlin.com/linux/latest/source/arch/x86/kvm/emulate.c#L668
Does that mean in some special cases, kvm supports AVX instructions ?
I didn’t really know the big picture, so just guess what it is doing .
Thanks,
Xu
> On
On Mon, Mar 4, 2024 at 8:29 PM Cédric Le Goater wrote:
> Now that the log_global*() handlers take an Error** parameter and
> return a bool, do the same for memory_global_dirty_log_start() and
> memory_global_dirty_log_stop(). The error is reported in the callers
> for now and it will be
On Mon, Mar 04, 2024 at 09:04:51PM +, Daniel P. Berrangé wrote:
> On Mon, Mar 04, 2024 at 05:15:05PM -0300, Fabiano Rosas wrote:
> > Peter Xu writes:
> >
> > > On Mon, Mar 04, 2024 at 08:53:24PM +0800, Peter Xu wrote:
> > >> On Mon, Mar 04, 2024 at 12:42:25PM +, Daniel P. Berrangé wrote:
Hi gaosong:
Hi,
Title 'target/loongarch: ' ...
OK! I will fix it in next version.
Thanks,
Xianglai.
Thanks.
Song Gao
在 2024/2/28 14:55, Xianglai Li 写道:
The lddir and ldpte instruction emulation has
a problem with the use of large page processing above level 2.
The page size is
On 2024/3/5 上午12:53, Richard Henderson wrote:
On 3/3/24 16:18, Bibo Mao wrote:
@@ -696,11 +700,15 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE
*f, int flags)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = >env;
- int i;
+ int i, fp_status;
On 3/4/24 4:48 PM, Paolo Bonzini wrote:
touch_all_pages() can return early, before creating threads. In this case,
however, it leaks the MemsetContext that it has allocated at the
beginning of the function.
Reported by Coverity as CID 1534922.
Fixes: 04accf43df8 ("oslib-posix: initialize
On Sat, Mar 2, 2024 at 6:38 AM Alyssa Ross wrote:
> Hi Gurchetan,
>
> > >> > Would this be a suitable commit for the 0.1.3 release of rutabaga?
> > >> >
> > >> >
> https://chromium.googlesource.com/crosvm/crosvm/+/5dfd74a0680d317c6edf44138def886f47cb1c7c
> > >> >
> > >> > The gfxstream/AEMU
Hey Paolo,
Thanks for confirming that the AVX is not supported for MMIO space.
So for the emulated device, basically I have to force the compiler avoid using
vmovdqu .
I am curious about how kvm emulates those instructions. Do you mind sharing
some related code pointer ?
Thanks,
Xu
On Mar
Hey Alex,
Thanks for the detailed explanation!
First answer your question:
Is your "program" just doing a memcpy() with an mmap() of the PCI BAR
acquired through pci-sysfs or a userspace vfio-pci driver within the
guest?
My program is using a usersapcee vfio-pci driver for both emulated device
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