Since different memory devices require finding, allocating, and putting
memory types, these common steps are abstracted in this patch,
enhancing the scalability and conciseness of the code.
Signed-off-by: Ho-Ren (Jack) Chuang
Reviewed-by: "Huang, Ying"
---
drivers/dax/kmem.c | 20
When a memory device, such as CXL1.1 type3 memory, is emulated as
normal memory (E820_TYPE_RAM), the memory device is indistinguishable
from normal DRAM in terms of memory tiering with the current implementation.
The current memory tiering assigns all detected normal memory nodes
to the same DRAM
The current implementation treats emulated memory devices, such as
CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
(E820_TYPE_RAM). However, these emulated devices have different
characteristics than traditional DRAM, making it important to
distinguish them. Thus, we
On 2024/03/29 6:44, BALATON Zoltan wrote:
On Thu, 28 Mar 2024, Rene Engel wrote:
I wanted to discuss this topic with you again, there was already a
patch series that worked well under Qemu with
Pegasos2/AmigaOneXe/Same460 and AmigaOs4.1. The option zoom-to-fit=on
should be used to adjust all
Check for flag bit in H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE need to use
bitwise NOT operator to ensure no other flag bits are set.
Reported by Coverity as CID 1540008, 1540009.
Reported-by: Peter Maydell
Signed-off by: Harsh Prateek Bora
---
hw/ppc/spapr_nested.c | 2 +-
1 file changed, 1
On 3/28/24 20:55, Peter Maydell wrote:
On Wed, 27 Mar 2024 at 05:41, Harsh Prateek Bora wrote:
On 3/26/24 21:32, Peter Maydell wrote:
On Tue, 12 Mar 2024 at 17:11, Nicholas Piggin wrote:
From: Harsh Prateek Bora
Introduce the nested PAPR hcalls:
- H_GUEST_GET_STATE which is
Hi Daniel,
On 3/25/24 16:55, Daniel P. Berrangé wrote:
On Mon, Mar 25, 2024 at 01:35:58PM +0800, Shaoqin Huang wrote:
Hi Daniel,
Thanks for your reviewing. I see your comments in the v7.
I have some doubts about what you said about the QAPI. Do you want me to
convert the current design into
> -Original Message-
> From: Peter Xu
> Sent: Thursday, March 28, 2024 11:22 PM
> To: Liu, Yuan1
> Cc: faro...@suse.de; qemu-devel@nongnu.org; hao.xi...@bytedance.com;
> bryan.zh...@bytedance.com; Zou, Nanhai
> Subject: Re: [PATCH v5 0/7] Live Migration With IAA
>
> On Thu, Mar 28,
When using the post-copy preemption feature to perform post-copy live
migration, the below scenario could lead to a deadlock and the migration
will never finish:
- Source connect() the preemption channel in postcopy_start().
- Source and the destination side TCP stack finished the 3-way
On Fri, Mar 29, 2024 at 11:02 AM Cindy Lu wrote:
>
> On Thu, Mar 28, 2024 at 12:12 PM Jason Wang wrote:
> >
> > On Wed, Mar 27, 2024 at 5:33 PM Cindy Lu wrote:
> > >
> > > On Wed, Mar 27, 2024 at 5:12 PM Jason Wang wrote:
> > > >
> > > > On Wed, Mar 27, 2024 at 4:28 PM Cindy Lu wrote:
> > > >
Hi Michael,
>-Original Message-
>From: Michael S. Tsirkin
>Subject: Re: [PATCH v1 3/6] intel_iommu: Add a framework to check and
>sync host IOMMU cap/ecap
>
>On Mon, Mar 18, 2024 at 02:20:50PM +0100, Eric Auger wrote:
>> Hi Michael,
>>
>> On 3/13/24 12:17, Michael S. Tsirkin wrote:
>> >
On Thu, Mar 28, 2024 at 12:12 PM Jason Wang wrote:
>
> On Wed, Mar 27, 2024 at 5:33 PM Cindy Lu wrote:
> >
> > On Wed, Mar 27, 2024 at 5:12 PM Jason Wang wrote:
> > >
> > > On Wed, Mar 27, 2024 at 4:28 PM Cindy Lu wrote:
> > > >
> > > > On Wed, Mar 27, 2024 at 3:54 PM Jason Wang wrote:
> > >
On Thu, Mar 28, 2024 at 5:59 PM Huang, Ying wrote:
>
> "Ho-Ren (Jack) Chuang" writes:
>
> > The current implementation treats emulated memory devices, such as
> > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
> > (E820_TYPE_RAM). However, these emulated devices have
> -Original Message-
> From: Taylor Simpson
> Sent: Thursday, February 1, 2024 4:34 AM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
> -Original Message-
> From: Peter Xu
> Sent: Thursday, March 28, 2024 11:16 PM
> To: Liu, Yuan1
> Cc: Daniel P. Berrangé ; faro...@suse.de; qemu-
> de...@nongnu.org; hao.xi...@bytedance.com; bryan.zh...@bytedance.com; Zou,
> Nanhai
> Subject: Re: [PATCH v5 5/7] migration/multifd:
> -Original Message-
> From: Taylor Simpson
> Sent: Thursday, February 1, 2024 4:34 AM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
> -Original Message-
> From: Taylor Simpson
> Sent: Thursday, February 1, 2024 4:34 AM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
On 28/03/2024 23:01, Peter Xu wrote:
> On Thu, Mar 28, 2024 at 11:18:04AM -0300, Fabiano Rosas wrote:
>> Philippe Mathieu-Daudé writes:
>>
>>> The whole RDMA subsystem was deprecated in commit e9a54265f5
>>> ("hw/rdma: Deprecate the pvrdma device and the rdma subsystem")
>>> released in v8.2.
On Thu, Mar 28, 2024 at 6:23 PM wrote:
> From: Marc-André Lureau
>
> ../migration/dirtyrate.c:186:5: error: ‘records’ may be used uninitialized
> [-Werror=maybe-uninitialized]
> ../migration/dirtyrate.c:168:12: error: ‘gen_id’ may be used uninitialized
> [-Werror=maybe-uninitialized]
>
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
> -Original Message-
> From: Taylor Simpson
> Sent: Wednesday, March 6, 2024 9:23 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> Marco Liebel (QUIC) ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
"Ho-Ren (Jack) Chuang" writes:
> The current implementation treats emulated memory devices, such as
> CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
> (E820_TYPE_RAM). However, these emulated devices have different
> characteristics than traditional DRAM, making it
The current implementation treats emulated memory devices, such as
CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
(E820_TYPE_RAM). However, these emulated devices have different
characteristics than traditional DRAM, making it important to
distinguish them. Thus, we
Since different memory devices require finding, allocating, and putting
memory types, these common steps are abstracted in this patch,
enhancing the scalability and conciseness of the code.
Signed-off-by: Ho-Ren (Jack) Chuang
Reviewed-by: "Huang, Ying"
---
drivers/dax/kmem.c | 20
When a memory device, such as CXL1.1 type3 memory, is emulated as
normal memory (E820_TYPE_RAM), the memory device is indistinguishable
from normal DRAM in terms of memory tiering with the current implementation.
The current memory tiering assigns all detected normal memory nodes
to the same DRAM
When a memory device, such as CXL1.1 type3 memory, is emulated as
normal memory (E820_TYPE_RAM), the memory device is indistinguishable
from normal DRAM in terms of memory tiering with the current implementation.
The current memory tiering assigns all detected normal memory nodes
to the same DRAM
On Thu, 28 Mar 2024, Dr. David Alan Gilbert wrote:
* BALATON Zoltan (bala...@eik.bme.hu) wrote:
On Sun, 24 Mar 2024, Dr. David Alan Gilbert wrote:
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
Signed-off-by:
* BALATON Zoltan (bala...@eik.bme.hu) wrote:
> On Sun, 24 Mar 2024, Dr. David Alan Gilbert wrote:
> > * Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
> > > Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
> > >
> > > Signed-off-by: Philippe Mathieu-Daudé
> > > ---
> > >
On Thu, 28 Mar 2024, Rene Engel wrote:
I wanted to discuss this topic with you again, there was already a patch series
that worked well under Qemu with
Pegasos2/AmigaOneXe/Same460 and AmigaOs4.1. The option zoom-to-fit=on should be
used to adjust all resolutions provided by the guest
system to
Richard Henderson writes:
> On 3/23/24 22:09, Sven Schnelle wrote:
>> The CPU seems to mask a few bits in the offset when running
>> under HP-UX. ISR/IOR register contents for an address in
>> the processor HPA (0xfffa) on my C8000 and J6750:
>> running on Linux: 3fff
It was noticed that my linux.vnet.ibm.com address does not
always work so dropping the vnet to see if that works better.
Signed-off-by: Glenn Miles
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a07af6b9d4..575ac2e05d 100644
On Thu, Mar 28, 2024 at 02:20:48PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> ../migration/ram.c:1873:23: error: ‘dirty’ may be used uninitialized
> [-Werror=maybe-uninitialized]
>
> When 'block' != NULL, 'dirty' is initialized.
>
> Signed-off-by: Marc-André
On Thu, Mar 28, 2024 at 02:20:45PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> ../migration/dirtyrate.c:186:5: error: ‘records’ may be used uninitialized
> [-Werror=maybe-uninitialized]
> ../migration/dirtyrate.c:168:12: error: ‘gen_id’ may be used uninitialized
>
On Thu, Mar 28, 2024 at 02:20:44PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> ../migration/block.c:966:16: error: ‘ret’ may be used uninitialized
> [-Werror=maybe-uninitialized]
>
> Given that "cluster_size" must be <= BLK_MIG_BLOCK_SIZE, the previous
> loop is
On Mon, 25 Mar 2024 at 08:52, Jinjie Ruan wrote:
>
> Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for
> ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.
>
> If FEAT_GICv3_NMI is supported, ich_ap_write() should consider
> ICV_AP1R_EL1.NMI
> bit. In icv_activate_irq() and
Adds migration support for Branch History Rolling
Buffer (BHRB) internal state.
Signed-off-by: Glenn Miles
Reviewed-by: Nicholas Piggin
---
Changes from v3:
- Rebased onto latest master branch
target/ppc/machine.c | 21 +
1 file changed, 21 insertions(+)
diff --git
This commit continues adding support for the Branch History
Rolling Buffer (BHRB) as is provided starting with the P8
processor and continuing with its successors. This commit
is limited to the recording and filtering of taken branches.
The following changes were made:
- Enabled functionality
This commit is preparatory to the addition of Branch History
Rolling Buffer (BHRB) functionality, which is being provided
today starting with the P8 processor.
BHRB uses several SPR register fields to control whether or not
a branch instruction's address (and sometimes target address)
should be
Add support for the clrbhrb and mfbhrbe instructions.
Since neither instruction is believed to be critical to
performance, both instructions were implemented using helper
functions.
Access to both instructions is controlled by bits in the
HFSCR (for privileged state) and MMCR0 (for problem
This is a series of patches for adding support for the Branch History
Rolling Buffer (BHRB) facility. This was added to the Power ISA
starting with version 2.07. Changes were subsequently made in version
3.1 to limit BHRB recording to instructions run in problem state only
and to add a control
On Thu, Mar 28, 2024 at 04:22:27PM +0100, Thomas Huth wrote:
> Since e9a54265f5 was not very clear about rdma migration code, should we
> maybe rather add a separate deprecation note for the migration part, and add
> a proper warning message to the migration code in case someone tries to use
> it
On Thu, 28 Mar 2024, Philippe Mathieu-Daudé wrote:
pc_system_flash_create() is only useful for PCI-based machines.
Move the call to the PCI-based init() handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 2 +-
hw/i386/pc_sysfw.c | 10 --
2 files changed, 5
On Thu, 28 Mar 2024, Philippe Mathieu-Daudé wrote:
x86_bios_rom_init() is the single non-PCI-machine call
from pc_system_firmware_init(). Extract it to the caller.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 6 +-
hw/i386/pc_sysfw.c | 5 +
2 files changed, 6
On Thu, 28 Mar 2024, Philippe Mathieu-Daudé wrote:
acpi_setup() caller knows about the machine state, so pass
it as argument to avoid a qdev_get_machine() call.
We already resolved X86_MACHINE(pcms) as 'x86ms' so use the
latter.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/acpi-build.h |
On 3/28/24 05:33, Peter Maydell wrote:
If the group of the highest priority pending interrupt is disabled
via ICC_IGRPEN*, the ICC_HPPIR* registers should return
INTID_SPURIOUS, not the interrupt ID. (See the GIC architecture
specification pseudocode functions ICC_HPPIR1_EL1[] and
Fixes: 83b4613ba83 ("disas: introduce show_opcodes")
Signed-off-by: Richard Henderson
---
disas/disas-mon.c | 1 +
disas/disas.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/disas/disas-mon.c b/disas/disas-mon.c
index 48ac492c6c..5d6d9aa02d 100644
--- a/disas/disas-mon.c
+++
On 28/03/2024 14.02, Philippe Mathieu-Daudé wrote:
GlusterFS+RDMA has been deprecated 8 years ago in commit
0552ff2465 ("block/gluster: deprecate rdma support"):
gluster volfile server fetch happens through unix and/or tcp,
it doesn't support volfile fetch over rdma. The rdma code may
On 28/03/2024 14.02, Philippe Mathieu-Daudé wrote:
The whole RDMA subsystem was deprecated in commit e9a54265f5
("hw/rdma: Deprecate the pvrdma device and the rdma subsystem")
released in v8.2.
Remove:
- PVRDMA device
- generated vmw_pvrdma/ directory from linux-headers
- rdmacm-mux tool
On 28/3/24 16:40, aidan_le...@selinc.com wrote:
From: aidaleuc
Signed-off-by: aidaleuc
---
qga/commands-common-ssh.c | 50 ++
qga/commands-common-ssh.h | 10
qga/commands-posix-ssh.c | 51 +++
On Thu, Mar 28, 2024 at 04:02:50PM +0200, Avihai Horon wrote:
> Hello,
>
> This small series fixes two migration bugs I stumbled upon recently.
> Comments are welcome, thanks for reviewing.
>
> Avihai Horon (2):
> migration: Set migration error in migration_completion()
> migration/postcopy:
On Thu, 28 Mar 2024 at 16:39, Marcin Juszkiewicz
wrote:
>
> Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA
> specifications. Then BBR defines firmware interface.
>
> Added note about DeviceTree data passed from QEMU to firmware. It is
> very minimal and provides only data we
On Thu, Mar 28, 2024 at 17:38:51 +0100, Marcin Juszkiewicz wrote:
> Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA
> specifications. Then BBR defines firmware interface.
>
> Added note about DeviceTree data passed from QEMU to firmware. It is
> very minimal and provides only
W dniu 28.03.2024 o 16:43, Peter Maydell pisze:
On Tue, 26 Mar 2024 at 09:58, Marcin Juszkiewicz
wrote:
Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA
specifications. Then BBR defines firmware interface.
Added note about DeviceTree data passed from QEMU to firmware. It
On Thu, Mar 28, 2024 at 10:06:01AM -0500, Eric Blake wrote:
> Adjusting cc list to add upstream NBD and drop developers unrelated to
> this part of the qemu series...
>
> On Thu, Mar 28, 2024 at 02:13:42PM +, Richard W.M. Jones wrote:
> > On Thu, Mar 28, 2024 at 03:06:03PM +0100, Thomas Huth
Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA
specifications. Then BBR defines firmware interface.
Added note about DeviceTree data passed from QEMU to firmware. It is
very minimal and provides only data we use in firmware.
Added NUMA information to list of things reported
On 3/28/24 16:50, Avihai Horon wrote:
On 28/03/2024 17:21, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
Hello Avihai,
On 3/28/24 15:02, Avihai Horon wrote:
After commit 9425ef3f990a ("migration: Use migrate_has_error() in
close_return_path_on_source()"),
The goal of these patches is to add support to a variety of virtio and
vhost devices for the VIRTIO_F_IN_ORDER transport feature. This feature
indicates that all buffers are used by the device in the same order in
which they were made available by the driver.
These patches attempt to implement a
Implements VIRTIO_F_IN_ORDER feature support for virtio devices using
the split virtqueue layout.
For a virtio device that has negotiated the VIRTIO_F_IN_ORDER feature
whose virtqueues use a split virtqueue layout, it's essential that
used VirtQueueElements are written to the used ring in-order.
Implements VIRTIO_F_IN_ORDER feature support for virtio devices using
the packed virtqueue layout.
For a virtio device that has negotiated the VIRTIO_F_IN_ORDER feature
whose virtqueues use a packed virtqueue layout, it's essential that used
VirtQueueElements are written to the descriptor ring
Add support for the VIRTIO_F_IN_ORDER feature across a variety of vhost
devices.
The inclusion of VIRTIO_F_IN_ORDER in the feature bits arrays for these
devices ensures that the backend is capable of offering and providing
support for this feature, and that it can be disabled if the backend
does
Initialize sequence variables for VirtQueue and VirtQueueElement
structures. A VirtQueue's sequence variables are initialized when a
VirtQueue is being created or reset. A VirtQueueElement's sequence
variable is initialized when a VirtQueueElement is being initialized.
These variables will be used
Extend the virtio device property definitions to include the
VIRTIO_F_IN_ORDER feature.
The default state of this feature is disabled, allowing it to be
explicitly enabled where it's supported.
Acked-by: Eugenio Pérez
Signed-off-by: Jonah Palmer
---
include/hw/virtio/virtio.h | 4 +++-
1 file
On Mon, 25 Mar 2024 at 06:19, Thomas Huth wrote:
> We are now using timeouts from the meson test harneess in meson.build, too,
> see the slow_qtests[] at the beginning of that file.
> You seem to be using a 10 minutes timeout in your test below
> (usart_wait_for_flag() function), but you didn't
On Sun, 24 Mar 2024 at 16:56, Arnaud Minier
wrote:
>
> This patch adds the STM32L4x5 USART
> (Universal Synchronous/Asynchronous Receiver/Transmitter)
> device and is part of a series implementing the
> STM32L4x5 with a few peripherals.
>
> It implements the necessary functionalities to
On Sun, 24 Mar 2024 at 16:57, Arnaud Minier
wrote:
>
> Add the USART to the SoC and connect it to the other implemented devices.
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
> ---
> docs/system/arm/b-l475e-iot01a.rst | 2 +-
> hw/arm/Kconfig | 1 +
>
On Sun, 24 Mar 2024 at 16:57, Arnaud Minier
wrote:
>
> Add a function to change the settings of the
> serial connection.
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
> ---
> hw/char/stm32l4x5_usart.c | 98 +++
> hw/char/trace-events |
x86_bios_rom_init() is the single non-PCI-machine call
from pc_system_firmware_init(). Extract it to the caller.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 6 +-
hw/i386/pc_sysfw.c | 5 +
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc.c
On Sun, 24 Mar 2024 at 16:57, Arnaud Minier
wrote:
>
> Implement the ability to read and write characters to the
> usart using the serial port.
>
> The character transmission is based on the
> cmsdk-apb-uart implementation.
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
> +/*
CXL depends on PCIe, which isn't available on non-PCI
machines such the ISA-only PC one.
Move CXLState to PcPciMachineState, and move the CXL
specific calls to pc_pci_machine_initfn() and
pc_pci_machine_done().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 3 ++-
On Sun, 24 Mar 2024 at 16:56, Arnaud Minier
wrote:
>
> Add the basic infrastructure (register read/write, type...)
> to implement the STM32L4x5 USART.
>
> Also create different types for the USART, UART and LPUART
> of the STM32L4x5 to deduplicate code and enable the
> implementation of different
pc_init1() is specific to the isapc and i440fx/piix machines,
rename it as pc_piix_init(). Expose it in "hw/i386/pc.h" to
be able to call it externally (see next patch).
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 +
hw/i386/pc_piix.c| 8
hw/isa/piix.c
Only PCI-based machines use the set of parallel flash devices.
Move the fields from PCMachineState to PcPciMachineState.
Directly pass a PcPciMachineState argument to the
pc_system_flash/fw methods.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 10
hw/i386/pc.c
fw_cfg_add_extra_pci_roots() expects a PCI bus, which only
PCI-based machines have. No need to call it on the ISA-only
machine. Move it to the PCI-specific machine_done handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
All PCI-based machines have the smbios_legacy_mode
field set to %false. Simplify by using an inlined
helper checking whether the machine is PCI-based or
not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 -
hw/i386/fw_cfg.c | 8 ++--
hw/i386/pc_piix.c| 2 --
3
pc_system_flash_create() is only useful for PCI-based machines.
Move the call to the PCI-based init() handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 2 +-
hw/i386/pc_sysfw.c | 10 --
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/hw/i386/pc.c
We are going to refactor fw_cfg_build_smbios() in the
next patches. In order to avoid too much #ifdef'ry in
it, define a stub.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/fw_cfg-smbios-stub.c | 15 +++
hw/i386/fw_cfg.c | 4 ++--
hw/i386/meson.build | 1 +
Since CXL helpers expect a PCI-based machine, we
can directly pass them a PcPciMachineState argument.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index
Extract the ISA-only PC machine code from pc_piix.c
to a new file, pc_isa.c.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
hw/i386/pc_isa.c| 33 +
hw/i386/pc_piix.c | 23 ---
hw/i386/meson.build | 1 +
4 files
Keep fw_cfg_build_smbios() for PCI-based machines, call
fw_cfg_build_smbios_legacy() directly from pc_machine_done().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/fw_cfg.c | 10 --
hw/i386/pc.c | 12 +++-
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git
smbios_defaults() and smbios_legacy_mode() are logical
opposite. Simplify using the latter.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/fw_cfg.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c
index ffa60a4a33..df05fe060c
acpi_setup() returns early if acpi_build_enabled is not set:
2752 void acpi_setup(PCMachineState *pcms)
2753 {
...
2768 if (!pcms->acpi_build_enabled) {
2769 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2770 return;
2771 }
acpi_build_enabled
"fw_cfg.h" declares fw_cfg_build_smbios() which use
SmbiosEntryPointType, itself declared in "qapi-types-machine.h".
void fw_cfg_build_smbios(PCMachineState *pcms, FWCfgState *fw_cfg,
SmbiosEntryPointType ep_type);
Factor fw_cfg_build_smbios_legacy() out of
fw_cfg_build_smbios().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/fw_cfg.h | 1 +
hw/i386/fw_cfg-smbios-stub.c | 4
hw/i386/fw_cfg.c | 33 ++---
3 files changed, 27 insertions(+), 11
All PCI-based machines have the gigabyte_align field
set to %true. Simplify by using an inlined helper
checking whether the machine is PCI-based or not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 9 -
hw/i386/pc.c | 1 -
hw/i386/pc_piix.c| 16
All PCI-based machines have the has_reserved_memory
field set to %true. Simplify by using an inlined helper
checking whether the machine is PCI-based or not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 -
hw/i386/pc.c | 17 ++---
hw/i386/pc_piix.c
pc_pci_hole64_start() is only used by PCI-based
machines. Pass it a PcPciMachineState argument,
removing a qdev_get_machine() call.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 2 +-
hw/i386/pc.c | 8
hw/pci-host/i440fx.c | 2 +-
hw/pci-host/q35.c| 2 +-
All PCI-based machines have the smbios_defaults field
set to %true. Simplify by using an inlined helper
checking whether the machine is PCI-based or not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 -
hw/i386/fw_cfg.c | 7 ++-
hw/i386/pc.c | 1 -
Introduce the pc_machine_is_pci_enabled() helper to be
able to alter PCMachineClass fields later.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 2 ++
hw/i386/pc.c | 11 +--
hw/i386/pc_piix.c| 11 ++-
hw/i386/pc_q35.c | 2 +-
acpi_setup() caller knows about the machine state, so pass
it as argument to avoid a qdev_get_machine() call.
We already resolved X86_MACHINE(pcms) as 'x86ms' so use the
latter.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/acpi-build.h | 3 ++-
hw/i386/acpi-build.c | 5 ++---
hw/i386/pc.c
South bridge type is only relevant for the i440fx/piix
machine, which is PCI-based.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 8
hw/i386/pc.c | 3 ++-
hw/i386/pc_piix.c| 12 ++--
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git
PCMachineClass::has_acpi_build is always %true for PCI
based machines. Remove it, setting the 'acpi_build_enabled'
field once in pc_pci_machine_initfn().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 3 ---
hw/i386/pc.c | 6 +++---
hw/i386/pc_piix.c| 1 -
3 files
All TYPE_PC_PCI_MACHINE-based machines have pci_enabled
set to %true. By checking a TYPE_PC_MACHINE inherits the
TYPE_PC_PCI_MACHINE base class, we don't need this field
anymore.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 -
hw/i386/pc.c | 3 +--
Since only PCI-based machines use the 'acpi_build_enabled',
move it to PcPciMachineState.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/acpi-build.h | 2 +-
include/hw/i386/pc.h | 3 ++-
hw/i386/acpi-build.c | 8
hw/i386/pc.c | 5 ++---
hw/i386/xen/xen-hvm.c | 3 ++-
5
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