On Wed, Apr 17, 2024 at 6:13 AM Chen, Jiqian wrote:
>
> On 2024/4/16 23:45, Igor Mammedov wrote:
> > On Tue, 16 Apr 2024 15:01:27 +0800
> > Jiqian Chen wrote:
> >
> >> In current code, when guest does S3, virtio-gpu are reset due to the
> >> bit No_Soft_Reset is not set. After resetting, the
Hi,
Thank you for your reply.
On Tuesday, April 16, 2024 2:11:16 PM IST Eugenio Perez Martin wrote:
> [...]
> > After re-reading the linked articles, I think I have got some more
> > clarity. One confusion was related to the difference between vdpa
> > and vhost-vdpa.
> >
> > So far what I have
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH v2 02/10] vfio: Introduce HIODLegacyVFIO device
>
>Hello,
>
>On 4/16/24 05:41, Duan, Zhenzhong wrote:
>> Hi Cédric,
>>
>>> -Original Message-
>>> From: Cédric Le Goater
>>> Subject: Re: [PATCH v2 02/10] vfio:
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do
>compatibility check with host IOMMU cap/ecap
>
>Hello,
>
>On 4/16/24 09:09, Duan, Zhenzhong wrote:
>> Hi Cédric,
>>
>>> -Original Message-
>>> From: Cédric Le Goater
>>>
On Tue, Apr 16, 2024 at 5:51 PM Yuri Benditovich
wrote:
>
> On Tue, Apr 16, 2024 at 10:14 AM Jason Wang wrote:
> >
> > On Tue, Apr 16, 2024 at 1:43 PM Yuri Benditovich
> > wrote:
> > >
> > > On Tue, Apr 16, 2024 at 7:00 AM Jason Wang wrote:
> > > >
> > > > On Mon, Apr 15, 2024 at 10:05 PM Yuri
From: Dongwon Kim
To enhance security in accessing the QemuDmaBuf struct, new helper
functions for setting specific fields within the struct were introduced.
And all occurrences where these fields were previously set directly
have been updated to utilize these helper functions.
Suggested-by:
From: Dongwon Kim
This series introduces privacy enhancements to the QemuDmaBuf struct
and its contained data to bolster security. it accomplishes this by
introducing of helper functions for allocating, deallocating, and
accessing individual fields within the struct and replacing all direct
From: Dongwon Kim
This commit introduces utility functions for the creation and deallocation
of QemuDmaBuf instances. Additionally, it updates all relevant sections
of the codebase to utilize these new utility functions.
Suggested-by: Marc-André Lureau
Cc: Philippe Mathieu-Daudé
Cc: Vivek
From: Dongwon Kim
This commit introduces dpy_gl_qemu_dmabuf_get_... helpers to extract
specific fields from the QemuDmaBuf struct. It also updates all instances
where fields within the QemuDmaBuf struct are directly accessed, replacing
them with calls to these new helper functions.
v6: fix
On 2024/4/16 23:45, Igor Mammedov wrote:
> On Tue, 16 Apr 2024 15:01:27 +0800
> Jiqian Chen wrote:
>
>> In current code, when guest does S3, virtio-gpu are reset due to the
>> bit No_Soft_Reset is not set. After resetting, the display resources
>> of virtio-gpu are destroyed, then the display
On 17/04/2024 10:44, Li Zhijian wrote:
> bdrv_activate_all() should not be called from the coroutine context, move
> it to the QEMU thread colo_process_incoming_thread() with the bql_lock
> protected.
>
> The backtrace is as follows:
> #4 0x561af7948362 in bdrv_graph_rdlock_main_loop ()
bdrv_activate_all() should not be called from the coroutine context, move
it to the QEMU thread colo_process_incoming_thread() with the bql_lock
protected.
The backtrace is as follows:
#4 0x561af7948362 in bdrv_graph_rdlock_main_loop () at
../block/graph-lock.c:260
#5 0x561af7907a68
On Tue, Apr 16, 2024 at 11:21 AM Jason Wang wrote:
>
> On Mon, Apr 15, 2024 at 6:41 PM Cindy Lu wrote:
> >
> > On Mon, Apr 15, 2024 at 5:34 PM Michael S. Tsirkin wrote:
> > >
> > > From: Cindy Lu
> > >
> > > During the booting process of the non-standard image, the behavior of the
> > > called
bdrv_activate_all() should not be called from the coroutine context, move
it to the QEMU thread colo_process_incoming_thread() with the bql_lock
protected.
The backtrace is as follows:
#4 0x561af7948362 in bdrv_graph_rdlock_main_loop () at
../block/graph-lock.c:260
#5 0x561af7907a68
On 4/16/24 16:04, Daniel Henrique Barboza wrote:
Privileged spec section 4.1.9 mentions:
"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)
If stval is written with a nonzero value when a breakpoint,
On 4/16/24 17:35, Pierrick Bouvier wrote:
On 4/15/24 21:06, Richard Henderson wrote:
Based-on: 20240404230611.21231-1-richard.hender...@linaro.org
("[PATCH v2 00/21] Rewrite plugin code generation")
This is an attempt to fix
https://gitlab.com/qemu-project/qemu/-/issues/2208
("PC is not
On Tue Apr 16, 2024 at 7:43 PM AEST, BALATON Zoltan wrote:
> On Tue, 16 Apr 2024, Nicholas Piggin wrote:
> > On Wed Apr 10, 2024 at 9:03 PM AEST, BALATON Zoltan wrote:
> >> On Wed, 10 Apr 2024, Nicholas Piggin wrote:
> >>> On Wed Apr 10, 2024 at 9:55 AM AEST, BALATON Zoltan wrote:
> Real
On 4/15/24 21:06, Richard Henderson wrote:
Based-on: 20240404230611.21231-1-richard.hender...@linaro.org
("[PATCH v2 00/21] Rewrite plugin code generation")
This is an attempt to fix
https://gitlab.com/qemu-project/qemu/-/issues/2208
("PC is not updated for each instruction in TCG plugins")
I
On 4/16/24 16:54, Michael Tokarev wrote:
27.03.2024 17:20, Daniel Henrique Barboza :
Commit 558f5c42ef gated the local tests with g_test_slow() to skip them
in 'make check'. The reported issue back then was this following CI
problem:
Hi,
This new version has a change suggested by Richard in v2. No other
changes made.
Changes from v2:
- patch 2:
- use tcg_constant_tl() instead of loading a temp and doing a
movi_tl()
- v2 link:
https://lore.kernel.org/qemu-riscv/20240416194132.1843699-1-dbarb...@ventanamicro.com/
Privileged spec section 4.1.9 mentions:
"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)
If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception
We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":
"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fifth release candidate for the QEMU 9.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-9.0.0-rc4.tar.xz
On 4/16/24 12:41, Daniel Henrique Barboza wrote:
@@ -62,6 +62,10 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
} else {
+TCGv temp =
On 10/27/23 14:10, Jean-Louis Dupond wrote:
> [...]
>
> I've checked all the code paths, and as far as I see it nowhere breaks
> the discard_no_unref option.
> It's important that we don't introduce new code paths that can make
> holes in the qcow2 image when this option is enabled :)
>
> If you
Looks good. Thanks for taking care of that for us!
-Glenn
Reviewed-by: Glenn Miles
On Tue, 2024-04-16 at 20:47 +0200, Philippe Mathieu-Daudé wrote:
> One of the biggest change from I2C spec v6 -> v7 is:
>
> • Updated the terms "master/slave" to "controller/target"
>
> Since it follows the
27.03.2024 17:20, Daniel Henrique Barboza :
Commit 558f5c42ef gated the local tests with g_test_slow() to skip them
in 'make check'. The reported issue back then was this following CI
problem:
https://lists.nongnu.org/archive/html/qemu-devel/2020-11/msg05510.html
This problem ended up being
We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":
"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with
Privileged spec section 4.1.9 mentions:
"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)
If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception
Hi,
This is a re-send of the patch sent as a 9.0 bugfix in [1], now reframed
as a non-bug fix chabge,
A new patch (2) was added to handle a similar scenario with ebreak and tval.
Changes from v1:
- patch 1:
- rewrite commit msg to make it clear that this is a non-bug
fix change
- new
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s]: D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d}[.],
popcnt{b, w, d},
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i: D-form
isel: A-form
The changes were verified by validating that the tcg ops generated by
PCMachineClass::smbios_uuid_encoded was only used by the
pc-i440fx-2.1 machine, which got removed. It is now always
true, remove it.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
---
include/hw/i386/pc.h | 1 -
hw/i386/fw_cfg.c | 3 +--
hw/i386/pc.c
x86_cpu_change_kvm_default() was only used out of kvm-cpu.c by
the pc-i440fx-2.1 machine, which got removed. Make it static,
and remove its declaration. "kvm-cpu.h" is now empty, remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
---
PCMachineClass::acpi_data_size was only used by the pc-i440fx-2.0
machine, which got removed. Since it is constant, replace the class
field by a definition (local to hw/i386/pc.c, since not used
elsewhere).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
'uuid_encoded' is always true, remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
---
include/hw/firmware/smbios.h | 3 +--
hw/arm/virt.c| 3 +--
hw/i386/fw_cfg.c | 2 +-
hw/loongarch/virt.c | 2 +-
hw/riscv/virt.c | 2 +-
No external code sets the 'memory-hotplug-support'
property, remove it.
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
---
hw/acpi/ich9.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index
The pc-i440fx-2.1 machine was deprecated for the 8.2
release (see commit c7437f0ddb "docs/about: Mark the
old pc-i440fx-2.0 - 2.3 machine types as deprecated"),
time to remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
---
AcpiBuildState::rsdp is always NULL, remove it,
simplifying acpi_build_update().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
---
hw/i386/acpi-build.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/hw/i386/acpi-build.c
X86CPU::kvm_no_smi_migration was only used by the
pc-i440fx-2.3 machine, which got removed. Remove it
and simplify kvm_put_vcpu_events().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
---
target/i386/cpu.h | 3 ---
target/i386/cpu.c | 2 --
target/i386/kvm/kvm.c | 7
The pc-i440fx-2.3 machine was deprecated for the 8.2
release (see commit c7437f0ddb "docs/about: Mark the
old pc-i440fx-2.0 - 2.3 machine types as deprecated"),
time to remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/about/deprecated.rst | 4 ++--
acpi_memory_hotplug::is_enabled is set to %true once via
ich9_lpc_initfn() -> ich9_pm_add_properties(). No need to
check it, so remove now dead code.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
---
hw/acpi/ich9.c | 28 ++--
1 file changed, 6
PCMachineClass::resizable_acpi_blob was only used by the
pc-i440fx-2.2 machine, which got removed. It is now always
true. Remove it, simplifying acpi_build().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
---
include/hw/i386/pc.h | 3 ---
hw/i386/acpi-build.c | 10 --
PCMachineClass::legacy_acpi_table_size was only used by the
pc-i440fx-2.0 machine, which got removed. Remove it and simplify
acpi_build().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
---
include/hw/i386/pc.h | 1 -
hw/i386/acpi-build.c | 62
PCMachineClass::rsdp_in_ram was only used by the
pc-i440fx-2.2 machine, which got removed. It is
now always true. Remove it, simplifying acpi_setup().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
---
include/hw/i386/pc.h | 1 -
hw/i386/acpi-build.c |
'legacy_align' is always NULL, remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: David Hildenbrand
Reviewed-by: Zhao Liu
---
include/hw/mem/pc-dimm.h | 3 +--
hw/arm/virt.c| 2 +-
hw/i386/pc.c | 2 +-
hw/loongarch/virt.c | 2
The pc-i440fx-2.2 machine was deprecated for the 8.2
release (see commit c7437f0ddb "docs/about: Mark the
old pc-i440fx-2.0 - 2.3 machine types as deprecated"),
time to remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
---
Similarly to the commit c7437f0ddb "docs/about: Mark the
old pc-i440fx-2.0 - 2.3 machine types as deprecated",
deprecate the 2.4 to 2.12 machines.
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
---
docs/about/deprecated.rst | 4
'legacy_align' is always NULL, remove it, simplifying
memory_device_pre_plug().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: David Hildenbrand
Reviewed-by: Zhao Liu
---
include/hw/mem/memory-device.h | 2 +-
hw/i386/pc.c | 3 +--
'smbios_encode_uuid' is always true, remove it,
simplifying smbios_encode_uuid().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
---
hw/smbios/smbios.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
index
The pc-i440fx-2.0 machine was deprecated for the 8.2
release (see commit c7437f0ddb "docs/about: Mark the
old pc-i440fx-2.0 - 2.3 machine types as deprecated"),
time to remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Zhao Liu
---
PCMachineClass::enforce_aligned_dimm was only used by the
pc-i440fx-2.1 machine, which got removed. It is now always
true. Remove it, simplifying pc_get_device_memory_range().
Update the comment in Avocado test_phybits_low_pse36().
Reviewed-by: Zhao Liu
Signed-off-by: Philippe Mathieu-Daudé
---
XHCI_FLAG_FORCE_PCIE_ENDCAP was only used by the
pc-i440fx-2.0 machine, which got removed. Remove it
and simplify usb_xhci_pci_realize().
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
---
hw/usb/hcd-xhci.h | 1 -
hw/usb/hcd-xhci-nec.c | 2 --
Series fully reviewed.
Since v3:
- Deprecate up to 2.12 (Thomas)
Since v2:
- Addressed Zhao review comments
Since v1:
- Addressed Zhao and Thomas review comments
Kill legacy code, because we need to evolve.
I ended there via dynamic machine -> ICH9 -> legacy ACPI...
This should also help
XHCI_FLAG_SS_FIRST was only used by the pc-i440fx-2.0 machine,
which got removed. Remove it and simplify various functions in
hcd-xhci.c.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
---
hw/usb/hcd-xhci.h | 3 +--
hw/usb/hcd-xhci-nec.c | 2 --
See previous commit for rationale.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i2c/i2c.h | 52 ++--
hw/i2c/core.c| 2 +-
2 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
index
Since v1:
- Convert TYPE_I2C_TARGET definition (Paolo)
Mechanical (mostly) conversion inspired by Wolfram [*] to
use inclusive terminology, similarly to the other renames
we did 3 years ago, shortly before the I2C spec v7 was
published.
This series convert core I2C. Following will convert the
One of the biggest change from I2C spec v6 -> v7 is:
• Updated the terms "master/slave" to "controller/target"
Since it follows the inclusive terminology from the "Conscious
Language in your Open Source Projects" guidelines [*], replace
the I2C terminology.
Mechanical transformation running:
We are going to modify these lines, fix their style
in order to avoid checkpatch.pl warnings:
WARNING: line over 80 characters
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i2c/i2c.h| 11 ++-
include/hw/nvram/eeprom_at24c.h | 6 +-
hw/arm/aspeed.c | 140
We are going to modify these lines, fix their style
in order to avoid checkpatch.pl warnings:
WARNING: Block comments use a leading /* on a separate line
WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on a separate line
Signed-off-by: Philippe
On Tue, Apr 16, 2024 at 02:14:57PM +0100, Peter Maydell wrote:
> On Tue, 16 Apr 2024 at 13:41, Cindy Lu wrote:
> >
> > On Tue, Apr 16, 2024 at 8:30 PM Peter Maydell
> > wrote:
> > >
> > > On Tue, 16 Apr 2024 at 13:29, Cindy Lu wrote:
> > > >
> > > > In function kvm_virtio_pci_vector_use_one(),
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
divd[u, e, eu][o][.]: XO-form
mod{sd, ud} : X-form
With this patch, all the fixed-point arithmetic instructions have been
moved to decodetree.
The changes were
On 4/15/24 23:39, Chinmay Rath wrote:
+static bool trans_MADDHDU(DisasContext *ctx, arg_MADDHDU *a)
...
+tcg_gen_movi_i64(t1, 0);
Drop the movi.
+tcg_gen_add2_i64(t1, cpu_gpr[a->vrt], lo, hi, cpu_gpr[a->rc], t1);
Use tcg_constant_i64(0).
With that,
Reviewed-by: Richard Henderson
+ To: Fred
On Tue, 16 Apr 2024 at 19:56, Alexandra Diupina
wrote:
> Peter, thank you! I agree with you that
> as mentioned in the documentation
> https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field,
> we should take 32 bits of the address from one field
> (for example, case
Hi Bastian,
Thanks for the information. I thought that I can do some prototyping before
the HW arrives. :)
Yes I am interested for your bare metal program boot_to_main run it on
TSIM.
Is Infineon TSIM free? I searched it and I didn't find any download link.
Could you please give a link for that
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the below instructions to decodetree specification :
neg[o][.] : XO-form
mod{sw, uw}, darn : X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which
16.04.2024 20:34, Cole Robinson wrote:
We have a couple patches in f40 that are bug fixes, avoids a crash on
invalid maxcpus for ppc64 guests. First is a prep patch. bug details in
patch 2
commit 2df5c1f5b014126595a26c6797089d284a3b211c
Author: Harsh Prateek Bora
Date: Wed Jan 24 10:30:55
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op'
On 4/16/24 13:03, Peter Maydell wrote:
On Tue, 16 Apr 2024 at 17:53, Don Porter wrote:
There is still a lot I am learning about the code base, but it seems
that qemu_get_guest_memory_mapping() does most of what one would need.
It currently only returns the "leaves" of the page table tree in a
On 4/15/24 23:39, Chinmay Rath wrote:
The handler methods for divw[u] instructions internally use Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if we move
the above said instructions to decodetree, as the ctx->opcode field is not
popluated in decodetree.
Peter, thank you! I agree with you that
as mentioned in the documentation
https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field,
we should take 32 bits of the address from one field
(for example, case 1, SRC_ADDR2_EXT - in code it is desc->source_address2)
and 16 bits (high or
On 4/15/24 23:39, Chinmay Rath wrote:
Moving the following instructions to decodetree specification :
mulli : D-form
mul{lw, lwo, hw, hwu}[.]: XO-form
The changes were verified by validating that the tcg ops generated by those
instructions
On 4/10/24 3:21 AM, Michael Tokarev wrote:
> The following patches are queued for QEMU stable v8.2.3:
>
> https://gitlab.com/qemu-project/qemu/-/commits/staging-8.2
>
> Patch freeze is 2024-04-20, and the release is planned for 2024-04-22:
>
> https://wiki.qemu.org/Planning/8.2
>
> Please
On Tue, Apr 16, 2024 at 03:58:22PM +0100, Jonathan Cameron wrote:
> On Mon, 15 Apr 2024 13:06:04 -0700
> fan wrote:
>
> > From ce75be83e915fbc4dd6e489f976665b81174002b Mon Sep 17 00:00:00 2001
> > From: Fan Ni
> > Date: Tue, 20 Feb 2024 09:48:31 -0800
> > Subject: [PATCH 09/13] hw/cxl/events:
On Tue, Apr 16, 2024 at 04:00:56PM +0100, Jonathan Cameron wrote:
> On Mon, 15 Apr 2024 10:37:00 -0700
> fan wrote:
>
> > On Fri, Apr 12, 2024 at 06:54:42PM -0400, Gregory Price wrote:
> > > On Mon, Mar 25, 2024 at 12:02:28PM -0700, nifan@gmail.com wrote:
> > > > From: Fan Ni
> > > >
> >
On 16-04-2024 15:09, Cédric Le Goater wrote:
Hello,
Please rephrase the subject to something like:
"ppc/pnv: Extend SPI model ..."
Using a verb is preferable.
Sure. Will update. Thank You.
On 4/9/24 19:56, Chalapathi V wrote:
In this commit SPI shift engine and sequencer logic is
On Tue, 16 Apr 2024 at 17:53, Don Porter wrote:
> There is still a lot I am learning about the code base, but it seems
> that qemu_get_guest_memory_mapping() does most of what one would need.
> It currently only returns the "leaves" of the page table tree in a list.
>
> What if I extend this
On 15-04-2024 20:44, Cédric Le Goater wrote:
Hello Chalapathi
The subject could be rephrased to : "ppc/pnv: Add SPI controller model".
On 4/9/24 19:56, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI seeproms, TPM,
On 4/15/24 12:37, Peter Maydell wrote:
On Mon, 15 Apr 2024 at 17:09, Don Porter wrote:
This patch set adds an 'info pg' command to the monitor, which prints
a nicer view of the page tables. A project in my graduate OS course
involves implementing x86 page table support, and my students have
On Tue, Apr 16, 2024 at 03:58:22PM +0100, Jonathan Cameron wrote:
> On Mon, 15 Apr 2024 13:06:04 -0700
> fan wrote:
>
> > From ce75be83e915fbc4dd6e489f976665b81174002b Mon Sep 17 00:00:00 2001
> > From: Fan Ni
> > Date: Tue, 20 Feb 2024 09:48:31 -0800
> > Subject: [PATCH 09/13] hw/cxl/events:
On 4/16/24 11:19, Jamin Lin wrote:
Add a test case to test Aspeed OpenBMC SDK v09.01 on AST2700 board.
It loads u-boot-nodtb.bin, u-boot.dtb, tfa and optee-os
images to dram first which base address is 0x4.
Then, boot and launch 4 cpu cores.
```
qemu-system-aarch64 -machine ast2700-evb
On Tue, Apr 16, 2024 at 04:00:56PM +0100, Jonathan Cameron wrote:
> On Mon, 15 Apr 2024 10:37:00 -0700
> fan wrote:
>
> > On Fri, Apr 12, 2024 at 06:54:42PM -0400, Gregory Price wrote:
> > > On Mon, Mar 25, 2024 at 12:02:28PM -0700, nifan@gmail.com wrote:
> > > > From: Fan Ni
> > > >
> >
On Wed, Apr 17, 2024 at 12:41:16AM +0800, Zhao Liu wrote:
> Hi Peter,
>
> On Tue, Apr 16, 2024 at 02:27:45PM +0100, Peter Maydell wrote:
> > Date: Tue, 16 Apr 2024 14:27:45 +0100
> > From: Peter Maydell
> > Subject: Re: [PATCH] Add zh_TW Traditional Chinese translation
> >
> > On Tue, 16 Apr
On Tue, Apr 16, 2024 at 10:02:53AM +, Jørgen Hansen wrote:
> On 4/15/24 19:56, fan wrote:
> > From 4b9695299d3d4b22f83666f8ab79099ec9f9817f Mon Sep 17 00:00:00 2001
> > From: Fan Ni
> > Date: Tue, 20 Feb 2024 09:48:30 -0800
> > Subject: [PATCH 08/13] hw/cxl/cxl-mailbox-utils: Add mailbox
Hi Peter,
On Tue, Apr 16, 2024 at 02:27:45PM +0100, Peter Maydell wrote:
> Date: Tue, 16 Apr 2024 14:27:45 +0100
> From: Peter Maydell
> Subject: Re: [PATCH] Add zh_TW Traditional Chinese translation
>
> On Tue, 16 Apr 2024 at 14:00, Peter Dave Hello
> wrote:
> >
> > From: Peter Dave Hello
>
On Tue, Apr 16, 2024 at 11:31:24AM +, Peter Dave Hello wrote:
> Date: Tue, 16 Apr 2024 11:31:24 +
> From: Peter Dave Hello
> Subject: [PATCH] Add zh_TW Traditional Chinese translation
>
> From: Peter Dave Hello
> Date: Tue, 16 Apr 2024 00:43:29 +0800
> Subject: [PATCH] Add a simple
On Tue, Apr 16, 2024 at 03:28:41PM +0200, Jürgen Groß wrote:
> On 16.04.24 13:32, Edgar E. Iglesias wrote:
> > On Wed, Apr 10, 2024 at 8:56 PM Peter Xu wrote:
> > >
> > > On Wed, Apr 10, 2024 at 06:44:38PM +0200, Edgar E. Iglesias wrote:
> > > > On Tue, Feb 27, 2024 at 11:37 PM Vikram Garhwal
>
On 4/16/24 11:19, Jamin Lin wrote:
Add AST2700 Evaluation board and its boot command.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
docs/system/arm/aspeed.rst | 39 ++
1 file changed, 35
On 16/04/2024 16.49, Philippe Mathieu-Daudé wrote:
On 16/4/24 16:23, Thomas Huth wrote:
On 16/04/2024 15.52, Philippe Mathieu-Daudé wrote:
Similarly to the commit c7437f0ddb "docs/about: Mark the
old pc-i440fx-2.0 - 2.3 machine types as deprecated",
deprecate the 2.4 to 2.7 machines.
On Tue, 16 Apr 2024 15:01:27 +0800
Jiqian Chen wrote:
> In current code, when guest does S3, virtio-gpu are reset due to the
> bit No_Soft_Reset is not set. After resetting, the display resources
> of virtio-gpu are destroyed, then the display can't come back and only
> show blank after
On 4/16/24 11:18, Jamin Lin wrote:
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ssi/aspeed_smc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index
On 4/16/24 11:18, Jamin Lin wrote:
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous chips such AST2600, AST2500 and AST2400.
Max memory is now
On Fri, 12 Apr 2024 at 08:37, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/i386/kvm/kvm.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
> index e68cbe9293..1fc809b2f9 100644
>
Hello Jamin,
On 4/16/24 11:18, Jamin Lin wrote:
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce dummy AST2700 SLI and SLIIO models.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
On 4/16/24 11:18, Jamin Lin wrote:
Fix coding style issues from checkpatch.pl
Test command:
scripts/checkpatch.pl --no-tree -f hw/misc/aspeed_sdmc.c
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/misc/aspeed_sdmc.c | 11 +++
On 4/16/24 11:18, Jamin Lin wrote:
These macros are no longer used for ASPEED SOCs, so removes them.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/misc/aspeed_sdmc.c | 15 ---
1 file changed, 15 deletions(-)
diff
On Fri, Apr 12, 2024 at 12:33:46AM -0700, Richard Henderson wrote:
> Date: Fri, 12 Apr 2024 00:33:46 -0700
> From: Richard Henderson
> Subject: [PATCH v3 27/27] target/i386/kvm: Improve KVM_EXIT_NOTIFY warnings
> X-Mailer: git-send-email 2.34.1
>
> Signed-off-by: Richard Henderson
> ---
>
On Wed, Apr 10 2024, Thomas Huth wrote:
> On 09/04/2024 09.47, Shaoqin Huang wrote:
>> Hi Thmoas,
>>
>> On 4/9/24 13:33, Thomas Huth wrote:
+ assert_has_feature(qts, "host", "kvm-pmu-filter");
>>>
>>> So you assert here that the feature is available ...
>>>
On Tue, Apr 16, 2024 at 03:52:49PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 16 Apr 2024 15:52:49 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 20/22] hw/i386/pc: Remove deprecated pc-i440fx-2.3
> machine
> X-Mailer: git-send-email 2.41.0
>
> The pc-i440fx-2.3 machine was
On Fri, 1 Mar 2024 10:41:09 -1000
Richard Henderson wrote:
> If translation is disabled, the default memory type is Device, which
> requires alignment checking. This is more optimally done early via
> the MemOp given to the TCG memory operation.
>
> Reviewed-by: Philippe Mathieu-Daudé
>
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