W dniu 3.05.2024 o 17:34, Zenghui Yu pisze:
We wrongly encoded ID_AA64PFR1_EL1 using {3,0,0,4,2} in hvf_sreg_match[] so
we fail to get the expected ARMCPRegInfo from cp_regs hash table with the
wrong key.
Fix it with the correct encoding {3,0,0,4,1}. With that fixed, the Linux
guest can
W dniu 2.05.2024 o 15:13, Peter Maydell pisze:
On Thu, 2 May 2024 at 14:11, Marcin Juszkiewicz
wrote:
W dniu 2.05.2024 o 15:04, Dorjoy Chowdhury pisze:
Should "return" also have "(1 << 24) |" to have MT=1 set?
Otherwise MPIDR_EL1 = 0x000100 can mean core0 in clu
W dniu 2.05.2024 o 15:04, Dorjoy Chowdhury pisze:
Should "return" also have "(1 << 24) |" to have MT=1 set?
Otherwise MPIDR_EL1 = 0x000100 can mean core0 in cluster1 or core1 in
cluster0.
Value 0x1000100 shows MT=1 so thread0 in core1 in cluster0.
I don't know all the details but from what
W dniu 19.04.2024 o 20:31, Dorjoy Chowdhury pisze:
-uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
+uint64_t arm_build_mp_affinity(ARMCPU *cpu, int idx, uint8_t clustersz)
{
+if (cpu->has_smt) {
+/*
+ * Right now, the ARM CPUs with SMT supported by QEMU only
W dniu 2.05.2024 o 12:37, Peter Maydell pisze:
* what are the constraints on the Aff* fields (eg that kernel
commit suggests Aff0 shouldn't be > 15)?
This one is apparently related to GICv3 -- if the GIC doesn't
implement RangeSelector support in ICC_SGI0R_EL1 and other
places
W dniu 22.04.2024 o 17:21, Richard Henderson pisze:
For Arm's CPUs they fall into two categories:
* older ones don't set MT in their MPIDR, and the Aff0
field is effectively the CPU number
* newer ones do set MT in their MPIDR, but don't have
SMT, so their Aff0 is always 0 and their
Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
before we can do that.
Signed-off-by: Peter Maydell
---
I leave it up to the sbsa-ref maintainers exactly when they
want to shift to 1GHz (probably after a TF-A release with the fix?)
Reviewed-by: Marcin Juszkiewicz
TF-A 2.11 will be released in June. It will have several other
W dniu 26.04.2024 o 18:06, Richard Henderson pisze:
Isn't this basically what MPIDR_EL1 is supposed to indicate?
We do not yet implement all of that in QEMU, but should.
QEMU has socket/cluster/core/thread model which could map to
aff3/aff2/aff1/aff0 (or aff0/1/2/3) of MPIDR_EL1 register,
Yining
tested-by: Marcin Juszkiewicz
Thanks. Checked with TF-A and EDK2 patches applied. PPTT table will be
more detailed now.
Reviewed-by: Marcin Juszkiewicz
W dniu 22.04.2024 o 17:37, Marcin Juszkiewicz pisze:
It also seems to be hardcoded in TF-A's support for the virt
board too, annoyingly.
I looked at it and it seems that TF-A can just read what is in
CNTFRQ_EL0 instead of hardcoding the value.
Submitted patch:
https
W dniu 22.04.2024 o 16:18, Peter Maydell pisze:
On Mon, 22 Apr 2024 at 14:38, Marcin Juszkiewicz
From what I see in EDK2 code we read CNTFREQ_EL0:
GetPlatformTimerFreq() checks for PcdArmArchTimerFreqInHz variable which
sbsa-ref has set to 0. So it calls ArmGenericTimerGetTimerFreq
W dniu 22.04.2024 o 14:56, Peter Maydell pisze:
On Fri, 19 Apr 2024 at 19:46, Peter Maydell wrote:
The upshot is that the only CPU type that changes is 'max'; but any
new type we add in future (whether v8.6 or not) will also get the new
1GHz default (assuming we spot in code review any
For quite a while I am experimenting with PCI Express setup on SBSA-Ref
system. And finally decided to write.
We want to play with NUMA setup and "pxb-pcie" can be assigned to NUMA
node other than cpu0 one. But adding it makes other cards dissapear...
When I boot sbsa-ref I have plain PCIe
W dniu 1.04.2024 o 21:55, Liviu Ionescu pisze:
On 1 Apr 2024, at 21:48, Richard
Henderson wrote:
You were told back in September that Ubuntu 18.04 is no longer
supported.
Sorry, I missed that.
BTW, according to ubuntu.com: "With Ubuntu Pro, the 18.04 LTS will be
fully supported until 2028.".
W dniu 28.03.2024 o 16:43, Peter Maydell pisze:
On Tue, 26 Mar 2024 at 09:58, Marcin Juszkiewicz
wrote:
Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA
specifications. Then BBR defines firmware interface.
Added note about DeviceTree data passed from QEMU to firmware
by DeviceTree.
Signed-off-by: Marcin Juszkiewicz
---
docs/system/arm/sbsa.rst | 35 ++-
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
index bca61608ff..2bf22a1d0b 100644
--- a/docs/system/arm
W dniu 27.03.2024 o 17:54, Philippe Mathieu-Daudé pisze:
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 7b548519b5..345c35507f 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -208,6 +208,13 @@ is no longer packaged in any distro making it
I was going through Arm (S)BSA tests run against sbsa-ref. Many of them
check for presence of other cards than "Root Complex Integrated
Endpoint" ones.
The "-device root-pcie-port" etc arguments can be used to add such ones
but I was wondering how to add them directly in C code. Tried to find
by DeviceTree.
Signed-off-by: Marcin Juszkiewicz
---
docs/system/arm/sbsa.rst | 37 -
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
index bca61608ff..d4d1f2efe3 100644
--- a/docs/system/arm
W dniu 25.03.2024 o 11:13, Mostafa Saleh pisze:
Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs
but not nested instances.
This patch series adds support for nested translation in SMMUv3,
this is controlled by property “arm-smmuv3.stage=nested”, and
advertised to guests as
W dniu 22.03.2024 o 19:51, Peter Maydell pisze:
On Tue, 12 Mar 2024 at 08:32, Xiong Yining
xiongyining1480 (2):
hw/arm/sbsa-ref:Enable CPU cluster on ARM sbsa machine
hw/arm/sbsa-ref: Add cpu-map to device tree
Thanks for these patches. I think we should squash the two
patches
W dniu 22.03.2024 o 09:50, Heinrich Schuchardt pisze:
>>> I see no mention of device trees in the spec, but I do see ACPI. Do we
>>> really expect a server platform to use DTs?
>>
>> This platform "kind of" follows sbsa-ref where we have very
>> minimalistic device tree sharing information
W dniu 22.03.2024 o 05:55, Alistair Francis pisze:
I see no mention of device trees in the spec, but I do see ACPI. Do we
really expect a server platform to use DTs?
This platform "kind of" follows sbsa-ref where we have very minimalistic
device tree sharing information qemu->firmware.
(16.11 s)
(11/11) test_sbsaref_openbsd73_max: PASS (16.08 s)
Signed-off-by: Marcin Juszkiewicz
---
Changes in v3:
- left OpenBSD at 7.3 (7.4+ is known to not boot)
https://gitlab.com/qemu-project/qemu/-/issues/2224
https://marc.info/?l=openbsd-arm=171050428327850=2
- added pauth variants
# SPDX-FileContributor: Marcin Juszkiewicz
#
@@ -32,34 +32,36 @@ def fetch_firmware(self):
"""
Flash volumes generated using:
-- Fedora GNU Toolchain version 13.2.1 20230728 (Red Hat 13.2.1-1)
+Toolchain from Debian:
+aarch64-linux-
sbsa-ref is supposed to emulate real hardware so virtio-rng-pci
does not fit here
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 8
1 file changed, 8 deletions(-)
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
b/tests/avocado
PAuth makes run timeout on CI so add tests using 'max' without
it and with impdef one.
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
PAuth makes run timeout on CI so add tests using 'max' without it
and with impdef one.
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 18 ++
1 file changed, 18 insertions(+)
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
b/tests/avocado
W dniu 14.03.2024 o 15:56, Alex Bennée pisze:
If we are not going to delete the entries then at least use a @skip
instead of commenting. Maybe:
@skip("Potential un-diagnosed upstream bug?")
Daniel or Peter suggested to open a GitLab issue and use
W dniu 14.03.2024 o 13:14, Alex Bennée pisze:
+# OpenBSD 7.4 does not boot on current max cpu.
+#
+# def test_sbsaref_openbsd_max_pauth_off(self):
+# """
+# :avocado: tags=cpu:max
+# :avocado: tags=os:openbsd
+# """
+# self.boot_openbsd("max,pauth=off")
If we are
PAuth makes run timeout on CI so add tests using 'max' without it
and with impdef one.
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 18 ++
1 file changed, 18 insertions(+)
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
b/tests/avocado
) test_sbsaref_alpine_linux_max: PASS (80.13 s)
(7/8) test_sbsaref_openbsd_cortex_a57: PASS (16.01 s)
(8/8) test_sbsaref_openbsd_neoverse_n1: PASS (16.05 s)
Signed-off-by: Marcin Juszkiewicz
---
Changes in v2:
- disabled 'max' tests on OpenBSD
- moved tags to 'one tag per line'
- added 'os:linux' tags to Alpine ones
- Link
# SPDX-FileContributor: Marcin Juszkiewicz
#
@@ -32,34 +32,36 @@ def fetch_firmware(self):
"""
Flash volumes generated using:
-- Fedora GNU Toolchain version 13.2.1 20230728 (Red Hat 13.2.1-1)
+Toolchain from Debian:
+aarch64-linux-
sbsa-ref is supposed to emulate real hardware so virtio-rng-pci
does not fit here
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 8
1 file changed, 8 deletions(-)
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
b/tests/avocado
7.4 was released in October 2023, time to update before 7.3 gets dropped.
Disabled tests for 'max' cpu as OpenBSD fails there.
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 47 +++-
1 file changed, 34 insertions(+), 13 deletions
W dniu 13.03.2024 o 12:44, Philippe Mathieu-Daudé pisze:
- :avocado: tags=cpu:cortex-a57
+ :avocado: tags=cpu:cortex-a57,os:openbsd
IIRC for some reason we must use one tag per line... Even if
named 'tags', this is handled as a single tag, so we couldn't
filter on "os:openbsd".
sbsa-ref is supposed to emulate real hardware so virtio-rng-pci
does not fit here
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 8
1 file changed, 8 deletions(-)
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
b/tests/avocado
# SPDX-FileContributor: Marcin Juszkiewicz
#
@@ -32,34 +32,36 @@ def fetch_firmware(self):
"""
Flash volumes generated using:
-- Fedora GNU Toolchain version 13.2.1 20230728 (Red Hat 13.2.1-1)
+Toolchain from Debian:
+aarch64-linux-
7.4 was released in October 2023, time to update before 7.3 gets dropped.
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
b
Juszkiewicz
---
Marcin Juszkiewicz (3):
tests/avocado: update sbsa-ref firmware
tests/avocado: drop virtio-rng from sbsa-ref tests
tests/avocado: use OpenBSD 7.4 for sbsa-ref
tests/avocado/machine_aarch64_sbsaref.py | 74 +++-
1 file changed, 34
W dniu 4.03.2024 o 11:25, Fei Wu pisze:
The RISC-V Server Platform specification[1] defines a standardized
set of hardware and software capabilities, that portable system
software, such as OS and hypervisors can rely on being present in a
RISC-V server platform. This patchset provides a RISC-V
There is no point in checking do we have PCIe if first thing after check
is adding PCIe card without checking.
Signed-off-by: Marcin Juszkiewicz
---
hw/arm/sbsa-ref.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index f2adf30337
W dniu 15.02.2024 o 9:52 AM, Dmitry Baryshkov pisze:
If we want to actually go there, I think the best option for PCMCIA
support is likely to replace the entire "soc_common" pcmcia driver
with a simple drivers/pata/ storage driver and no support for
other cards.
hmm, main usage for PCMCIA/CF
W dniu 14.02.2024 o 1:26 PM, Dmitry Baryshkov pisze:
The thriving world of PostmarketOS only exist because Google was
clever to realize devices should have a developer mode.
There were two projects that worked on reenabling phones and PDAs from
that era, hack'n'dev and handhelds.org. I think
W dniu 12.02.2024 o 15:36, Guenter Roeck pisze:
The machines I have in mind are:
PXA2xx machines:
akita Sharp SL-C1000 (Akita) PDA (PXA270)
borzoi Sharp SL-C3100 (Borzoi) PDA (PXA270)
connex Gumstix Connex (PXA255)
mainstone Mainstone II
CPU cluster on ARM sbsa machine
hw/arm/sbsa-ref: Add cpu-map to device tree
hw/arm/sbsa-ref.c | 36
1 file changed, 36 insertions(+)
Tested-by: Marcin Juszkiewicz
Booted system with "-smp 8,sockets=2,clusters=2,cores=1,threads=2" and
got wha
W dniu 27.12.2023 o 13:07, Xiong Yining pisze:
From: xiongyining1480
Support CPU topology description through device tree.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
---
hw/arm/sbsa-ref.c | 35 +++
1 file changed, 35 insertions(+)
diff --git
W dniu 18.12.2023 o 12:32, Peter Maydell pisze:
Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the
Neoverse N2 and Neoverse V1 CPUs. We continue to downgrade FEAT_NV2
support to FEAT_NV for the latter two CPU types.
According to Neoverse-V1 TRM r1p2 it has FEAT_NV2. Similar
W dniu 8.12.2023 o 20:09, Cleber Rosa pisze:
The tests under machine_aarch64_virt.py do not need read-write access
to the ISOs. The ones under machine_aarch64_sbsaref.py, on the other
hand, will need read-write access, so let's give each test an unique
file.
And while at it, let's use a single
W dniu 27.11.2023 o 00:12, Gavin Shan pisze:
@@ -2939,6 +2900,28 @@ static void virt_machine_class_init(ObjectClass *oc,
void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
+static const char * const valid_cpu_types[] = {
W dniu 27.11.2023 o 00:12, Gavin Shan pisze:
After the series is applied:
[gshan@gshan q]$ ./build/qemu-system-aarch64 -M virt -cpu cortex-a8
qemu-system-aarch64: Invalid CPU type: cortex-a8
The valid types are: cortex-a7, cortex-a15, cortex-a35, cortex-a55, \
W dniu 20.11.2023 o 01:27, Gavin Shan pisze:
Testing
===
With the following command lines, the output messages are varied before
and after the series is applied.
./build/qemu-system-aarch64\
-accel tcg -machine virt,gic-version=3 \
-cpu cortex-a8 -smp maxcpus=2,cpus=1
I noticed that Neoverse-V1 has FEAT_RNG enabled so let enable it also on
Neoverse-N2.
Signed-off-by: Marcin Juszkiewicz
---
target/arm/tcg/cpu64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 08db1dbcc7..fcda99e158
/ahci: simplify and document PxCI handling")
Reported-by: Marcin Juszkiewicz
Signed-off-by: Niklas Cassel
Tested-by: Marcin Juszkiewicz
FreeBSD 14-rc3 boots fine on AArch64 with this patch:
Trying to mount root from cd9660:/dev/iso9660/14_0_RC3_AARCH64_BO [ro]...
cd0 at ahcich0 bus 0 scbus0 ta
would fail to reset.
The problem was not noticed in Linux, because Linux uses a COMRESET
instead of a legacy software reset by default.
Fixes: e2a5d9b3d9c3 ("hw/ide/ahci: simplify and document PxCI handling")
Reported-by: Marcin Juszkiewicz
Signed-off-by: Niklas Cassel
Sorry, I misse
W dniu 3.10.2023 o 22:41, Niklas Cassel pisze:
On Tue, Oct 03, 2023 at 08:11:39PM +0300, Michael Tokarev wrote:
Were you able to take a look at what's going on here? I wish I were
able to help here but I know right to nothing about ahci emulation..
I was away on a conference all last week,
W dniu 8.09.2023 o 15:29, Marcin Juszkiewicz pisze:
W dniu 31.08.2023 o 12:05, Marcin Juszkiewicz pisze:
W dniu 30.08.2023 o 23:48, Michael S. Tsirkin pisze:
current code sets PCI_SEC_LATENCY_TIMER to WO, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec which says
Update prebuilt firmware images:
- Neoverse V1/N2 cpu support
- non-secure EL2 virtual timer
- XHCI controller in DSDT
With those changes we can now run OpenBSD as part of sbsa-ref tests.
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 68
:
- added OpenBSD test
- decided to not run Neoverse-V1 tests
Marcin Juszkiewicz (1):
tests/avocado: update firmware to enable OpenBSD test on sbsa-ref
tests/avocado/machine_aarch64_sbsaref.py | 68
1 file changed, 58 insertions(+), 10 deletions(-)
--
2.41.0
I work on SBSA Reference Platform (sbsa-ref) at Linaro. And yesterday I
wanted to check how non-Linux operating systems work on sbsa-ref machine.
One of them was FreeBSD 13.2 - the latest one. Fetched bootonly ISO
image [1] and booted system.
1.
1 fixes a few minor errors in the A710 definition
that I spotted while I was cross-checking it against the
N2 TRM to see what had changed.
Patch 2 is the new CPU model.
Tested-by: Marcin Juszkiewicz
root@sbsa-ref:~# lscpu
Architecture: aarch64
CPU op-mode(s): 32-bit, 64-bit
+---
5 files changed, 54 insertions(+), 29 deletions(-)
create mode 100644 include/hw/arm/bsa.h
Tested-by: Marcin Juszkiewicz
Reviewed-by: Marcin Juszkiewicz
Update prebuilt firmware images to have TF-A with Neoverse V1 support enabled.
This allowed us to enable test for this cpu in sbsa-ref machine.
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 25 ++--
1 file changed, 15 insertions(+), 10
W dniu 14.09.2023 o 14:01, Leif Lindholm pisze:
While reviewing Marcin's patch this morning, cross referencing different
specifications and looking at various places around the source code in
order to convinced myself he really hadn't missed something out (the
existing plumbing made it *so*
END
--
On Armv8.0 cpus this timer should not exist as there is no VHE.
I hope this code is correct. Tried to compare with other emulation
targets but only "virt" and "sbsa-ref" use cpu cores newer than v8.0
ones.
Marcin Juszkiewicz (1):
sbsa-
Armv8.1+ cpus have Virtual Host Extension (VHE) which added non-secure
EL2 virtual timer.
This change adds it to fullfil Arm BSA (Base System Architecture)
requirements.
Signed-off-by: Marcin Juszkiewicz
---
hw/arm/sbsa-ref.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/sbsa
I am working on aarch64/sbsa-ref machine so people can have virtual
machine to test their OS against something reminding standards compliant
system.
One of tools I use is BSA ACS (Base System Architecture - Architecture
Compliance Suite) [1] written by Arm. It runs set of tests to check does
W dniu 31.08.2023 o 12:05, Marcin Juszkiewicz pisze:
W dniu 30.08.2023 o 23:48, Michael S. Tsirkin pisze:
current code sets PCI_SEC_LATENCY_TIMER to WO, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec which says:
This register does not apply to PCI Express
W dniu 2.09.2023 o 20:11, Liviu Ionescu pisze:
When trying to build 8.1.0 on an Ubuntu 18.04 aarch64, I get the
above error.
Ubuntu 18.04 is not supported anymore by Canonical. End-Of-Life was in
May 2023.
The offending code in `/util/cpuinfo-aarch64.c` is:
> ```c
> #ifdef CONFIG_LINUX
>
Express to PCI/PCI-X Bridges, refer to the
[PCIe-to-PCI-PCI-X-Bridge] for requirements for this register.
also, fix typo in comment where it's make writeable - this typo
is likely what prevented us noticing we violate this requirement
in the 1st place.
Reported-by: Marcin Juszkiewicz
Signed-off
W dniu 29.08.2023 o 22:46, Michael S. Tsirkin pisze:
On Tue, Aug 29, 2023 at 10:44:08PM +0200, Marcin Juszkiewicz wrote:
W dniu 29.08.2023 o 22:40, Michael S. Tsirkin pisze:
It passes with sbsa-ref (which is not using QEMU versioning).
Fails (as expected) when used new property for each pcie
W dniu 29.08.2023 o 19:07, Michael S. Tsirkin pisze:
No - it depends on secondart bus type and only applies to bridges.
Also we need compat machinery.
Marcin could you pls test the following?
Works fine:
822 : Check Type 1 config header rules : Result: PASS
diff --git
W dniu 29.08.2023 o 22:40, Michael S. Tsirkin pisze:
It passes with sbsa-ref (which is not using QEMU versioning).
Fails (as expected) when used new property for each pcie-root-port
(ignore line breaks):
"-device pcie-root-port,
x-pci-express-writeable-slt-bug=true,
W dniu 29.08.2023 o 22:18, Michael S. Tsirkin pisze:
On Tue, Aug 29, 2023 at 10:05:47PM +0200, Marcin Juszkiewicz wrote:
W dniu 29.08.2023 o 19:07, Michael S. Tsirkin pisze:
No - it depends on secondart bus type and only applies to bridges.
Also we need compat machinery.
Marcin could you pls
W dniu 29.08.2023 o 15:57, Philippe Mathieu-Daudé pisze:
On 29/8/23 13:39, Marcin Juszkiewicz wrote:
Does someone know where the problem may be? And how to fix it?
Commit fb23162885 ("pci: initialize pci config headers depending it pci
header type.") sets PCI_SEC_LATENCY_TIME
I am working on aarch64/sbsa-ref machine so people can have virtual
machine to test their OS against something reminding standards compliant
system.
One of tools I use is BSA ACS (Base System Architecture - Architecture
Compliance Suite) [1] written by Arm. It runs set of tests to check does
W dniu 10.08.2023 o 19:12, Peter Maydell pisze:
On Thu, 10 Aug 2023 at 18:05, Richard Henderson
On 8/10/23 08:49, Peter Maydell wrote:
On Thu, 10 Aug 2023 at 03:36, Richard Henderson
Will sbsa-ref want this core ?
It only has 40 PA bits, and I think sbsa-ref requires 48.
Yes, it does
W dniu 13.07.2023 o 14:34, Gavin Shan pisze:
On 7/13/23 21:52, Marcin Juszkiewicz wrote:
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that what the
user specifies is not "cortex-a8-arm-cpu" but "cortex-a8", why
do we i
W dniu 13.07.2023 o 13:44, Peter Maydell pisze:
I see this isn't a change in this patch, but given that
what the user specifies is not "cortex-a8-arm-cpu" but
"cortex-a8", why do we include the "-arm-cpu" suffix in
the error messages? It's not valid syntax to say
"-cpu cortex-a8-arm-cpu", so
(TYPE_XHCI_SYSBUS);
+qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
Looks like tab instead of spaces.
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
Tested-by: Marcin Juszkiewicz
Reviewed-by: Marcin J
W dniu 10.07.2023 o 09:28, Richard Henderson pisze:
hw/usb/hcd-xhci-nec.c: DEFINE_PROP_UINT32("slots", XHCINecState,
slots, XHCI_MAXSLOTS),
hw/usb/hcd-xhci-sysbus.c: DEFINE_PROP_UINT32("slots",
XHCISysbusState, xhci.numslots, XHCI_MAXSLOTS),
The default is XCHI_MAXSLOTS, not 1. So I
W dniu 6.07.2023 o 17:25, Jean-Philippe Brucker pisze:
(Note that there is an issue with TF-A missing ENABLE_FEAT_FGT for qemu at
the moment, which prevents booting Linux with -cpu max. I'll send the fix
to TF-A after this, but this reproducer should at least boot edk2.)
Which reminds me that
W dniu 4.07.2023 o 16:54, Philippe Mathieu-Daudé pisze:
On 4/7/23 15:35, Marcin Juszkiewicz wrote:
W dniu 4.07.2023 o 15:06, Peter Maydell pisze:
This patchset implements the Cortex Neoverse-V1 CPU type, as a
representative Armv8.3 (+ some extras from 8.4) CPU matching real
hardware
W dniu 4.07.2023 o 15:21, Peter Maydell pisze:
Just to be clear about the status of this patch, I don't
have a problem with the code changes, but it does definitely
need a much clearer commit message to explain why we're changing
the way we handle the PCI controller. So I'm dropping this from
I can add "reach SBSA level 4" to todo list as it requires v8.3 cpu
(I do not count 'max' cpu type).
Tested-by: Marcin Juszkiewicz
Add PCI Express information into DeviceTree as part of SBSA-REF
versioning.
Trusted Firmware will read it and provide to next firmware level.
Signed-off-by: Marcin Juszkiewicz
---
hw/arm/sbsa-ref.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw
W dniu 21.06.2023 o 05:46, Yuquan Wang pisze:
On 2023-06-21 01:24, Leif wrote:
> > Leif, do you think we should bump the minor version here?
> I think that makes sense, yes.
There is a new confusion: Which minor version should I bump to (2 or 3) ?
As I found that Marcin’s latest patch (add
From: Shashi Mallela
Create ITS as part of SBSA platform GIC initialization.
GIC ITS information is in DeviceTree so TF-A can pass it to EDK2.
Bumping platform version to 0.2 as this is important hardware change.
Signed-off-by: Shashi Mallela
Co-authored-by: Marcin Juszkiewicz
Signed-off
In 2021 Shashi Mallela sent v8 of GIC ITS patchset [1]. At that time it
was decided to do platform versioning first.
1.
https://lore.kernel.org/qemu-devel/20210812165341.40784-8-shashi.mall...@linaro.org/
Now we are going through our list of changes for SBSA Reference Platform
and GIC ITS is
W dniu 19.06.2023 o 14:55, Peter Maydell pisze:
On Tue, 6 Jun 2023 at 19:24, Marcin Juszkiewicz
wrote:
We need GIC ITS information in DeviceTree so TF-A can pass it to EDK2.
Bumping platform version to 0.2 as this is important hardware change.
We should fold this patch into the previous
W dniu 19.06.2023 o 14:41, Peter Maydell pisze:
I'm going to apply this to target-arm.next with this squashed in
to fix a few grammar/format nits and add some text from the comment
in the source file about the platform version part.
Thanks.
My English grammar sucks so I am glad that you
-by: Yuquan Wang
Reviewed-by: Marcin Juszkiewicz
W dniu 7.06.2023 o 16:33, Philippe Mathieu-Daudé pisze:
On 30/5/23 17:22, Marcin Juszkiewicz wrote:
Update prebuilt firmware images to have TF-A with FEAT_FGT support
enabled. This allowed us to enable test for "max" cpu in sbsa-ref
machine.
Signed-off-by: Marcin Juszkiewicz
-
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Thomas Huth
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 0f42c556d7..4484de67e8 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -249,6 +249,7 @@ config SBSA_REF
select PL061
From: Shashi Mallela
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index
will be placed in DeviceTree for firmware to use - that's a
job for second patch. Which also bumps platform version to 0.2 version.
Trusted Firmware will read GIC ITS address and provide to EDK2 via
Secure Monitor Call (SMC). Same way as it is done with GIC addresses
already.
Marcin Juszkiewicz (1):
hw/arm
We need GIC ITS information in DeviceTree so TF-A can pass it to EDK2.
Bumping platform version to 0.2 as this is important hardware change.
Signed-off-by: Marcin Juszkiewicz
---
hw/arm/sbsa-ref.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/arm/sbsa-ref.c b
W dniu 5.06.2023 o 11:55, Yuquan Wang pisze:
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capablity instead of EHCI.
Please also modify
W dniu 6.06.2023 o 12:04, Peter Maydell pisze:
On Tue, 6 Jun 2023 at 10:47, Marcin Juszkiewicz
wrote:
W dniu 5.06.2023 o 11:55, Yuquan Wang pisze:
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses
Reviewed-by: Marcin Juszkiewicz
Without EDK2 changes Linux behaves same way (no USB found), with EDK2
changes (EHCI->XHCI) Linux gets USB devices.
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