On 4/24/24 10:50 AM, Philippe Mathieu-Daudé wrote:
Hi Marek,
On 18/4/24 14:04, Marek Vasut wrote:
On 4/18/24 1:10 PM, Philippe Mathieu-Daudé wrote:
On 27/3/24 15:48, Philippe Mathieu-Daudé wrote:
The Nios II target is deprecated since v8.2 in commit 9997771bc1
("target/nios2: Depr
on hardware, either for treewide
changes, or by code inspection. The only notable exceptions I could
find are from Andreas Oetken and Bernd Weiberg at Siemens and
from Marek Vasut (all added to Cc in case they have something to add).
I might still have the 10M50 board, but it wasn't powered for a very
On 4/18/24 7:53 AM, Thomas Huth wrote:
On 18/04/2024 05.27, Sandra Loosemore wrote:
Tomorrow I plan to push patches to mark the nios2 target as obsolete
in GCC 14.
Background: Intel has EOL'ed the Nios II processor IP and is now
directing their FPGA customers to a RISC-V platform instead.
10m50-ghrd & nios2-generic-nommu machines)
- Tests
Cc: Marek Vasut
Signed-off-by: Philippe Mathieu-Daudé
Thank you
[2]
https://lore.kernel.org/qemu-devel/805fc7b5-03f0-56d4-abfd-ed010d4fa...@denx.de/
Signed-off-by: Philippe Mathieu-Daudé
Yes please, go for it, from my side:
Acked-by: Marek Vasut
On 6/11/20 12:27 AM, Philippe Mathieu-Daudé wrote:
> On 6/10/20 11:13 PM, Sven Schnelle wrote:
>> On Mon, Jun 08, 2020 at 12:17:11AM +0200, Philippe Mathieu-Daudé wrote:
>>> Hi Sven, could you review thiw one-line patch?
>>>
>>> On 4/18/20 2:25 AM, Mare
On 4/18/20 2:25 AM, Marek Vasut wrote:
> The tulip driver claims to emulate dec21143 and it does not emulate dec21142.
> The dec21142 and dec21143 can be discerned by the PCI revision register,
> where dec21142 reports value < 0x20 and dec21143 value >= 0x20. E.g. the
> U-Boot '
rifies that the
PCI revision ID is >= 0x20, otherwise refuses to operate such a card.
This patch sets the PCI revision ID to 0x20 to match the dec21143 and
thus also permits e.g. U-Boot to work with the tulip emulation.
Fixes: 34ea023d4b95 ("net: add tulip (dec21143) driver")
Signed-off-by: Ma
On 09/11/2018 05:08 PM, Alex Bennée wrote:
>
> Marek Vasut writes:
>
>> On 09/11/2018 04:14 PM, Laurent Vivier wrote:
>>> Le 11/09/2018 à 16:06, Alex Bennée a écrit:
>>>> This is to work around the limitations of the buildroot
>>>> qemu_nios2_10
t;4.16.0"
>>
>> struct target_pt_regs {
>> unsigned long r8;/* r8-r15 Caller-saved GP registers */
>>
>
> I have no objection. Perhaps you could ask NiosII Maintainers (cc).
If that's needed, so be it. The Linux 3.19 was required because some
obscure ABI change happened at that point.
--
Best regards,
Marek Vasut
On 05/18/2018 10:19 PM, Julian Brown wrote:
> On Fri, 18 May 2018 21:52:04 +0200
> Marek Vasut <ma...@denx.de> wrote:
>
>> On 05/18/2018 09:23 PM, Julian Brown wrote:
>>> This patch (by Sandra Loosemore, mildly rebased) adds support for
>>> semih
cery.com>
Is there some documentation for this stuff ? It looks interesting, but
how can I try it here ?
[...]
--
Best regards,
Marek Vasut
on vectors and reset CPU for it to take effect.
> */
> +cpu->reset_addr = 0xd000; //0xd400;
> +cpu->exception_addr = 0xc8000120;
> +cpu->fast_tlb_miss_addr = 0x7fff400; //0xc100;
This //0xfoo should probably go away
--
Best regards,
Marek Vasut
gies for the noise!
Success !
--
Best regards,
Marek Vasut
re unchanged.
>
> OK, or any comments?
Same problem as with v1, git format-patch + git send-email please.
--
Best regards,
Marek Vasut
re unchanged.
>
> OK, or any comments?
Same problem as with v2, git format-patch + git send-email please.
--
Best regards,
Marek Vasut
dard for CAN devices.
[...]
--
Best regards,
Marek Vasut
On 10/10/2017 05:19 PM, Paolo Bonzini wrote:
> On 10/10/2017 10:58, Marek Vasut wrote:
>>> #0 0x77931945 in pthread_cond_wait@@GLIBC_2.3.2 () at
>>> /lib64/libpthread.so.0
>>> #1 0x557cf9c5 in qemu_cond_wait (cond=cond@entry=0x55b5f9c0
>>
On 10/10/2017 10:15 AM, Thomas Huth wrote:
> On 10.10.2017 09:57, Marek Vasut wrote:
>> On 10/10/2017 09:20 AM, Thomas Huth wrote:
>>> Hi Chris, hi Marek,
>>
>> Hi,
>>
>>> I recently noticed that when I start qemu-system-nios2 (build from the
>>&
down right and
> hangs somewhere in pause_all_vcpus() forever.
> Do you have any idea what might be wrong here?
Nope, can you debug it and ev. send patch ? We're talking about git
HEAD, right ?
> Thanks,
> Thomas
>
--
Best regards,
Marek Vasut
On 07/13/2017 09:59 PM, Programmingkid wrote:
>
> On Jul 13, 2017, at 3:01 PM, Marek Vasut wrote:
>
>> On 07/13/2017 08:23 PM, Programmingkid wrote:
>>>
>>> On Jul 13, 2017, at 10:48 AM, Marek Vasut wrote:
>>>
>>>> On 07/13/2017 04:28 PM,
On 07/13/2017 08:23 PM, Programmingkid wrote:
>
> On Jul 13, 2017, at 10:48 AM, Marek Vasut wrote:
>
>> On 07/13/2017 04:28 PM, Programmingkid wrote:
>>> Hi I have recently created a new documentation page for the Nios2 target. I
>>> would greatly appre
2
is I believe Altera specific. And we only support Nios2 R1 EL thus far.
> Page: http://wiki.qemu.org/Documentation/Platforms/Nios2
>
--
Best regards,
Marek Vasut
L, 0,
>> rx_fifo_size),
>
> This should now be
>
> VMSTATE_VBUFFER_UINT32(rx_fifo, AlteraJUARTState, 1, NULL,
> rx_fifo_size),
>
> due to commit 59046ec29ad4 ("migration: consolidate VMStateField.start")
> getting rid of the _start macro argument.
>
Cool, thanks for checking. Can we get a V7 ?
--
Best regards,
Marek Vasut
On 03/17/2017 05:51 PM, Peter Maydell wrote:
> On 27 February 2017 at 19:38, Marek Vasut <ma...@denx.de> wrote:
>> Add a const qom link between the CPU and the IIC instead
>> of passing the CPU link through a qom property.
>>
>> Signed-off-by: Marek Vasut <ma..
On 03/17/2017 06:09 PM, Markus Armbruster wrote:
> Marek Vasut <ma...@denx.de> writes:
>
>> Add a const qom link between the CPU and the IIC instead
>> of passing the CPU link through a qom property.
>>
>> Signed-off-by: Marek Vasut <ma...@denx.de>
&
Add a const qom link between the CPU and the IIC instead
of passing the CPU link through a qom property.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Alexander Graf <ag...@suse.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Igor Mammedov <imamm...@redhat.com>
Cc: Jeff Da Si
On 02/27/2017 08:38 PM, Marek Vasut wrote:
> Add a const qom link between the CPU and the IIC instead
> of passing the CPU link through a qom property.
>
> Signed-off-by: Marek Vasut <ma...@denx.de>
> Cc: Alexander Graf <ag...@suse.de>
> Cc: Chris Wulff <crwu.
On 02/27/2017 01:37 PM, Igor Mammedov wrote:
> On Sun, 26 Feb 2017 17:48:15 +0100
> Marek Vasut <ma...@denx.de> wrote:
>
>> Add a const qom link between the CPU and the IIC instead
>> of passing the CPU link through a qom property.
>>
>> Signed-off-by: Marek
Add a const qom link between the CPU and the IIC instead
of passing the CPU link through a qom property.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Alexander Graf <ag...@suse.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Igor Mammedov <imamm...@redhat.com>
Cc: Jeff Da Si
On 02/22/2017 07:31 PM, Markus Armbruster wrote:
> Marek Vasut <ma...@denx.de> writes:
>
>> On 02/22/2017 07:31 AM, Markus Armbruster wrote:
>>> I know this has been committed already, but here goes anyway:
>>>
>>> Marek Vasut <ma...@denx.de> wr
Add a const qom link between the CPU and the IIC instead
of passing the CPU link through a qom property.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Alexander Graf <ag...@suse.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon T
On 02/22/2017 07:31 AM, Markus Armbruster wrote:
> I know this has been committed already, but here goes anyway:
>
> Marek Vasut <ma...@denx.de> writes:
>
>> From: Chris Wulff <crwu...@gmail.com>
>>
>> Add the Altera Nios2 internal interrupt controller m
t;juro.bystri...@intel.com>
Acked-by: Marek Vasut <ma...@denx.de>
--
Best regards,
Marek Vasut
rq);
> +}
[...]
> +typedef struct AlteraJUARTState {
> +SysBusDevice busdev;
> +MemoryRegion mmio;
> +CharBackend chr;
> +qemu_irq irq;
> +
> +unsigned int rx_fifo_size;
> +unsigned int rx_fifo_pos;
> + unsigned int rx_fifo_len;
> +uint32_t jdata;
> +uint32_t jcontrol;
> +uint8_t *rx_fifo;
> +} AlteraJUARTState;
> +
> +void altera_juart_create(int channel, const hwaddr addr, qemu_irq irq,
> +uint32_t fifo_size);
Fix the alignment here so it doesn't look so braindead, align under the
first open parenthesis.
> +#endif /* ALTERA_JUART_H */
>
--
Best regards,
Marek Vasut
ever ffs is rejected by checkpatch as non-portable
> libc call.
Doesn't it suggest to use ctz32() ?
https://lists.gnu.org/archive/html/qemu-devel/2015-03/msg03661.html
>>> +#define DEFAULT_FIFO_SIZE 64
>>
>> This is still not QOM property , why ?
>>
>
> Not sure what you mean, the code has:
>
> DEFINE_PROP_UINT32("fifo-size", AlteraJUARTState, rx_fifo_size,
> DEFAULT_FIFO_SIZE),
Ah ok, I missed that (and that should've been part of the changelog for
example ... )
--
Best regards,
Marek Vasut
ra_juart.h
> new file mode 100644
> index 000..8b0a4a6
> --- /dev/null
> +++ b/include/hw/char/altera_juart.h
> @@ -0,0 +1,46 @@
> +/*
> + * Altera JTAG UART emulation
> + *
> + * Copyright (c) 2016-2017 Intel Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef ALTERA_JUART_H
> +#define ALTERA_JUART_H
> +
> +#include "hw/sysbus.h"
> +#include "sysemu/char.h"
> +
> +/*
> + * The read and write FIFO depths can be set from 8 to 32,768 bytes.
> + * Only powers of two are allowed. A depth of 64 is generally optimal for
> + * performance, and larger values are rarely necessary.
> + */
> +
> +#define DEFAULT_FIFO_SIZE 64
This is still not QOM property , why ?
> +typedef struct AlteraJUARTState {
> +SysBusDevice busdev;
> +MemoryRegion mmio;
> +CharBackend chr;
> +qemu_irq irq;
> +
> +unsigned int rx_fifo_size;
> +unsigned int rx_fifo_pos;
> +unsigned int rx_fifo_len;
> +uint32_t jdata;
> +uint32_t jcontrol;
> +uint8_t *rx_fifo;
> +} AlteraJUARTState;
> +
> +void altera_juart_create(int channel, const hwaddr addr, qemu_irq irq,
> +uint32_t fifo_size);
> +
> +#endif /* ALTERA_JUART_H */
>
--
Best regards,
Marek Vasut
= altera_juart_read,
> .write = altera_juart_write,
> .endianness = DEVICE_LITTLE_ENDIAN,
> .valid = {
> .min_access_size = 4,
> .max_access_size = 4
> }
> };
This answers my question , thanks.
--
Best regards,
Marek Vasut
g about?
>>
>> By real hardware I mean real Nios2 system ...
>>
>>> If "real hardware" contains MMU or MPU then an exception is generated on
>> misalign access.
>>
>> Is this handled here or not ?
>>
>
> Sorry, I am not sure I understand the question.
> Exceptions are handled by interrupt controller.
> This code for JTAG UART does not have any misaligned accesses.
>
>
The code running on nios2 can issue unaligned access to the jtag uart
registers, yes ? If that happens, what happens on real HW and how is
this emulated ?
--
Best regards,
Marek Vasut
ART_H
>>>>> +
>>>>> +#include "hw/sysbus.h"
>>>>> +#include "sysemu/char.h"
>>>>> +
>>>>> +/*
>>>>> + * The read and write FIFO depths can be set from 8 to 32,768 bytes.
>>>>> + * Only powers of two are allowed. A depth of 64 is generally optimal
>>>> for
>>>>> + * performance, and larger values are rarely necessary.
>>>>> + */
>>>>> +
>>>>> +#define FIFO_LENGTH 64
>>>>
>>>> Should probably be a QOM property, no ?
>>>
>>> Did not want to mess with dynamic FIFO buffer allocation.
>>
>> You probably should, since this is configurable at the FPGA level (in
>> QSys), right ?
>>
>
> OK, will implement fifo size as a property
>
>
> Thanks
> Juro
>
--
Best regards,
Marek Vasut
y necessary.
>>> + */
>>> +
>>> +#define FIFO_LENGTH 64
>>
>> Should probably be a QOM property, no ?
>
> Did not want to mess with dynamic FIFO buffer allocation.
You probably should, since this is configurable at the FPGA level (in
QSys), right ?
>>
; + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef ALTERA_JUART_H
> +#define ALTERA_JUART_H
> +
> +#include "hw/sysbus.h"
> +#include "sysemu/char.h"
> +
> +/*
> + * The read and write FIFO depths can be set from 8 to 32,768 bytes.
> + * Only powers of two are allowed. A depth of 64 is generally optimal for
> + * performance, and larger values are rarely necessary.
> + */
> +
> +#define FIFO_LENGTH 64
Should probably be a QOM property, no ?
> +typedef struct AlteraJUARTState {
> +SysBusDevice busdev;
> +MemoryRegion mmio;
> +CharBackend chr;
> +qemu_irq irq;
> +
> +unsigned int rx_fifo_pos;
> +unsigned int rx_fifo_len;
> +uint32_t jdata;
> +uint32_t jcontrol;
> +uint8_t rx_fifo[FIFO_LENGTH];
> +} AlteraJUARTState;
> +
> +void altera_juart_create(int channel, const hwaddr addr, qemu_irq irq);
> +
> +#endif /* ALTERA_JUART_H */
>
btw for trivial patches like this, cover letter is not necessary .
--
Best regards,
Marek Vasut
On 01/18/2017 08:33 PM, Richard Henderson wrote:
> On 01/16/2017 04:44 PM, Marek Vasut wrote:
>> +TCGv_i32 tmp = tcg_const_i32(instr.imm5 + 32);
>> +gen_helper_mmu_write(dc->cpu_env, tmp, load_gpr(dc, instr.a));
>> +tcg_temp_free_i32(tmp);
>
ios2-opc.c
opcodes/nios2-dis.c
Checkpatch says total: 114 errors, 0 warnings, 3609 lines checked , which
is caused by a different coding style in those files. These warnings and
errors are not addressed To let these files be easily synchronized between
binutils and qemu.
Signed-off-by: Marek
On 01/18/2017 08:35 PM, Richard Henderson wrote:
> On 01/16/2017 04:44 PM, Marek Vasut wrote:
>> +F: target-nios2/
>
> Filename change.
>
> r~
OK
--
Best regards,
Marek Vasut
From: Chris Wulff <crwu...@gmail.com>
Add support for emulating Altera NiosII R1 architecture into qemu.
This patch is based on previous work by Chris Wulff from 2012 and
updated to latest mainline QEMU.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.c
Add remaining bits of the Altera NiosII R1 support into qemu, which
is documentation, MAINTAINERS file entry, configure bits, arch_init
and configuration files for both linux-user (userland binaries) and
softmmu (hardware emulation).
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris
Add the Altera 10M50 Nios2 GHRD model. This allows emulating the
10M50 development kit with the Nios2 GHRD loaded in the FPGA. It
is possible to boot Linux kernel and run userspace, thus far only
from initrd as storage support is not yet implemented.
Signed-off-by: Marek Vasut <ma...@denx.de&
From: Chris Wulff <crwu...@gmail.com>
Add the Altera timer model.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loosemore <san...@codesourcery.
Add missing bits for qemu-user required for emulating Altera Nios2
userspace binaries.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loosemore <san...
dra Loosemore <san...@codesourcery.com>
Cc: Yves Vandervennet <yvand...@altera.com>
Cc: Alexander Graf <ag...@suse.de>
Cc: Richard Henderson <r...@twiddle.net>
Chris Wulff (3):
nios2: Add architecture emulation support
nios2: Add IIC interrupt controller emulation
nios2:
From: Chris Wulff <crwu...@gmail.com>
Add the Altera Nios2 internal interrupt controller model.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loos
On 01/17/2017 09:16 AM, Alexander Graf wrote:
>
>
>> Am 17.01.2017 um 01:18 schrieb Marek Vasut <ma...@denx.de>:
>>
>>> On 01/16/2017 11:21 PM, Alexander Graf wrote:
>>>
>>>
>>>> On 31/12/2016 14:22, Marek Vasut wrote:
&
Add missing bits for qemu-user required for emulating Altera Nios2
userspace binaries.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loosemore <san...
From: Chris Wulff <crwu...@gmail.com>
Add the Altera timer model.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loosemore <san...@codesourcery.
ios2-opc.c
opcodes/nios2-dis.c
Checkpatch says total: 114 errors, 0 warnings, 3609 lines checked , which
is caused by a different coding style in those files. These warnings and
errors are not addressed To let these files be easily synchronized between
binutils and qemu.
Signed-off-by: Marek
From: Chris Wulff <crwu...@gmail.com>
Add the Altera Nios2 internal interrupt controller model.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loos
Add the Altera 10M50 Nios2 GHRD model. This allows emulating the
10M50 development kit with the Nios2 GHRD loaded in the FPGA. It
is possible to boot Linux kernel and run userspace, thus far only
from initrd as storage support is not yet implemented.
Signed-off-by: Marek Vasut <ma...@denx.de&
From: Chris Wulff <crwu...@gmail.com>
Add support for emulating Altera NiosII R1 architecture into qemu.
This patch is based on previous work by Chris Wulff from 2012 and
updated to latest mainline QEMU.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.c
emulation
Marek Vasut (4):
nios2: Add disas entries
nios2: Add usermode binaries emulation
nios2: Add Altera 10M50 GHRD emulation
nios2: Add support for Nios-II R1
MAINTAINERS |8 +
arch_init.c |2 +
configure
Add remaining bits of the Altera NiosII R1 support into qemu, which
is documentation, MAINTAINERS file entry, configure bits, arch_init
and configuration files for both linux-user (userland binaries) and
softmmu (hardware emulation).
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris
On 01/16/2017 11:21 PM, Alexander Graf wrote:
>
>
> On 31/12/2016 14:22, Marek Vasut wrote:
>> From: Chris Wulff <crwu...@gmail.com>
>>
>> Add support for emulating Altera NiosII R1 architecture into qemu.
>> This patch is based on previous work by Chris W
On 01/16/2017 11:36 PM, Alexander Graf wrote:
>
>
> On 31/12/2016 14:22, Marek Vasut wrote:
>> From: Chris Wulff <crwu...@gmail.com>
>>
>> Add the Altera timer model.
>>
>> Signed-off-by: Marek Vasut <ma...@denx.de>
>> Cc: Chris Wulff <
On 12/31/2016 02:22 PM, Marek Vasut wrote:
> Add nios2 disassembler support. This patch is composed from binutils files
> from commit "Opcodes and assembler support for Nios II R2". The files from
> binutils used in this patch are:
>
> include/opcode/nios2.h
>
ios2-opc.c
opcodes/nios2-dis.c
Checkpatch says total: 114 errors, 0 warnings, 3609 lines checked , which
is caused by a different coding style in those files. These warnings and
errors are not addressed To let these files be easily synchronized between
binutils and qemu.
Signed-off-by: Marek
Add missing bits for qemu-user required for emulating Altera Nios2
userspace binaries.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loosemore <san...
From: Chris Wulff <crwu...@gmail.com>
Add support for emulating Altera NiosII R1 architecture into qemu.
This patch is based on previous work by Chris Wulff from 2012 and
updated to latest mainline QEMU.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.c
Add the Altera 10M50 Nios2 GHRD model. This allows emulating the
10M50 development kit with the Nios2 GHRD loaded in the FPGA. It
is possible to boot Linux kernel and run userspace, thus far only
from initrd as storage support is not yet implemented.
Signed-off-by: Marek Vasut <ma...@denx.de&
Add remaining bits of the Altera NiosII R1 support into qemu, which
is documentation, MAINTAINERS file entry, configure bits, arch_init
and configuration files for both linux-user (userland binaries) and
softmmu (hardware emulation).
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris
From: Chris Wulff <crwu...@gmail.com>
Add the Altera Nios2 internal interrupt controller model.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loos
From: Chris Wulff <crwu...@gmail.com>
Add the Altera timer model.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loosemore <san...@codesourcery.
On 11/13/2016 05:25 PM, Guenter Roeck wrote:
> On 11/13/2016 04:43 AM, Marek Vasut wrote:
>> On 11/13/2016 01:01 PM, Marek Vasut wrote:
>>> On 11/13/2016 12:25 AM, Guenter Roeck wrote:
>>>> Hi Marek,
>>>
>>> Hi!
>>>
>>>> On
On 11/13/2016 05:09 PM, Guenter Roeck wrote:
> Hi Marek,
>
> On 11/13/2016 04:01 AM, Marek Vasut wrote:
>>>
>>> diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c
>>> index 564dbae..e0a9aff 100644
>>> --- a/hw/nios2/boot.c
>>> +++ b/hw/nios2/bo
On 11/13/2016 01:01 PM, Marek Vasut wrote:
> On 11/13/2016 12:25 AM, Guenter Roeck wrote:
>> Hi Marek,
>
> Hi!
>
>> On 11/12/2016 01:50 PM, Marek Vasut wrote:
>>> On 11/07/2016 08:54 PM, Guenter Roeck wrote:
>>>> Hi Marek,
>>>>
>>&g
On 11/13/2016 12:25 AM, Guenter Roeck wrote:
> Hi Marek,
Hi!
> On 11/12/2016 01:50 PM, Marek Vasut wrote:
>> On 11/07/2016 08:54 PM, Guenter Roeck wrote:
>>> Hi Marek,
>>>
>>> On 11/07/2016 10:14 AM, Marek Vasut wrote:
>>>> On 11/07/2016 04:58
On 11/07/2016 08:54 PM, Guenter Roeck wrote:
> Hi Marek,
>
> On 11/07/2016 10:14 AM, Marek Vasut wrote:
>> On 11/07/2016 04:58 AM, Guenter Roeck wrote:
>>> On Tue, Oct 25, 2016 at 09:57:43PM +0200, Marek Vasut wrote:
>>>> From: Chris Wulff <crwu...@gmail.c
On 11/07/2016 04:58 AM, Guenter Roeck wrote:
> On Tue, Oct 25, 2016 at 09:57:43PM +0200, Marek Vasut wrote:
>> From: Chris Wulff <crwu...@gmail.com>
>>
>> Add support for emulating Altera NiosII R1 architecture into qemu.
>> This patch is based on previ
On 10/31/2016 10:27 PM, Romain Naour wrote:
> Hi Marek, all,
Hi,
> Le 18/10/2016 à 06:17, Marek Vasut a écrit :
>> On 10/15/2016 03:15 PM, Romain Naour wrote:
>>> Hi Marek,
>>
>> Hi!
>>
>>> Le 28/09/2016 à 01:30, Marek Vasut a écrit :
>>>
From: Chris Wulff <crwu...@gmail.com>
Add support for emulating Altera NiosII R1 architecture into qemu.
This patch is based on previous work by Chris Wulff from 2012 and
updated to latest mainline QEMU.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.c
On 10/23/2016 06:20 AM, Richard Henderson wrote:
> On 10/22/2016 08:01 PM, Marek Vasut wrote:
>>> For signed division, you have to protect against 0x8000 / -1 as
>>> well, which raises an overflow exception on the x86 host.
>>
>> You mean similar to what
On 10/20/2016 04:35 PM, Richard Henderson wrote:
> On 10/20/2016 06:44 AM, Marek Vasut wrote:
>> +typedef struct Nios2Instruction {
>> +void (*handler)(DisasContext *dc, uint32_t code, TCGMemOp
>> flags);
>> +uint32_t flags;
>> +} Nios2Instruction;
&g
From: Chris Wulff <crwu...@gmail.com>
Add support for emulating Altera NiosII R1 architecture into qemu.
This patch is based on previous work by Chris Wulff from 2012 and
updated to latest mainline QEMU.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.c
On 10/20/2016 07:05 AM, Richard Henderson wrote:
> On 10/19/2016 08:01 PM, Marek Vasut wrote:
>>> > You might like 0xfffc better, but that does require that you count
>>> > f's appropriately for the type. That's why I like -4: it's obvious
>>> (or
>>
On 10/19/2016 06:18 PM, Richard Henderson wrote:
> On 10/18/2016 07:31 PM, Marek Vasut wrote:
>>> Processing a little more data can be preferable to fewer branch
>>> prediction failures. And the best way to avoid those is to not have the
>>> branch at all.
On 10/19/2016 05:50 PM, Richard Henderson wrote:
> On 10/18/2016 08:23 PM, Marek Vasut wrote:
>>> The documentation appears less than clear about whether or not loads
>>> into r0 recognize exceptions from the load, as opposed to simply not
>>> modifying r0.
>&
On 10/19/2016 01:04 AM, Richard Henderson wrote:
> On 10/18/2016 02:50 PM, Marek Vasut wrote:
>> +/* Special R-Type instruction opcode */
>> +#define INSN_R_TYPE 0x3A
>> +
>> +/* I-Type instruction parsing */
>> +#define I_TYPE(instr, co
On 10/19/2016 03:24 AM, Richard Henderson wrote:
> On 10/18/2016 03:05 PM, Marek Vasut wrote:
>>>> Thanks, I hope this is fixed now, although I mostly special-case the
>>>> R_ZERO handling throughout the code. Any writes to R_ZERO are now
>>>> ignored
From: Chris Wulff <crwu...@gmail.com>
Add support for emulating Altera NiosII R1 architecture into qemu.
This patch is based on previous work by Chris Wulff from 2012 and
updated to latest mainline QEMU.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.c
On 10/18/2016 10:44 PM, Richard Henderson wrote:
> On 10/18/2016 11:32 AM, Marek Vasut wrote:
>> But the instruction encoding does, so I can use the field from the
>> instruction to directly index the register array.
>
> Well, no, you can't.
>
> In fact, it would
ios2-opc.c
opcodes/nios2-dis.c
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loosemore <san...@codesourcery.com>
Cc: Yves Vandervennet <yvand..
From: Chris Wulff <crwu...@gmail.com>
Add support for emulating Altera NiosII R1 architecture into qemu.
This patch is based on previous work by Chris Wulff from 2012 and
updated to latest mainline QEMU.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.c
Add the Altera 10M50 Nios2 GHRD model. This allows emulating the
10M50 development kit with the Nios2 GHRD loaded in the FPGA. It
is possible to boot Linux kernel and run userspace, thus far only
from initrd as storage support is not yet implemented.
Signed-off-by: Marek Vasut <ma...@denx.de&
Add missing bits for qemu-user required for emulating Altera Nios2
userspace binaries.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loosemore <san...
From: Chris Wulff <crwu...@gmail.com>
Add the Altera timer model.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loosemore <san...@codesourcery.
From: Chris Wulff <crwu...@gmail.com>
Add the Altera Nios2 internal interrupt controller model.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loos
Add remaining bits of the Altera NiosII R1 support into qemu, which
is documentation, MAINTAINERS file entry, configure bits, arch_init
and configuration files for both linux-user (userland binaries) and
softmmu (hardware emulation).
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris
On 10/18/2016 05:31 PM, Richard Henderson wrote:
> On 10/17/2016 08:58 PM, Marek Vasut wrote:
>>> There's no particular reason why R_PC needs to be 64; if you change it
>>> to 32, you can simplify this.
>>
>> I believe this is in fact needed, see [1] page 18 (se
On 10/15/2016 03:15 PM, Romain Naour wrote:
> Hi Marek,
Hi!
> Le 28/09/2016 à 01:30, Marek Vasut a écrit :
>> Add nios2 disassembler support. This patch is composed from binutils files
>> from commit "Opcodes and assembler support for Nios II R2". The files from
&g
gt; +return i_type_instructions[op].name;
>> +}
>> +}
>
> What is this function used for?
Nothing, removed.
>> +/* I-Type instruction */
>> +typedef struct Nios2IType {
>> +uint32_t op:6;
>> +uint32_t imm16:16;
>> +uint32_t b:5;
>> +uint32_t a:5;
>> +} QEMU_PACKED Nios2IType;
>
> These bitfields are a non-starter. Layout of them is non-portable in
> more ways than is worth going into here. You must use extract32 and
> sextract32 to extract the fields.
Fixed
>> +
>> +union i_type_u {
>> +uint32_t v;
>> +Nios2IType i;
>> +};
>> +
>> +#define I_TYPE(instr, op) \
>> +union i_type_u instr_u = { .v = op }; \
>> +Nios2IType *instr = _u.i
>
> You could probably still hide everything behind this macro, with an
> inline function returning a structure (defined *without* bitfields).
Yes, fixed.
>> +/*
>> + * Return values for instruction handlers
>> + */
>> +#define INSTR_UNIMPL -2 /* Unimplemented instruction */
>> +#define INSTR_ERR-1 /* Error in instruction */
>> +#define PC_INC_NORMAL 0 /* Normal PC increment after instruction */
>> +#define PC_INC_BY_INSTR 1 /* PC got incremented by instruction */
>> +#define INSTR_BREAK 2 /* Break encountered */
>> +#define INSTR_EXCEPTION 255 /* Instruction generated an exception
>> +(the exception cause will be stored
>> +in struct nios2 */
>
> What's the gain over using a simple enum with sequential values?
These are unused, so removed.
>> +/*
>> + * FIXME: Convert to VMstate
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/hw.h"
>> +#include "hw/boards.h"
>> +
>> +void cpu_save(QEMUFile *f, void *opaque)
>> +{
>> +/* TODO */
>> +}
>> +
>> +int cpu_load(QEMUFile *f, void *opaque, int version_id)
>> +{
>> +/* TODO */
>> +return 0;
>> +}
>
> Fixing this is no longer optional.
This file wasn't even compiled, so removed.
>> +void helper_memalign(CPUNios2State *env, uint32_t addr, uint32_t dr,
>> uint32_t wr, uint32_t mask)
>> +{
>> +if (addr & mask) {
>> +qemu_log("unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
>> + addr, mask, wr, dr);
>> +env->regs[CR_BADADDR] = addr;
>> +env->regs[CR_EXCEPTION] = EXCP_UNALIGN << 2;
>> +helper_raise_exception(env, EXCP_UNALIGN);
>> +}
>> +}
>
> What is this doing that cc->do_unaligned_access doesn't?
Switched to do_unaligned_access, thanks.
>> +/* Initialize DC */
>> +dc->cpu_env = cpu_env;
>> +dc->cpu_R = cpu_R;
>
> What is this assignment for? Are you planning to implement shadow
> registers at some point?
Eventually yes, but so far I haven't seen that used at all.
> r~
Thanks for the review!
--
Best regards,
Marek Vasut
ios2-opc.c
opcodes/nios2-dis.c
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chris Wulff <crwu...@gmail.com>
Cc: Jeff Da Silva <jdasi...@altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Sandra Loosemore <san...@codesourcery.com>
Cc: Yves Vandervennet <yvand
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