Dear Jan Kiszka,
We flush coalesced MMIO in the device models now, and VNC - for which
this was once introduced - is also fine without it as it has its own
refresh timer.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
vl.c | 13 -
1 files changed, 0 insertions(+), 13
Hello, myself Avinash Jain. I want to contribute to QEMU but i don't know
anything about it, I am new to this. Can any buddy please provide me an
initial step. I work on Ubuntu 10.10. Please provide me some demo tutorial
to start with Qemu on ubutnu.
--
thanx regards,
avinash
(+91) 9502681447
MinGW-w64 already defines lseek and ftruncate (and uses the 64 bit
variants). The conditional compilation avoids redefinitions
(which would be wrong) and compiler warnings.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
qemu-common.h |8 ++--
1 files changed, 6 insertions(+), 2
MinGW-w64 and some versions of MinGW32 don't provide libiberty.a,
so add this library only if it was found.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
configure |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/configure b/configure
index ca25250..bb16498
On it
On Fri, Mar 9, 2012 at 2:42 AM, Anthony Liguori anth...@codemonkey.ws wrote:
On 03/04/2012 10:39 PM, Peter A. G. Crosthwaite wrote:
Xilinx zynq-7000 machine model. Also includes device model for the
zynq-specific
system level control register (SLCR) module.
Signed-off-by: Peter A. G.
nvm,
youve got it covered. Thanks Anthony.
On Sat, Mar 10, 2012 at 8:15 PM, Peter Crosthwaite
peter.crosthwa...@petalogix.com wrote:
On it
On Fri, Mar 9, 2012 at 2:42 AM, Anthony Liguori anth...@codemonkey.ws wrote:
On 03/04/2012 10:39 PM, Peter A. G. Crosthwaite wrote:
Xilinx zynq-7000
On 2012-03-10 07:19, Marek Vasut wrote:
Dear Jan Kiszka,
We flush coalesced MMIO in the device models now, and VNC - for which
this was once introduced - is also fine without it as it has its own
refresh timer.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
vl.c | 13
Am 10.03.2012 11:14, schrieb Stefan Weil:
MinGW-w64 already defines lseek and ftruncate (and uses the 64 bit
variants). The conditional compilation avoids redefinitions
(which would be wrong) and compiler warnings.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
qemu-common.h |8
The topic of whether and by whom docs/tracing.txt is maintained was
brought up. It currently does not have an official maintainer.
Add it to the tracing section so that Stefan gets cc'ed on patches.
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Stefan Hajnoczi stefa...@linux.vnet.ibm.com
On Fri, Mar 09, 2012 at 09:04:03PM +, Daniel P. Berrange wrote:
On Fri, Mar 09, 2012 at 05:56:52PM -0300, Eduardo Habkost wrote:
Resurrecting an old thread:
I didn't see any clear conclusion in this thread (this is why I am
resurrecting it), except that many were arguing that libvirt
Am 08.02.2012 06:53, schrieb David Gibson:
For the pseries machine, TCE (IOMMU) tables can either be directly
malloc()ed in qemu or, when running on a KVM which supports it, mmap()ed
from a KVM ioctl. The latter option is used when available, because it
allows the (frequent bottlenext)
Am 28.02.2012 09:54, schrieb Paolo Bonzini:
Property removal modifies the list, so it is not safe to continue
iteration. We know anyway that each object can have only one
parent (see object_property_add_child), so exit after finding
the requested object.
Reported-by: Michael S. Tsirkin
Am 28.02.2012 09:54, schrieb Paolo Bonzini:
These were stored as NULL due to wrong cut-and-paste from set_pointer.
Reported-by: Gerhard Wiesinger li...@wiesinger.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
Reviewed-by: Andreas Färber afaer...@suse.de
/-F
---
On 9 March 2012 18:47, Andreas Färber afaer...@suse.de wrote:
Am 09.03.2012 18:11, schrieb Peter Maydell:
On 9 March 2012 14:28, Andreas Färber afaer...@suse.de wrote:
No, please. We're describing sizes, not addresses. target_phys_addr_t
thus is semantically wrong here. The RAM size is
Am 10.03.2012 14:51, schrieb Peter Maydell:
On 9 March 2012 18:47, Andreas Färber afaer...@suse.de wrote:
Am 09.03.2012 18:11, schrieb Peter Maydell:
On 9 March 2012 14:28, Andreas Färber afaer...@suse.de wrote:
No, please. We're describing sizes, not addresses. target_phys_addr_t
thus is
Am 09.03.2012 20:04, schrieb Alexander Graf:
On 09.03.2012, at 19:47, Andreas Färber wrote:
Am 09.03.2012 18:11, schrieb Peter Maydell:
On 9 March 2012 14:28, Andreas Färber afaer...@suse.de wrote:
No, please. We're describing sizes, not addresses. target_phys_addr_t
thus is semantically
On 10 March 2012 14:08, Andreas Färber afaer...@suse.de wrote:
Am 10.03.2012 14:51, schrieb Peter Maydell:
Length of a block of memory on the guest is what I meant.
What you need is an integer type large enough to hold the
difference between two guest pointer values. The size of
that type
On Sat, Mar 10, 2012 at 12:42:46PM +, Daniel P. Berrange wrote:
I could have sworn we had this discussion a year ago or so, and had decided
that the default CPU models would be in something like
/usr/share/qemu/cpu-x86_64.conf
and loaded regardless of the -nodefconfig setting.
Hi Avinash ,
These links contain enough information for you to get started :
http://wiki.qemu.org/Manual
https://help.ubuntu.com/community/Installation/QemuEmulator
--Jaspal
On Sat, Mar 10, 2012 at 1:24 PM, Avinash Jain jain.av...@gmail.com wrote:
Hello, myself Avinash Jain. I want to
Am 10.03.2012 13:11, schrieb Andreas Färber:
Am 10.03.2012 11:14, schrieb Stefan Weil:
MinGW-w64 already defines lseek and ftruncate (and uses the 64 bit
variants). The conditional compilation avoids redefinitions
(which would be wrong) and compiler warnings.
Signed-off-by: Stefan
Am 10.03.2012 11:14, schrieb Stefan Weil:
MinGW-w64 and some versions of MinGW32 don't provide libiberty.a,
so add this library only if it was found.
What do we need it for at all then?
Andreas
Signed-off-by: Stefan Weil s...@weilnetz.de
---
configure |8 +++-
1 files changed, 7
This is a little cleanup/consolidation for some iovec-related
low-level routines in qemu.
First patch consolidates qemu_iovec_memset_skip() and
qemu_iovec_memset(), which is just a little cleanup.
The rest renames arguments of iovec I/O functions to be
more understandable/obvious (see comments
This patch combines two functions into one, simplifies the
implementation and adds some assert()s into place.
Signed-off-by: Michael Tokarev m...@tls.msk.ru
---
block/qcow2.c |4 +-
block/qed.c|4 +-
cutils.c | 54
Rename arguments and use size_t for sizes instead of int
-qemu_sendv(int sockfd, struct iovec *iov, int len, int iov_offset)
+qemu_sendv(int sockfd, struct iovec *iov, size_t bytes, size_t offset)
The main motivation was to make it clear that length and offset are
in _bytes_, not in iov
The same as for non-coroutine versions in previous patches:
rename arguments to be more obvious, change type of arguments
from int to size_t where appropriate, and use common code for
send and receive paths (with one extra argument) since these
are exactly the same. Use common qemu_sendv_recvv()
Make it much more understandable, and add comments to it.
This is in order to prepare similar function for writev_readv().
The new implementation has been extensively tested by
splitting a large buffer into many small randomly-sized
chunks, sending it over socket to another, slow process
and
Rename do_sendv_recvv() to qemu_sendv_recvv(),
change its last arg (do_send) from int to bool,
export it in qemu-common.h, and made the two
callers of it (qemu_sendv() and qemu_recvv())
to be trivial #defines just adding 5th arg.
qemu_sendv_recvv() will be used later.
Signed-off-by: Michael
The encryption is speed-optimized AES256. The compression is proprietary, as is
common for backup image files, however in hindsight I agree with you. I too
would prefer for it to all be open. It's possible we maybe able to make such a
shift. Thanks for your thoughts and suggestions.
Sent from
This function allows to obtain a singly-linked list of classes, which
can be sorted by the caller.
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Anthony Liguori anth...@codemonkey.ws
---
include/qemu/object.h | 11 +++
qom/object.c | 17 +
2 files
The internal CPU feature flags were only ever set in
cpu_reset_model_id(). Therefore move their initialization into
ARMCPUClass. We might want to tweak them in the future though (e.g.,
-cpu cortex-r4,+fpu), so keep a copy in ARMCPU. This in turn means we
need to infer features for both ARMCPUClass
If storagecraft disappears the customers still have the existing tools, which
can, for instance, convert their backup images to vhd or VMDK, so I think this
is probably not an issue.
Sent from a phone
On Mar 9, 2012, at 3:28 AM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 09/03/2012 10:23,
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu-qom.h |1 +
target-arm/cpu.c | 11 +++
target-arm/helper.c | 29 -
3 files changed, 12 insertions(+), 29 deletions(-)
diff --git
We g_malloc0()'ed CPUARMState ourself, and exec.c's cpu_copy() runs
through cpu_init() as well, so we are at liberty to supply the CPUState
any way we see fit. Having CPUARMState as field in the QOM CPU allows
both to access env from an ARMCPU object and to access the QOM Object
and its
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu-qom.h |1 +
target-arm/cpu.c |6 ++
target-arm/helper.c |3 ---
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu-qom.h
Move last remaining TI925T bits to ti925t_reset().
This reduces cpu_state_reset() to triviality and lets us reset the CPU
directly from arm_cpu_initfn().
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c|4
Only one CPU is created on this board, so we can use /cpu.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/integratorcp.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index 9bdb9e6..ac3fd7e 100644
--- a/hw/integratorcp.c
Having moved the reset code for some CPUs to class_init, we can drop
some of the cases in the switch.
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.h|2 --
target-arm/helper.c |5 -
2 files changed, 0 insertions(+), 7
No other emulated CPU uses this at this time.
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
Cc: Andrzej Zaborowski balr...@gmail.com
---
target-arm/cpu.c| 14 ++
target-arm/cpu.h|6 --
target-arm/helper.c |8
I'm believe your patch set provides these behaviors now:
* QEMU block drivers report discard_granularity.
* discard_granularity = 0 means no discard
* The guest is told there's no discard support.
* discard_granularity 0 is undefined.
The OMAPCP feature allows to switch between TI915T and TI925T via
cp15 c15_ticonfig register. Move reset into ti925t-specific callback.
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c| 18 ++
target-arm/helper.c
Create a CPU subclass, and register classes matching all CPU models
except for pxa270, which is an alias for pxa270-a0.
Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,
except for special value any.
Replace cpu_arm_find_by_name()'s string - CPUID lookup by storing the
CPUID in
None of the machines in QEMU offer a JTAG debug interface, so this info
was unused. Further, the PXA250 ID contradicts the February 2002
Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision.
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell
On 03/10/2012 09:58 AM, Eduardo Habkost wrote:
On Sat, Mar 10, 2012 at 12:42:46PM +, Daniel P. Berrange wrote:
I could have sworn we had this discussion a year ago or so, and had decided
that the default CPU models would be in something like
/usr/share/qemu/cpu-x86_64.conf
and loaded
Allow to inspect and manipulate MIDR variant and revision fields.
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c | 48
1 files changed, 48 insertions(+), 0 deletions(-)
diff --git
Instead of having classes per CPUID value, keep just one pxa270 class
and use pxa270-a1 etc. as aliases that override default CPU properties.
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Paul Brook p...@codesourcery.com
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c|
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu-qom.h |3 +++
target-arm/cpu.c | 11 +++
target-arm/cpu.h |1 -
target-arm/helper.c | 12
4 files changed, 14 insertions(+), 13 deletions(-)
diff
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu-qom.h |1 +
target-arm/cpu.c | 18 ++
target-arm/helper.c | 12
3 files changed, 19 insertions(+), 12 deletions(-)
diff --git
Am 10.03.2012 19:24, schrieb Anthony Liguori:
Humans probably do one of two things: 1) no cpu option or 2) -cpu host.
So then why are you introducing -cpu Westmere?
[...]
P.S. I spent 30 minutes the other day helping a user who was attempting
to figure out whether his processor was a Conroe,
For now set them in the reset function.
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu-qom.h |2 +
target-arm/cpu.c | 63 ++
target-arm/helper.c | 51
This allows to share initialization between CPU models.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-arm/cpu.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 00b7ecc..1e34cba 100644
--- a/target-arm/cpu.c
+++
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu-qom.h |1 +
target-arm/cpu.c | 19 +++
target-arm/cpu.h |3 ---
target-arm/helper.c | 17 -
4 files changed, 20 insertions(+), 20
Hello,
Since the ARM target lately has been the target with the highest rate of
changes,
let's convert it first, as a proof of concept. Especially its reset handler can
be greatly simplified through QOM.
Patch 1 is a RESEND of object_class_get_list() v2. Needed for virtually every
target.
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu-qom.h |1 +
target-arm/cpu.c | 17 +
target-arm/helper.c | 14 --
3 files changed, 18 insertions(+), 14 deletions(-)
diff --git
Am 10.03.2012 17:28, schrieb Andreas Färber:
Am 10.03.2012 11:14, schrieb Stefan Weil:
MinGW-w64 and some versions of MinGW32 don't provide libiberty.a,
so add this library only if it was found.
What do we need it for at all then?
Andreas
Signed-off-by: Stefan Weil s...@weilnetz.de
---
tcg_out_label is always called with a third argument of pointer type
which was casted to tcg_target_long.
These casts can be avoided by changing the prototype of tcg_out_label.
There was also a cast to long. For most hosts with
sizeof(long) == sizeof(tcg_target_long) == sizeof(void *) this did
Am 05.02.2012 21:19, schrieb Stefan Weil:
Most MemoryRegionOps already had the const attribute.
This patch adds it to the remaining ones.
Signed-off-by: Stefan Weils...@weilnetz.de
---
hw/cuda.c |2 +-
hw/ide/ahci.c |4 ++--
hw/ide/cmd646.c|6 +++---
On Fri, Mar 09, 2012 at 07:51:06PM +1300, Alexey Korolev wrote:
In this patch we introduce the pri_region_entry structure and
significantly simplify the pci_bus structure.
Instead of arrays now we are using linked lists to account resources and
assign memory bases.
Since we modify the
Am 25.02.2012 14:50, schrieb Stefan Weil:
Without the break statement, case 5 sets month and year from the same
data. This does not look correct.
The missing break was reported by splint.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
hw/ds1338.c | 1 +
1 files changed, 1 insertions(+), 0
Casting a pointer to an integer value must use uintptr_t or intptr_t
(not long) for portable code. MinGW-w64 requires this because
sizeof(long) != sizeof(void *) for w64 hosts, so casting to long
raises a compiler warning.
I use uintptr_t instead of intptr_t because changing the sign does not
Am 25.02.2012 14:50, schrieb Stefan Weil:
Without the break statement, case 5 sets month and year from the same
data. This does not look correct.
The missing break was reported by splint.
Signed-off-by: Stefan Weil s...@weilnetz.de
Assigning data to both month and year certainly makes no
*Newsflash*
We do have a well-behaving KVM Host with 3.2.9 kernel on machine C
After again numerous attempts to find the culprit, I decided to copy the
kernel 2.6.35 and modules from machine A to machine C, where it
exhibited also the desired well-behaving.
I then simply copied its config to a
On 08.03.2012, at 02:12, David Gibson wrote:
Currently, the function spapr_create_phb() uses its parameters to
initialize the correct memory windows for the new PCI Host Bridge
(PHB). This is not the way things are supposed to be done with qdevs,
and means you can't create extra PHBs easily
On 08.03.2012, at 02:12, David Gibson wrote:
The pseries xics interrupt controller, like most interrupt
controllers can support both message (i.e. edge sensitive) interrupts
and level sensitive interrupts, but it needs to know which are which.
When I implemented the xics emulation for
Rename do_sendv_recvv() to qemu_sendv_recvv(),
change its last arg (do_send) from int to bool,
export it in qemu-common.h, and made the two
callers of it (qemu_sendv() and qemu_recvv())
to be trivial #defines just adding 5th arg.
qemu_sendv_recvv() will be used later.
Signed-off-by: Michael
This patch combines two functions into one, simplifies the
implementation and adds some assert()s into place.
The new prototype of qemu_iovec_memset():
void qemu_iovec_memset(qiov, size_t offset, int c, size_t bytes)
It is different from former qemu_iovec_memset_skip(), and
I want to make other
Make it much more understandable, and add comments to it.
This is in order to prepare similar function for writev_readv().
The new implementation has been extensively tested by
splitting a large buffer into many small randomly-sized
chunks, sending it over socket to another, slow process
and
Similar to
qemu_iovec_memset(QEMUIOVector *qiov, size_t offset, int c, size_t bytes);
the new prototype is:
qemu_iovec_from_buffer(QEMUIOVector *qiov, size_t offset, const void *buf,
size_t bytes);
The processing starts at offset bytes within qiov.
This way, we may copy a bounce buffer
This is a little cleanup/consolidation for some iovec-related
low-level routines in qemu.
The plan is to make library functions more understandable,
consistent and useful.
The patch changes prototypes of several iov and qiov functions
to match each other, changes types of arguments for some
Rename arguments and use size_t for sizes instead of int
-qemu_sendv(int sockfd, struct iovec *iov, int len, int iov_offset)
+qemu_sendv(int sockfd, struct iovec *iov, size_t offset, size_t bytes)
The main motivation was to make it clear that length and offset are
in _bytes_, not in iov
The same as for non-coroutine versions in previous patches:
rename arguments to be more obvious, change type of arguments
from int to size_t where appropriate, and use common code for
send and receive paths (with one extra argument) since these
are exactly the same. Use common qemu_sendv_recvv()
qemu_iovec_concat() is currently a wrapper for qemu_iovec_copy(),
use the former (with extra 0 arg) in a few places where it is used.
Change skip argument of qemu_iovec_copy() from uint64_t to size_t,
since size of qiov itself is size_t, so there's no way to skip larger
sizes. Rename it to
On Fri, 2012-03-09 at 21:58 +1100, David Gibson wrote:
What about virtio?
virtio doesn't use virtualized PCI DMA, it uses direct hypervisor
access to guest memory, by guest physical address. It *shouldn't*,
but it does - that's the way it's specced and that's the way the guest
kernel
On 11.03.2012 05:49, Michael Tokarev wrote:
This is a little cleanup/consolidation for some iovec-related
low-level routines in qemu.
The plan is to make library functions more understandable,
consistent and useful.
The patch changes prototypes of several iov and qiov functions
to match
ISA bus only use IRQ 0~15, so don't need to give an array qemu_irq 0~24, just
array qemu_irq i8259 is ok.
Signed-off-by: Wanpeng Li l...@linux.vnet.ibm.com
---
hw/pc_piix.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index
ISA bus only use IRQ 0~15, so don't need to give an array qemu_irq 0~23, just
array qemu_irq i8259 is ok.
Signed-off-by: Wanpeng Li l...@linux.vnet.ibm.com
---
hw/pc_piix.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index
On 2012-03-11 08:04, Wanpeng Li wrote:
ISA bus only use IRQ 0~15, so don't need to give an array qemu_irq 0~23, just
array qemu_irq i8259 is ok.
Signed-off-by: Wanpeng Li l...@linux.vnet.ibm.com
---
hw/pc_piix.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git
76 matches
Mail list logo
