regarding
missing braces which are actually there. I suspect it is
because of a comment.
checkpatch also complains about the labeled statements in
the switch, which I think are in fact good for readability.
Claudio Fontana (4):
include/elf.h: add aarch64 ELF machine and relocs
tcg/aarch64
we will use the 26bit relative relocs in the aarch64 tcg target.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
include/elf.h | 129 ++
1 file changed, 129 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index
support compiling on aarch64.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
configure | 8
1 file changed, 8 insertions(+)
diff --git a/configure b/configure
index 9439f1c..9cc398c 100755
--- a/configure
+++ b/configure
@@ -384,6 +384,8 @@ elif check_define __s390__
add SUBS to the arithmetic instructions and add a shift parameter to
all arithmetic instructions, so we can make use of shifted registers.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
tcg/aarch64/tcg-target.c | 36 +++-
1 file changed, 27
add preliminary support for TCG target aarch64.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
include/exec/exec-all.h |5 +-
tcg/aarch64/tcg-target.c | 1185 ++
tcg/aarch64/tcg-target.h | 99
translate-all.c |2
On 23.05.2013 15:03, Peter Maydell wrote:
On 23 May 2013 13:53, Andreas Färber afaer...@suse.de wrote:
Am 23.05.2013 14:50, schrieb Peter Maydell:
I'm happy for us to wait until an actual big-endian system
running Linux appears before we worry about it.
I was worried about Big Endian QEMU
On 23.05.2013 18:39, Peter Maydell wrote:
On 23 May 2013 09:18, Claudio Fontana claudio.font...@huawei.com wrote:
add preliminary support for TCG target aarch64.
Richard's handling the technical bits of the review, so
just some minor style nits here.
I tested this on the foundation model
On 23.05.2013 18:29, Richard Henderson wrote:
On 05/23/2013 01:18 AM, Claudio Fontana wrote:
+static inline void patch_reloc(uint8_t *code_ptr, int type,
+ tcg_target_long value, tcg_target_long
addend)
+{
+switch (type) {
+case R_AARCH64_JUMP26
(removing Paolo from CC as agreed with him)
On 24.05.2013 10:51, Claudio Fontana wrote:
On 23.05.2013 18:39, Peter Maydell wrote:
On 23 May 2013 09:18, Claudio Fontana claudio.font...@huawei.com wrote:
add preliminary support for TCG target aarch64.
Richard's handling the technical bits
Hello,
On 27.05.2013 11:47, Laurent Desnogues wrote:
Hi,
basically pointing out what I pointed for v1.
On Thu, May 23, 2013 at 10:18 AM, Claudio Fontana
claudio.font...@huawei.com wrote:
add preliminary support for TCG target aarch64.
Signed-off-by: Claudio Fontana claudio.font
On 24.05.2013 19:02, Richard Henderson wrote:
On 05/24/2013 01:53 AM, Claudio Fontana wrote:
No real need to special case zero; it's just an extra test slowing down the
compiler.
Yes, we need to handle the special case zero.
Otherwise no instruction at all would be emitted for value 0
On 27.05.2013 20:47, Richard Henderson wrote:
On 2013-05-27 04:43, Claudio Fontana wrote:
Hmm, true. Although I'd been thinking more along the lines of
arranging the code such that we'd use movz to set the zero.
I think we need to keep treating zero specially if we want to keep
On 27.05.2013 23:14, Laurent Desnogues wrote:
On Monday, May 27, 2013, Richard Henderson r...@twiddle.net
mailto:r...@twiddle.net wrote:
On 2013-05-27 04:43, Claudio Fontana wrote:
Hmm, true. Although I'd been thinking more along the lines of
arranging the code such that we'd use movz
for aarch64
+ *
+ * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH
+ * Written by Claudio Fontana
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version.
+ *
+ * See the COPYING file in the top-level directory for details
the cracks in v2
Claudio Fontana (3):
include/elf.h: add aarch64 ELF machine and relocs
tcg/aarch64: implement new TCG target for aarch64
configure: permit compilation on arm aarch64
configure|8 +
include/elf.h| 129 ++
include/exec/exec-all.h |5 +-
tcg
we will use the 26bit relative relocs in the aarch64 tcg target.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
include/elf.h | 129 ++
1 file changed, 129 insertions
support compiling on aarch64.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
configure | 8
1 file changed, 8 insertions(+)
diff --git a/configure b/configure
index eb74510..f021bdd 100755
--- a/configure
+++ b
add preliminary support for TCG target aarch64.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
include/exec/exec-all.h |5 +-
tcg/aarch64/tcg-target.c | 1159 ++
tcg/aarch64/tcg-target.h | 99
translate-all.c |2
On 28.05.2013 18:18, Richard Henderson wrote:
On 05/28/2013 08:28 AM, Claudio Fontana wrote:
+static inline void tcg_out_movi_aux(TCGContext *s,
+TCGReg rd, uint64_t value)
+{
+uint32_t half, base, movk = 0, shift = 0;
+
+/* construct halfwords
the cracks in v2
Changes in v4:
* made move immediate implementation more concise
* added comments explaining how the move immediate works
* reserve the frame pointer register (FP)
Claudio Fontana (3):
include/elf.h: add aarch64 ELF machine and relocs
tcg/aarch64: implement new TCG target
we will use the 26bit relative relocs in the aarch64 tcg target.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
include/elf.h | 129 ++
1 file changed, 129 insertions
add preliminary support for TCG target aarch64.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
include/exec/exec-all.h |5 +-
tcg/aarch64/tcg-target.c | 1161 ++
tcg/aarch64/tcg-target.h | 99
translate-all.c |2
support compiling on aarch64.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
configure | 8
1 file changed, 8 insertions(+)
diff --git a/configure b/configure
index eb74510..f021bdd 100755
--- a/configure
+++ b
On 31.05.2013 21:07, Richard Henderson wrote:
On 05/31/2013 10:57 AM, Jani Kokkonen wrote:
+ARITH_SUBS = 0x6b,
Any reason you're adding SUBS here, but not ANDS?
I also forgot ANDS, I'll add them and reorder.
+/* encode a logical immediate, mapping user parameter
+ M=set bits pattern
On 31.05.2013 21:13, Richard Henderson wrote:
On 05/31/2013 11:05 AM, Jani Kokkonen wrote:
+static inline void tcg_out_uxt(TCGContext *s, int s_bits,
+ TCGReg rd, TCGReg rn)
+{
+/* using ALIASes UXTB 0x53001c00, UXTH 0x53003c00
+ of UBFM Wd, Wn, #0,
On 31.05.2013 21:11, Richard Henderson wrote:
On 05/31/2013 11:01 AM, Jani Kokkonen wrote:
+static inline void tcg_out_rev(TCGContext *s, int ext, TCGReg rd, TCGReg rm)
+{
+/* using REV 0x5ac00800 */
+unsigned int base = ext ? 0xdac00c00 : 0x5ac00800;
+tcg_out32(s, base | rm 5 |
into 2 patches
* for byte swapping, remove REV32, we can just use REV
* fix broken comment in tcg_out_uxt
Claudio Fontana (4):
tcg/aarch64: improve arith shifted regs operations
tcg/aarch64: implement AND/TEST immediate pattern
tcg/aarch64: implement byte swap operations
tcg/aarch64
for arith operations, add SUBS, ANDS, ADDS and add a shift parameter
so that all arith instructions can make use of shifted registers.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
tcg/aarch64/tcg-target.c | 46 +-
1 file changed, 29
implement the optional byte swap operations with the dedicated
aarch64 instructions.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
tcg/aarch64/tcg-target.c | 32
tcg/aarch64/tcg-target.h | 10 +-
2 files changed, 37 insertions(+), 5
add functions to AND/TEST registers with immediate patterns.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
tcg/aarch64/tcg-target.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index
implement the optional sign/zero extend operations with the dedicated
aarch64 instructions.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
tcg/aarch64/tcg-target.c | 58 ++--
tcg/aarch64/tcg-target.h | 20 -
2 files
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index be02724..f4836f7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -745,6 +745,12 @@ M: qemu-devel@nongnu.org
S: Maintained
F: tcg
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index be02724..f4836f7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -745,6 +745,12 @@ M: qemu-devel@nongnu.org
S: Maintained
F: tcg
On 03.06.2013 16:57, Peter Maydell wrote:
On 3 June 2013 15:23, Richard Henderson r...@twiddle.net wrote:
On 06/02/2013 10:15 AM, Peter Maydell wrote:
So for a new architecture how do we determine whether we need
to fiddle with the start address or not? (More specifically,
is aarch64 going to
On 04.06.2013 18:13, Peter Maydell wrote:
On 4 June 2013 16:55, Claudio Fontana claudio.font...@huawei.com wrote:
I'm trying to get this to run, in order to be able to test the
aarch64 TCG User mode support I have under development.
Does it work as a first pass with aarch64 put
);
+}
+#endif
break;
#if defined(TARGET_NR_getdents64) defined(__NR_getdents64)
case TARGET_NR_getdents64:
--
Claudio Fontana
Server OS Architect
Huawei Technologies Duesseldorf GmbH
Riesstraße 25 - 80992 München
office: +49 89 158834 4135
mobile: +49 15253060158
(-)
Tested on aarch64 with Foundation v8.
Tested-by: Claudio Fontana claudio.font...@huawei.com
Tested-by: Claudio Fontana claudio.font...@huawei.com
guest binaries: x86-64 small binary, PPC 'ls' binary from debian
Claudio Fontana (2):
user-exec.c: aarch64 initial implementation of cpu_signal_handler
tcg/aarch64: implement user mode qemu ld/st
configure| 2 +-
tcg/aarch64/tcg-target.c | 121
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
user-exec.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/user-exec.c b/user-exec.c
index 71bd6c5..fa7f1f1 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -448,6 +448,21 @@ int cpu_signal_handler(int host_signum
From: Jani Kokkonen jani.kokko...@huawei.com
also put aarch64 in the list of archs that do not need an ldscript.
Signed-off-by: Jani Kokkoken jani.kokko...@huawei.com
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
configure| 2 +-
tcg/aarch64/tcg-target.c | 121
Hello all,
On 30.05.2013 13:07, Peter Maydell wrote:
On 29 May 2013 10:04, Claudio Fontana claudio.font...@huawei.com wrote:
This series implements preliminary support for the ARM aarch64 TCG target.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Cc'd some people who might like
and positive, and the scaled value must be
representable with 12bits.
This patch requires multiple reviewed but not committed yet series
reachable from:
https://lists.gnu.org/archive/html/qemu-devel/2013-06/msg00880.html
AArch64 TCG target implementation, git repo
Claudio Fontana (1):
tcg/aarch64
implement the 12bit scaled unsigned immediate offset
variant of LDR/STR. This improves code size by avoiding
the movi + ldst_r for naturally aligned offsets in range.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
tcg/aarch64/tcg-target.c | 32 +---
1
Hello
Richard,
A minimal update to use the new helpers with the return address argument.
Cc: Claudio Fontana address@hidden
Signed-off-by: Richard Henderson address@hidden
---
include/exec/exec-all.h | 18 --
tcg/aarch64/tcg-target.c | 28
2
On 10/05/13 09:37, Richard Henderson wrote:
On 10/04/2013 02:15 PM, Claudio Fontana wrote:
At first glance I think we should add X4 to the list of restrictions in
function `target_parse_constraint':
No, we've consumed all of the inputs at this point. We only
need list those registers
--
Claudio Fontana
Server OS Architect
Huawei Technologies Duesseldorf GmbH
Hi Peter,
On 05.09.2013 10:59, Peter Maydell wrote:
On 5 September 2013 09:31, Claudio Fontana claudio.font...@huawei.com wrote:
I just finished bisecting a regression I am experiencing on ARM 32bit target,
After a painful bisection, I got a first bad commit, which when reverted
(or not) the added code complexity.
But using the INSN_* you introduced instead of inline numbers is of course fine
for me.
Claudio
--
Claudio Fontana
Server OS Architect
Huawei Technologies Duesseldorf GmbH
On 05.09.2013 17:41, Richard Henderson wrote:
On 09/05/2013 06:32 AM, Claudio Fontana wrote:
{
-uint32_t half, base, shift, movk = 0;
-/* construct halfwords of the immediate with MOVZ/MOVK with LSL */
-/* using MOVZ 0x5280 | extended reg.. */
-base = (value 0x
Hello Richard,
On 02.09.2013 19:54, Richard Henderson wrote:
I'm not sure if I posted v2 or not, but my branch is named -3,
therefore this is v3. ;-)
The jumbo fixme patch from v1 has been split up. This has been
updated for the changes in the tlb helpers over the past few weeks.
For the
On 09.09.2013 16:08, Richard Henderson wrote:
On 09/09/2013 01:13 AM, Claudio Fontana wrote:
after carefully reading and testing your patches, this is how I suggest to
proceed:
first do the implementation of the new functionality (tcg opcodes, jit) in a
way that is consistent
On 02.09.2013 19:54, Richard Henderson wrote:
Also tidy the implementation of setcond in order to share code.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/aarch64/tcg-target.c | 33 +
tcg/aarch64/tcg-target.h | 4 ++--
2 files changed, 27
On 09.09.2013 17:07, Richard Henderson wrote:
On 09/09/2013 08:02 AM, Claudio Fontana wrote:
On 09.09.2013 16:08, Richard Henderson wrote:
On 09/09/2013 01:13 AM, Claudio Fontana wrote:
after carefully reading and testing your patches, this is how I suggest to
proceed:
first do
memory model.
Claudio Fontana (4):
configure: add c++ compiler support
rules.mak: support C++ compiling and linking
disas: add libvixl source code for aarch64
disas: implement host disassembly output for aarch64
configure| 21 +
disas.c
and CXXFLAGS in the default way.
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
---
configure | 15 +++
1 file changed, 15 insertions(+)
diff --git a/configure b/configure
index 0a55c20..6b73d99 100755
--- a/configure
+++ b/configure
@@ -252,6 +252,8 @@ for opt do
support compilation of .cc and .cpp files,
and if C++ is enabled always link with C++ in the non-libtool case.
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
---
rules.mak | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/rules.mak b
use C++ libvixl to implement output, for now only enabled for the host output
disasm, since we don't have the aarch64 target yet.
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
---
configure | 6 +
disas.c | 2 ++
disas/Makefile.objs
On 10.09.2013 10:45, Peter Maydell wrote:
On 10 September 2013 09:27, Claudio Fontana claudio.font...@huawei.com
wrote:
On another side, I end up having to manually revert some parts
of these which you put as prerequisites, during bisection when
landing after them, which is a huge time drain
On 10.09.2013 15:16, Richard Henderson wrote:
On 09/10/2013 01:27 AM, Claudio Fontana wrote:
There are two aspects.
On one side, although some changes do not break anything, I see some
problems in them.
Then let us discuss them, sooner rather than later.
Putting them as a prerequisite
On 02.09.2013 19:54, Richard Henderson wrote:
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/aarch64/tcg-target.c | 28 +++-
1 file changed, 7 insertions(+), 21 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index
On 02.09.2013 19:54, Richard Henderson wrote:
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/aarch64/tcg-target.c | 44 ++--
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
:
+case INDEX_op_movi_i64:
+case INDEX_op_movi_i32:
+/* Always implemented with tcg_out_mov/i, never with tcg_out_op. */
default:
-tcg_abort(); /* opcode not implemented */
+/* Opcode not implemented. */
+tcg_abort();
}
}
Ok
--
Claudio
On 12.09.2013 10:58, Peter Maydell wrote:
On 12 September 2013 09:25, Claudio Fontana claudio.font...@huawei.com
wrote:
On 02.09.2013 19:54, Richard Henderson wrote:
-case INDEX_op_bswap64_i64:
-ext = 1; /* fall through */
case INDEX_op_bswap32_i64:
+/* Despite
On 12.09.2013 16:02, Richard Henderson wrote:
On 09/12/2013 01:30 AM, Claudio Fontana wrote:
+case INDEX_op_mov_i64:
+case INDEX_op_mov_i32:
+case INDEX_op_movi_i64:
+case INDEX_op_movi_i32:
+/* Always implemented with tcg_out_mov/i, never with tcg_out_op
Hello Richard,
On 14.09.2013 23:54, Richard Henderson wrote:
This reduces the code size of the function significantly.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/aarch64/tcg-target.c | 95
+---
1 file changed, 50 insertions(+),
On 14.09.2013 23:54, Richard Henderson wrote:
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/aarch64/tcg-target.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 983a74a..8f19b50
On 14.09.2013 23:54, Richard Henderson wrote:
And since we're no longer talking about opcodes, merge the 0x1ac02000
data2 primary opcode with the shift subcode to create the full insn.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/aarch64/tcg-target.c | 49
INDEX_op_setcond_i64:
case INDEX_op_setcond_i32:
-tcg_out_cmp(s, ext, a1, a2, 0);
+tcg_out_cmp(s, ext, a1, a2);
tcg_out_cset(s, 0, a0, args[3]);
break;
agreed. This is an artifact from a previous implementation of the tlb lookup.
Reviewed-by: Claudio Fontana
On 14.09.2013 23:54, Richard Henderson wrote:
Now that we've converted opcode fields to pre-shifted insns, we
can merge the implementation of arithmetic and shift insns.
Simplify the left/right shift parameter to just the left shift
needed by tcg_out_tlb_read.
Signed-off-by: Richard
On 14.09.2013 23:54, Richard Henderson wrote:
This merges the implementation of tcg_out_addi and tcg_out_subi.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/aarch64/tcg-target.c | 79
+++-
1 file changed, 31 insertions(+), 48
On 14.09.2013 23:54, Richard Henderson wrote:
Avoid the magic numbers in the current implementation.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/aarch64/tcg-target.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git
On 14.09.2013 23:54, Richard Henderson wrote:
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/aarch64/tcg-target.c | 103
---
1 file changed, 80 insertions(+), 23 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c
*/
-if ((1ULL CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) {
-tcg_abort();
-}
-#endif
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0x);
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0x);
Reviewed-by: Claudio Fontana
On 14.09.2013 23:54, Richard Henderson wrote:
When profitable, initialize the register with MOVN instead of MOVZ,
before setting the remaining lanes with MOVK.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/aarch64/tcg-target.c | 88
Hallo Andreas,
On 16.09.2013 08:53, Andreas Färber wrote:
Am 11.09.2013 15:08, schrieb Claudio Fontana:
use C++ libvixl to implement output, for now only enabled for the host output
disasm, since we don't have the aarch64 target yet.
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
On 16.09.2013 17:50, Richard Henderson wrote:
On 09/16/2013 02:16 AM, Claudio Fontana wrote:
I agree in general with the approach lets see if it is more convenient to
start with MOVN.
The existing implementation is, although not easy, leaner.
Can we make it a little this one a little bit
On 16.09.2013 18:20, Richard Henderson wrote:
On 09/16/2013 12:42 AM, Claudio Fontana wrote:
+/* Hoist the loads of the most common arguments. */
+TCGArg a0 = args[0];
+TCGArg a1 = args[1];
+TCGArg a2 = args[2];
+int c2 = const_args[2];
+
Either all or none (add c0, c1
On 16.09.2013 17:07, Richard Henderson wrote:
On 09/16/2013 12:45 AM, Claudio Fontana wrote:
default:
-tcg_abort(); /* opcode not implemented */
+/* Opcode not implemented. */
+tcg_abort();
}
}
This change above seems unnecessary.
Perhaps qemu doesn't
On 16.09.2013 17:32, Richard Henderson wrote:
On 09/16/2013 01:41 AM, Claudio Fontana wrote:
On 14.09.2013 23:54, Richard Henderson wrote:
Now that we've converted opcode fields to pre-shifted insns, we
can merge the implementation of arithmetic and shift insns.
Simplify the left/right shift
On 16.09.2013 17:45, Richard Henderson wrote:
On 09/16/2013 02:02 AM, Claudio Fontana wrote:
-static inline void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg rn,
- TCGReg rm)
+static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg
On 16.09.2013 17:06, Richard Henderson wrote:
On 09/16/2013 12:56 AM, Claudio Fontana wrote:
case INDEX_op_shl_i64:
case INDEX_op_shl_i32:
-if (c2) {/* LSL / UBFM Wd, Wn, (32 - m) */
+if (c2) {
tcg_out_shl(s, ext, a0, a1, a2);
-} else
On 17.09.2013 16:27, Richard Henderson wrote:
On 09/17/2013 01:01 AM, Claudio Fontana wrote:
I don't have anything against it in principle, but just adding c0 and c1,
which iirc should cover all uses, would be fine by me.
Not really.
There are 6 potential args[] values, 5 of which might
On 17.09.2013 16:54, Richard Henderson wrote:
On 09/17/2013 01:23 AM, Claudio Fontana wrote:
It would have been handy if ARM had officially assigned identifiers to the
formats, like Power, S390, and ia64 do. Then one can build in the format
ids
into both the function and enumeration names
On 17.09.2013 16:27, Richard Henderson wrote:
On 09/17/2013 01:01 AM, Claudio Fontana wrote:
I don't have anything against it in principle, but just adding c0 and c1,
which iirc should cover all uses, would be fine by me.
Not really.
There are 6 potential args[] values, 5 of which might
On 18.09.2013 16:54, Richard Henderson wrote:
On 09/18/2013 01:24 AM, Claudio Fontana wrote:
If you _really_ want to strip the right shift functionality away for some
reason, could you state it?
(1) It will never never ever be used.
(2) I do not find + for LSR, - for LSL intuitive at all
Hi Alex,
On 09/27/13 02:48, Alexander Graf wrote:
This adds handling for the b and bl instructions.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 61
++
1 file changed, 61 insertions(+)
diff --git
is better even for AArch64, since objdump
will see more use and be more tested.
I don't have anywhere to test until September, but I generally
Acked-by: Claudio Fontana claudio.font...@huawei.com
provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) C3
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
---
The following patch has been started during Linaro Connect
provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) C3
Signed-off-by: Claudio Fontana claudio.font...@linaro.org
Signed-off-by: Alex Bennée a...@bennee.com
Reviewed-by: Alex
Hello,
On 09/27/2013 08:25 PM, Richard Henderson wrote:
On 09/26/2013 05:48 PM, Alexander Graf wrote:
This patch adds emulation support for the orr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 28 +++
target-arm/helper-a64.h| 1 +
On 11/18/2013 02:15 PM, Peter Maydell wrote:
On 18 November 2013 13:12, Michael Matz m...@suse.de wrote:
Hi,
On Mon, 18 Nov 2013, Claudio Fontana wrote:
+case 3:
+tcg_gen_rotr_i64(r, cpu_reg(reg), tcg_shift);
+break;
Incorrect rotate for 32bit?
32bit rotates
Btw, in the first patch:
On 11/18/2013 02:12 PM, Michael Matz wrote:
From df54486da31d6329696effa61096eda5ab85395a Mon Sep 17 00:00:00 2001
From: Michael Matz m...@suse.de
Date: Sun, 24 Mar 2013 02:52:42 +0100
Subject: [PATCH] Fix 32bit rotates.
The 32bit shifts generally weren't careful
Hello all,
On 09/27/2013 02:48 AM, Alexander Graf wrote:
This patch adds emulation support for the adr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 24
1 file changed, 24 insertions(+)
diff --git
On 11/19/2013 06:17 PM, Claudio Fontana wrote:
Hello all,
On 09/27/2013 02:48 AM, Alexander Graf wrote:
This patch adds emulation support for the adr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 24
1 file changed, 24
On 09/27/2013 09:42 PM, Richard Henderson wrote:
On 09/26/2013 05:48 PM, Alexander Graf wrote:
+if (setflags) {
+tcg_dst = cpu_reg(dest);
+} else {
+tcg_dst = cpu_reg_sp(dest);
+}
Never sp for logicals.
This should be ok in my view, the manual explicitly shows
0
#define TCG_TARGET_HAS_ext8s_i641
#define TCG_TARGET_HAS_ext16s_i64 1
--
Claudio Fontana
Server OS Architect
Huawei Technologies Duesseldorf GmbH
Riesstraße 25 - 80992 München
office: +49 89 158834 4135
mobile: +49 15253060158
on Aarch64 Foundationv8 (sparc-softmmu, arm-softmmu,
x86_64-softmmu).
Tested-by: Claudio Fontana claudio.font...@huawei.com
Reviewed-by: Claudio Fontana claudio.font...@huawei.com
: Implement tlb lookup fast path
configure|2 +-
include/exec/exec-all.h | 14 +++
tcg/aarch64/tcg-target.c | 224
+++---
3 files changed, 189 insertions(+), 51 deletions(-)
It's good for me, thank you Jani.
Reviewed-by: Claudio
Hi Jani,
On 20.06.2013 12:53, Jani Kokkonen wrote:
Supports CONFIG_QEMU_LDST_OPTIMIZATION
Signed-off-by: Jani Kokkonen jani.kokko...@huawei.com
---
configure|2 +-
include/exec/exec-all.h | 16 +++-
tcg/aarch64/tcg-target.c | 197
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