On 7/25/23 20:39, Fan Ni wrote:
> From: Fan Ni
>
> Not all dpa range in the dc regions is valid to access until an extent
> covering the range has been added. Add a bitmap for each region to
> record whether a dc block in the region has been backed by dc extent.
> For the bitmap, a bit in the
On 7/25/23 20:39, Fan Ni wrote:
> From: Fan Ni
>
> Add dynamic capacity extent list representative to the definition of
> CXLType3Dev and add get DC extent list mailbox command per
> CXL.spec.3.0:.8.2.9.8.9.2.
>
> Signed-off-by: Fan Ni
> ---
> hw/cxl/cxl-mailbox-utils.c | 71
On 7/25/23 20:39, Fan Ni wrote:
> From: Fan Ni
>
> Per CXL spec 3.0, two mailbox commands are implemented:
> Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and
> Release Dynamic Capacity (Opcode 4803h) 8.2.9.8.9.4.
>
> Signed-off-by: Fan Ni
> ---
> hw/cxl/cxl-mailbox-utils.c |
On 2/18/23 11:22, Gregory Price wrote:
> Breaking this off into a separate thread for archival sake.
>
> There's a bug with handling execution of instructions held in CXL
> memory - specifically when an instruction crosses a page boundary.
>
> The result of this is that type-3 devices cannot use
On 2/28/23 11:49, Jonathan Cameron wrote:
>>> Second there's the performance issue:
>>>
>>> 0) Do we actually care about performance? How likely are users to
>>> attempt to run software out of CXL memory?
>>>
>>> 1) If we do care, is there a potential for converting CXL away from the
>>>
ed-by: Sid Manning
> Reported-by: Jørgen Hansen
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/translator.c | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
> index ef5193c67e..1cf404
On 2/21/24 19:15, nifan@gmail.com wrote:
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> on links or open attachments unless you recognize the sender and know that
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>
>
> From: Fan Ni
>
> With the change, when setting up memory for
On 2/21/24 19:15, nifan@gmail.com wrote:
> CAUTION: This email originated from outside of Western Digital. Do not click
> on links or open attachments unless you recognize the sender and know that
> the content is safe.
>
>
> From: Fan Ni
>
> Per cxl spec r3.1, add dynamic capacity
> On 15 Mar 2024, at 13.25, Alex Bennée wrote:
>
> Jørgen Hansen writes:
>
>> Hi,
>>
>> While doing some testing using numactl-based interleaving of application
>> memory
>> across regular memory and CXL-based memory using QEMU with tcg, I ran into
Hi,
While doing some testing using numactl-based interleaving of application memory
across regular memory and CXL-based memory using QEMU with tcg, I ran into an
issue similar to what we saw a while back - link to old issue:
On 3/25/24 20:02, nifan@gmail.com wrote:
> From: Fan Ni
>
> With the change, we extend the extent release mailbox command processing
> to allow more flexible release. As long as the DPA range of the extent to
> release is covered by accepted extent(s) in the device, the release can be
>
second page turned out to be mmio. In this case we
> truncate the block, and the previous logic for can_do_io could leave
> a block with a single insn with can_do_io set to false, which would
> fail an assertion in cpu_io_recompile.
>
> Reported-by: Jørgen Hansen
> Signed-off-by: Ric
On 3/25/24 20:02, nifan@gmail.com wrote:
> From: Fan Ni
>
> Per CXL spec 3.1, two mailbox commands are implemented:
> Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.9.9.3, and
> Release Dynamic Capacity (Opcode 4803h) 8.2.9.9.9.4.
>
> For the process of the above two commands, we use
On 4/15/24 19:56, fan wrote:
> From 4b9695299d3d4b22f83666f8ab79099ec9f9817f Mon Sep 17 00:00:00 2001
> From: Fan Ni
> Date: Tue, 20 Feb 2024 09:48:30 -0800
> Subject: [PATCH 08/13] hw/cxl/cxl-mailbox-utils: Add mailbox commands to
> support add/release dynamic capacity response
>
> Per CXL
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