Marcel Kilgus via Ql-Users wrote:
> I've already started putting together a clone using an Xilinx
> XC9572XL, which I have lying around. The Verilog file compiled from
> the get-go, I just had to remove the additional SS lines because of
> Pin restrictions in the small chip on my eval board. The
On 2 Feb 2018 at 16:25, Marcel Kilgus via Ql-Users wrote:
> Well, I said I'd do it and apparently I did it:
>
> https://www.kilgus.net/2018/02/02/clonetastic-ql-sd-clone-working-with-goldcard-clone/
What surprises me is this: "With the original Verilog code my clone
didn't work at all, so it's
Marcel, would you be willing to share your modifications for QL-SD2?
Dave
On Fri, Feb 2, 2018 at 10:51 AM, pgraf--- via Ql-Users <
ql-users@lists.q-v-d.com> wrote:
> On 2 Feb 2018 at 16:25, Marcel Kilgus via Ql-Users wrote:
>
> > Well, I said I'd do it and apparently I did it:
> >
> >
pgraf--- via Ql-Users wrote:
>> Well, I said I'd do it and apparently I did it:
>>
>> https://www.kilgus.net/2018/02/02/clonetastic-ql-sd-clone-working-with-goldcard-clone/
> What surprises me is this: "With the original Verilog code my clone
> didn't work at all, so it's definitely not just the
Dave Park via Ql-Users wrote:
> Marcel, would you be willing to share your modifications for QL-SD2?
Sure, I can be bribed :-P Also, it's GPLed anyway... but I want to
make some more tests, preferably with the original hardware first.
Marcel
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