But ASIC is usually updating the paper area most of the time...
So I'd like to know how does it perform in paper area.
Also, I made the following change to my program: I removed the FRAME
interrupt handler and replaced it with LINE 191 interrupt handling. This way
I put the top and bottom border
And what are those numbers after semicolons (in the asm code below)?
I originally though it's number of T-states, but POP must take at least 12T,
definitely not 4T.
/---
Aley
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On
Behalf Of Edwin Blink
Sent: Tuesday,
- Original Message -
From: Aley Keprt [EMAIL PROTECTED]
I originally though it's number of T-states, but POP must take at least
12T,
definitely not 4T.
Obviously a typing mistake :-)
here are some more timings for PUSH/POP:
PUSH qq (5,3,3) Standard =11Ts
PUSH qq (5+3,3+1,3+1) RAM
Incidentally, what are the 5 cycles for an LDIR?
It uses the same technique as used by relative jumps to add a value of -2
to PC.
so is it really the case that the z80 reads the (erroneous) next
instruction before doing PC-=2 (as
one source on the web suggested)?
I think that suggestion
Edwin Blink wrote:
Incidentally, what are the 5 cycles for an LDIR?
It uses the same technique as used by relative jumps to add a value
of -2 to PC.
Without wishing to appear stupid (yeah, I know, too late, haha), I'm still
not clear why that's a memory access.
I've found a more helpful
From: Geoff Winkless [EMAIL PROTECTED]
Without wishing to appear stupid (yeah, I know, too late, haha), I'm still
not clear why that's a memory access.
It's not. The delay is added there for convenience. But in fact it will
delay the next
opcode fetch (unless it is in rom but read below).
I can't remember if thats the case with Colins device he showed recently?Edwin Blink [EMAIL PROTECTED] wrote:
From: Geoff Winkless <[EMAIL PROTECTED]> Without wishing to appear stupid (yeah, I know, too late, haha), I'm still not clear why that's a memory access.It's not. The delay is added there
On Wed, 2005-02-02 at 19:11, Edwin Blink wrote:
I'd prefer a redesigned ASIC (with a few other fixes). I see little
advantage in
having a accelerator board Because the extra power is needed in handling
video memory. An accelerator board would have to wait just like the Z80
does.
A simple
