On Sat, 23 Jun 2018, Mark Kettenis wrote:
> > Date: Fri, 22 Jun 2018 17:16:14 +0200 (CEST)
> > From: Mark Kettenis
> >
> > It takes the alpha/hppa/mips64 approach of storing the state in struct
> > sigcontext instead of using a pointer. Using unsigned int and
> > unsigned long long instead of
There is a comma missing in rev 1.44:
Index: cpu.h
===
RCS file: /cvs/src/sys/arch/arm/include/cpu.h,v
retrieving revision 1.44
diff -u -p -r1.44 cpu.h
--- cpu.h 2 Mar 2017 10:38:10 - 1.44
+++ cpu.h 3 Mar 2017
Am 19.09.2016 um 22:30 schrieb Philip Guenther:
On Mon, Sep 19, 2016 at 11:02 AM, Jasper Lievisse Adriaanse
wrote:
OK?
Index: alpha/alpha/db_trace.c
...
ok guenther@
There is one too many closing brace in the arm code:
Index: sys/arch/arm/arm/db_trace.c
On Wed, 20 Nov 2013, Jonathan Gray wrote:
On Tue, Nov 19, 2013 at 01:09:32AM +1100, Jonathan Gray wrote:
On Sat, Nov 16, 2013 at 10:42:05AM +0100, Markus Hennecke wrote:
On Sat, 9 Nov 2013, Jonathan Gray wrote:
This adds the initial bits for the i217/i218 PHY and the
Lynx Point
On Sat, 9 Nov 2013, Jonathan Gray wrote:
This adds the initial bits for the i217/i218 PHY and the
Lynx Point PCH found in Haswell systems.
Doesn't include the new workarounds yet and follows
the pch2/82579 paths for now but this seems to be enough
to make a desktop machine with I217-LM
On Sat, 12 Oct 2013, Patrick Wildt wrote:
Am 11.10.2013 um 22:46 schrieb Artturi Alm artturi@gmail.com:
On 10/11/13 20:39, Markus Hennecke wrote:
About ethaddr, have you tried pinging another host from u-boot?
Does your u-boot support emac? the one i initially downloaded
On Sat, 5 Oct 2013, Artturi Alm wrote:
Current version attached, extract to /sys/arch/armv7 and read the short
notes file, no more out of allwinner/ patches needed thanks to armv7.
A20 support still needs a workaround under /sys/arch/arm/cortex/ which
i didn't include as i think support is
On 06/09/11 17:02, Kenneth R Westerback wrote:
On Thu, Jun 09, 2011 at 12:18:06AM +0200, Mark Kettenis wrote:
The current amd64 code allows for a fairly limited number of device
interrupts on the primary CPU. The exact number is a bit fuzzy, but
is somewhere between 11 and 27. If you go