On Thu, Mar 17, 2022 at 07:12:16AM +, Visa Hankala wrote:
> On Wed, Mar 16, 2022 at 11:09:12PM +0100, Alexander Bluhm wrote:
> > On Tue, Mar 15, 2022 at 09:15:34AM +, Visa Hankala wrote:
> > > However, some DEC Alpha CPUs have their data caches divided into cache
> > > banks to improve
On Wed, Mar 16, 2022 at 11:09:12PM +0100, Alexander Bluhm wrote:
> On Tue, Mar 15, 2022 at 09:15:34AM +, Visa Hankala wrote:
> > However, some DEC Alpha CPUs have their data caches divided into cache
> > banks to improve bandwidth. These cache banks are relatively
> > independent. The system
On Tue, Mar 15, 2022 at 09:15:34AM +, Visa Hankala wrote:
> However, some DEC Alpha CPUs have their data caches divided into cache
> banks to improve bandwidth. These cache banks are relatively
> independent. The system maintains coherency, but bus contention can
> delay propagation of cache
This removes the data dependency consumer barrier from the atomic_load_*
functions. I think the intent was to keep these functions relaxed in
terms of CPU memory order.
This makes these functions more agreeable in code that assertions may
use, such as the suggested refcnt_read().
Removing the
