Hi
Unless you have fancy switches on your LAN (1588 stamping), PTP performance
will be dependent on load and the “goodness” of the switches you do have. These
are pretty much the same (external) things that impact NTP. On a LAN with
variable
loading (time to stream some movies …) the
Frank;
Thanks for your long and detailed explanation.
I was able to get the internal OCXO to that precision but it was probably
luck
to get the trimmer that close. I worked at it for a while.
I am using T.I. mode with the averaging mode. I assumed that it took 10K
readings
and averaged the
On Mon, June 15, 2015 8:01 pm, Bob Camp wrote:
Unless you have fancy switches on your LAN (1588 stamping), PTP
performance will be dependent on load and the goodness of the switches
you do
have. These are pretty much the same (external) things that impact NTP.
Yes, but proper differentiated
Hi
I’ve spent a lot of time with both of those papers and with a couple of others
in the “series’. The gotcha is in the interpretation of the calibration
results. It
is often very unclear which pattern comes before which other pattern. Since
the internal PLL’s have jitter in the 20 to 30 ps RMS
kb...@n1k.org said:
Since the internal PLLâs have jitter in the 20 to 30 ps RMS range, that
limits a lot of the data you get.
I haven't looked recently, but I doubt if much has changed. Xilinx uses DLLs
rather than PLLs.
They have a long chain of buffers and a giant multiplexor to
Using an ADC to sample a triggered damped sinewave easily achieves 5ps
resolution (eg Keysight Acquiris). With a better optimised waveform model
and least squares fitting routine greater resolution is feasible.
The accuracy is dependent on the ADC sampling clock stability.
An optical frequency
Hi
Coming up with a reference clock can be harder than you might think.
Most of the jitter numbers you see published on frequency sources are based on a
“jitter mask” that runs from (maybe) 10 KHz up to 20 MHz. That’s fine for a
specific
telecom need. It may not in any way apply to capturing a
On Mon, June 15, 2015 1:23 am, David J Taylor wrote:
I don't think either system is good enough as a microsecond level
server, but either is fine for tenth millisecond level.
The BeagleBone Black has the advantage that you can run one of the timers
from an external input, so you can use the
So we finally got in our test Heol N024 GPS replacement board for the
Trimble Ace III that ran into the 1995 rollover and most notably
affected just about everyone with a Datum/Symmetricom/Microsemi TymServe
2100.
As Olivier Descoubes (the contact at Heol) posted I can confirm that
their
It also has better performance than the original board and some newer
NTP servers that use older GPS. This is just based off of data that I'm
reading. I'm not proficient enough to do testing and analysis on it
other than the data sheet and what my TymServe display tells me.
If anyone has any
Hi
Just to be clear, your peer delay numbers for the Pi show and improvement
from 0.5 ms down to 0.3 ms with some tweaks. A “non-usb” ethernet setup can
get those delays down much further. In the context of the original question
“tweaking the USB drivers” this is what was being addressed.
Pete,
you do not specify, whether you use FREQ or T.I. when you use the
averaging function.
First of all, its OCXO can be adjusted to a few parts in 1e-9 only, as
the trimmer is too unprecise.
If the OCXO is running for several weeks already (idle state), its drift
may be as low as a few
On Wed, 10 Jun 2015 21:45:33 -0400
Bob Camp kb...@n1k.org wrote:
The delay line in an FPGA approach might get you to 20 ps. There is a lot of
hand
waving in the calibration process to get there. ( = figuring out that state A
came before
state B is based on things that are difficult to
On Thu, 11 Jun 2015 14:22:58 +
Alan Ambrose alan.ambr...@anagram.net wrote:
A clever interpolator for frequency or TIC would kill it -
for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with
a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC
and an 80 MHz
On Fri, 12 Jun 2015 18:29:29 -0400
Ed Armstrong eds_equipm...@verizon.net wrote:
The Ethernet on the Raspberry Pi is on the USB bus. That adds about a 1/2
ms
of jitter.
Is it possible to modify the kernel so the USB is polled more often, and
would that significantly reduce the jitter?
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