Dr Bruce Griffiths wrote:
The design is probably a pair of low noise n channel JFETs
configured as a push push doubler.
Inputs driven in antiphase so that each FET conducts ffor
opposite 1/2 cycles with the 2 FET drains connected in parallel.
A bypassed trimpot connected between the FET
Christopher Hoover wrote:
Dr Bruce Griffiths wrote:
The design is probably a pair of low noise n channel JFETs
configured as a push push doubler.
Inputs driven in antiphase so that each FET conducts ffor
opposite 1/2 cycles with the 2 FET drains connected in parallel.
A bypassed
Christopher Hoover wrote:
Dr Bruce Griffiths wrote:
The design is probably a pair of low noise n channel JFETs
configured as a push push doubler.
Inputs driven in antiphase so that each FET conducts ffor
opposite 1/2 cycles with the 2 FET drains connected in parallel.
A bypassed