In my mind, at least, this is still the same subject…
Does anyone have any results to share re the SiLabs Si53xx ‘Jitter Attenuating
Clock Multipliers’?
Is this a helpful way to supply a 1GHz counter with a ‘0.1ps rms phase jitter’
clock?
Alan
___
On Wed, 17 Jun 2015 09:32:23 +1200
Bruce Griffiths bruce.griffi...@xtra.co.nz wrote:
Do you mean the technique that Panek et al. [1] are using?
Not quite he used an impulse to excite a saw filter rather than switching
off the dc current feed to an inductor or the equivalent.
Is there any
I used the output of a CMOS frequency divider to drive a capacitor coupled
passive dual diode and resistor plus a parallel tank circuit comprising a 1uH
powdered iron core (amidon #6) inductor and a 100pF silvered mica capacitor.
The ADC used a 100MHz clock which also drove the frequency
Hoi Bruce,
On Tue, 16 Jun 2015 12:24:34 +1200
Bruce Griffiths bruce.griffi...@xtra.co.nz wrote:
Using an ADC to sample a triggered damped sinewave easily achieves 5ps
resolution (eg Keysight Acquiris). With a better optimised waveform model
and least squares fitting routine greater
Hi
On Jun 15, 2015, at 11:26 PM, Hal Murray hmur...@megapathdsl.net wrote:
kb...@n1k.org said:
Since the internal PLL’s have jitter in the 20 to 30 ps RMS range, that
limits a lot of the data you get.
I haven't looked recently, but I doubt if much has changed. Xilinx uses DLLs
On Mon, 15 Jun 2015 20:26:09 -0700
Hal Murray hmur...@megapathdsl.net wrote:
Does anybody have data on what the jitter actually looks like? I'd expect
several blurry peaks, with the spacing between peaks being the step size of
the delay/mux chain and the blur being wider if there is more
On Tuesday, June 16, 2015 10:01:09 AM Attila Kinali wrote:
Hoi Bruce,
On Tue, 16 Jun 2015 12:24:34 +1200
Bruce Griffiths bruce.griffi...@xtra.co.nz wrote:
Using an ADC to sample a triggered damped sinewave easily achieves
5ps
resolution (eg Keysight Acquiris). With a better optimised
Hi
I’ve spent a lot of time with both of those papers and with a couple of others
in the “series’. The gotcha is in the interpretation of the calibration
results. It
is often very unclear which pattern comes before which other pattern. Since
the internal PLL’s have jitter in the 20 to 30 ps RMS
kb...@n1k.org said:
Since the internal PLLâs have jitter in the 20 to 30 ps RMS range, that
limits a lot of the data you get.
I haven't looked recently, but I doubt if much has changed. Xilinx uses DLLs
rather than PLLs.
They have a long chain of buffers and a giant multiplexor to
Using an ADC to sample a triggered damped sinewave easily achieves 5ps
resolution (eg Keysight Acquiris). With a better optimised waveform model
and least squares fitting routine greater resolution is feasible.
The accuracy is dependent on the ADC sampling clock stability.
An optical frequency
Hi
Coming up with a reference clock can be harder than you might think.
Most of the jitter numbers you see published on frequency sources are based on a
“jitter mask” that runs from (maybe) 10 KHz up to 20 MHz. That’s fine for a
specific
telecom need. It may not in any way apply to capturing a
On Wed, 10 Jun 2015 21:45:33 -0400
Bob Camp kb...@n1k.org wrote:
The delay line in an FPGA approach might get you to 20 ps. There is a lot of
hand
waving in the calibration process to get there. ( = figuring out that state A
came before
state B is based on things that are difficult to
On Thu, 11 Jun 2015 14:22:58 +
Alan Ambrose alan.ambr...@anagram.net wrote:
A clever interpolator for frequency or TIC would kill it -
for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with
a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC
and an 80 MHz
Hello
It also depends on which device primitives you can use. Xilinx spartan
series has an SRL16, 16 bit shift register that can be ganged to form dividers
/ pre scalers. It only takes up one lut or slice, I forget which.
Link
On Jun 11, 2015, at 4:11 AM, Bob Camp kb...@n1k.org wrote:
Hi
Hi
The whole “weird primitives” thing is why I try to count this stuff in
registers (flip flops) used rather than what ever neat name the marketing guys
came up with this week that sounds better than “glob of stuff”.
Bob
On Jun 12, 2015, at 11:44 PM, lincoln linc...@ampmonkeys.com wrote:
Hi
Well, take the CPLD up to 100 MHz, and feed 20 ns pulses to the TDC’s RC, drive
that into a cheap 24 bit sigma delta A/D and you have an easy 1 Fs. Do a little
processing on multiple samples and you have 15 displayed digits.
=
Of course everything past about 50 ps is just noise ….
It
On Tue, Jun 9, 2015 at 11:40 AM, Alan Ambrose alan.ambr...@anagram.net wrote:
How about a 1pS resolution TIC? :)
Or a 12 digit frequency counter? :) :)
It's not a proper time-nut project unless there's a nutty element...
Well, how complex? Front end with a fast ADC and make a DSP DMTD
Hi
Depending on which chip you are using and how big it is, you can get into the
150 to
500 ps range running a carry chain as a TDC.That’s without getting into things
like
hand routing and temperature / voltage issues.
How big a chip you need will be a function of how high you can get the
Hi,
So that turns into 2 games:
How fast can you count?
How many digits can you get in 1 second?
A clever interpolator for frequency or TIC would kill it - for TIC essentially
a PICTIC on steroids. The PICTIC does 19pS with a 10 bit ADC and a 66MHz clock,
an SR620 does 4pS with a 12 bit
alan.ambr...@anagram.net said:
How about a 1pS resolution TIC? :)
An alternative way to describe that sort of problem is
How accurately can you locate an edge?
I haven't looked carefully at the Spartan 3E. You might be able to run a
signal along a column through a slow path and clock the
HI
On Jun 10, 2015, at 3:28 AM, Hal Murray hmur...@megapathdsl.net wrote:
alan.ambr...@anagram.net said:
How about a 1pS resolution TIC? :)
An alternative way to describe that sort of problem is
How accurately can you locate an edge?
I haven't looked carefully at the Spartan 3E.
Hi,
This thread really makes me want to do an FPGA timing project. I have a
Papilio One on hand, which uses the Spartan 3E.
But what to do with it? It has to be something much more interesting than
what a PicDiv or simple logic can do to make it worth my time. Hmm...
How about a 1pS
Sent: 08 June 2015 15:09
To: time-nuts@febo.com
Subject: Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
On Sun, 07 Jun 2015 11:23:40 +0100, David C. Partridge wrote:
My reading so far of what's been said in this thread is that you might
get good results using a CPLD/FPGA
On Mon, 08 Jun 2015 16:27:26 +0100, David C. Partridge wrote:
I'm up for either ... My thoughts are to try it out on a development
board and if it works, maybe build a few for possible sale, and also
release Gerbers and VHDL files.
Regards,
David Partridge
I have these cheap cards ,
On Sun, 07 Jun 2015 11:23:40 +0100, David C. Partridge wrote:
My reading so far of what's been said in this thread is that you might
get good results using a CPLD/FPGA as a divider but ... .
..
..
..
Thanks again Dave
Is this going to be an open source project, or something you buy ?
CFO
My reading so far of what's been said in this thread is that you might get good
results using a CPLD/FPGA as a divider but ... .
Bruce pointed me to Rubiola's paper
http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf,
and while I'm sure the lambda divider is excellent,
Hi
As always, the real answer is “that depends”.
If you are dividing to 1 pps from 10 MHz, the CPLD or FPGA is a fine answer to
the question. It will give you some cool bells and whistles (like sync and
advance / retard) without adding anything to the budget. If you wish to re-sync
the
Hi
Last time I saw university multi project wafer prices, the cost was around $5K
for a
run on a “not state of the art” fab process. That included absolutely nothing
in the way of design assistance. It was strictly “we fab what you told us to
do”. The
“run date” for the chips was also a bit
rich...@karlquist.com said:
I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
timebase. It was great because you just write a 17 bit counter in VHDL and
there it is. You don't have to know anything about building digital
hardware any more (40 years of experience
The counter only had to run at ~50 MHz, on account of our
mode locked laser ran at that frequency. I don't remember
what the CPLD was rated at.
Rick
On 6/5/2015 8:19 PM, Hal Murray wrote:
rich...@karlquist.com said:
I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
Hi
On Jun 5, 2015, at 11:19 PM, Hal Murray hmur...@megapathdsl.net wrote:
rich...@karlquist.com said:
I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
timebase. It was great because you just write a 17 bit counter in VHDL and
there it is. You don't have to know
Hi
Here’s an example:
http://parts.arrow.com/item/detail/arrow-development-tools/bemicromax10#pg2e
https://www.altera.com/products/fpga/max-series/max-10/overview.highResolutionDisplay.html
There are other outfits that make similar parts that are at least as good. This
is considered a
low end
On Sat, 6 Jun 2015 09:52:11 -0400
Bob Camp kb...@n1k.org wrote:
Was it a simple
counter or was there enable/up/down/load type gating involved?
What would you have done if you needed to run a bit faster?
Bought a faster FPGA or gone to an ASIC.
Could you buy a
faster chip?
I used a CPLD in a 900 GHz (that's right 900 GHz) optical
sampling scope timebase. It was great because you just
write a 17 bit counter in VHDL and there it is. You
don't have to know anything about building digital
hardware any more (40 years of experience wasted).
Nobody cares about look
Thanks Bruce. That is an excellent option.
I did a paper over a decade ago on the jitter and phase noise for Actel
(Now Microsemi) comparing their eX device to the Xilinx CPLD. It was
intended to show the eX device was preferable to the Xilinx CPLD. It makes
a difference as to what device is
Hi
As always, the real answer it “that depends”.
If your objective is wide band phase noise and you want to start from 100 MHz
and get 10 MHz (fig 6 in
the Lamda paper), you can get at least another 6 db with a simple divide by 10
chip than with all the
fancy stuff.
Bob
On Jun 3, 2015,
Is this a sensible thing to consider doing? Or would I be better sticking to
AC/HC/AHC/LVC logic?
Regards,
David Partridge
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Is this a sensible thing to consider doing? Or would I be better sticking to
AC/HC/AHC/LVC logic?
Regards,
David Partridge
Yes, please consider it. I would be very interested in the results.
We measured under 2 ps jitter for the PIC dividers [1] used with the cute
little TADD-2 board
Programmable logic rocks. If you need a 13 bit counter, you can do that. It
is easy to create alarms and special controls.
Jerry
On Jun 2, 2015 2:22 PM, David C. Partridge david.partri...@perdrix.co.uk
wrote:
Is this a sensible thing to consider doing? Or would I be better sticking
to
Hi
A lot depends on exactly which CPLD or which FPGA you are looking at and how
they put the guts of it together. If you find one that is “just right” it
*might* be within
10 db of high speed CMOS. Since there is a 20 db delta between the HC you
mention
and the AC that leaves a bit of room.
david.partri...@perdrix.co.uk said:
Is this a sensible thing to consider doing? Or would I be better sticking
to AC/HC/AHC/LVC logic?
A CPLD is a fine way to divide by a large number. Even the smaller FPGAs are
probably overkill but they should work fine.
If you are interested in jitter,
Am 02.06.2015 um 21:27 schrieb Tom Van Baak:
Is this a sensible thing to consider doing? Or would I be better sticking to
AC/HC/AHC/LVC logic?
Regards,
David Partridge
Yes, please consider it. I would be very interested in the results.
I have made a stamp sized board that has a Xilinx 2C64
On Tue, 2 Jun 2015 14:13:04 +0100
David C. Partridge david.partri...@perdrix.co.uk wrote:
Is this a sensible thing to consider doing?
Or would I be better sticking to AC/HC/AHC/LVC logic?
It depends ;-)
For most things it should be ok. You can reach lower levels of noise
with single 74xxx
On Tuesday, June 02, 2015 02:13:04 PM David C. Partridge wrote:
Is this a sensible thing to consider doing? Or would I be better sticking
to AC/HC/AHC/LVC logic?
`
Regards,
David Partridge
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To
You can always cleanup the outputs of the CPLD or FPGA by resynchronising the
outputs to the input clock using a dedicated D flipflop for each output.
Bruce
On Wednesday, 3 June 2015 3:22 PM, Bob Camp kb...@n1k.org wrote:
Hi
A lot depends on exactly which CPLD or which FPGA you
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