On Jan 20, 2011, at 1:59 AM, Kumar Gala wrote:
ctrl_regs.c: In function 'set_ddr_sdram_mode_2':
ctrl_regs.c:690:6: warning: unused variable 'i'
'i' is only used by DDR3 code.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |2 +-
1
On Jan 19, 2011, at 11:01 PM, Kumar Gala wrote:
The following changes since commit e1ccf97c5d7651664d37c0c5aa243874b8851b2d:
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2011-01-17
20:31:46 +0100)
are available in the git repository at:
On 01/20/2011 03:06 AM, Thomas Besemer wrote:
Hi folks -
I had posted last week. I was able to get basic Splash Screen going on EVK,
through using patches I found from googling around. At the end of this email,
the patch set that shows the differences from the U-Boot I pulled on
On 01/18/2011 04:37 PM, Sergei Shtylyov wrote:
Hello.
Stefano Babic wrote:
From: Anatolij Gustschin ag...@denx.de
The MXC SPI driver didn't calculate the SPI clock up to
now and just highest possible divider 512 for DATA
^
I think used shouldn't have been ommitted
The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.
Features supported by IFC are,
Dear Tom Warren,
In message 1295471986-2395-2-git-send-email-twar...@nvidia.com you wrote:
Signed-off-by: Tom Warren twar...@nvidia.com
checkpatch.pl reports:
total: 6 errors, 12 warnings, 1155 lines checked
/tmp/patch has style problems, please review.
Please clean up.
Dear Alex Dubov,
In message 25376.26093...@web37608.mail.mud.yahoo.com you wrote:
Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
memory, real time clock and additional serial EEPROM on i2c bus
Patchset V2 contain patches for SPI sent previously independently to ML
and additional patches for I2C.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Signed-off-by: Stefano Babic sba...@denx.de
CC: Heiko Schocher h...@denx.de
---
Changes:
Wolfgang Denk:
- Do not use XXX in defines because are blocked by SPAM filters
drivers/i2c/mxc_i2c.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git
The patch adds UART support for the i.MX35 processor.
Signed-off-by: Stefano Babic sba...@denx.de
---
drivers/serial/serial_mxc.c | 15 ++-
1 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index
This driver accesses to processor's register
via __REG macros, that are removed (or are planned
to be removed) and replaced by C structures.
This patches replaces all occurrencies of __REG macros.
Signed-off-by: Stefano Babic sba...@denx.de
CC: Heiko Schocher h...@denx.de
---
There is sporadic failures when more as one I2C slave
is on the bus and the processor tries to communicate
with more as one slave.
The problem was seen on a mx35pdk (two I2C slaves,
PMIC controller and CAN/RTC chip).
Signed-off-by: Stefano Babic sba...@denx.de
CC: Heiko Schocher h...@denx.de
---
The patch adds helper funtions for basic access to the registers
of the MC9sdz60 chip (multifunctional device with RTC and CAN) via
I2C interface.
Signed-off-by: Stefano Babic sba...@denx.de
---
drivers/misc/Makefile |5 ++-
drivers/misc/mc9sdz60.c | 51
From: Anatolij Gustschin ag...@denx.de
We need to shift only one time in each cycle in the swapping loop
for unaligned tx case. Currently two byte shift operations are
performed in each loop cycle causing zero gaps in the transmited
data, so not all data scheduled for transmition is actually
Signed-off-by: Stefano Babic sba...@denx.de
---
drivers/spi/mxc_spi.c | 96
1 files changed, 72 insertions(+), 24 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index d558137..5670714 100644
--- a/drivers/spi/mxc_spi.c
From: Anatolij Gustschin ag...@denx.de
The MXC SPI driver didn't calculate the SPI clock up to
now and just used highest possible divider 512 for DATA
RATE in the control register. This results in very low
transfer rates.
The patch adds code to calculate and setup the SPI clock
frequency for
This patch cleans driver code replacing all accesses
to registers with fixed offsets with a corresponding
structure.
Signed-off-by: Stefano Babic sba...@denx.de
---
arch/arm/include/asm/arch-mx31/mx31-regs.h | 11 +++
arch/arm/include/asm/arch-mx35/imx-regs.h | 12
The patch adds suupport for the Freescale's mx35pdk board
(known as well as mx35_3stack).
The board boots from the NOR flash. Following devices
are supported:
- two ethernet devices (FEC and SMC911x on debug board)
- I2C
- PMIC (MC13892) via I2C interface
- UART
- NOR flash (64MB)
- NAND
Dear Dipen Dudhat,
In message 1295509580-28959-1-git-send-email-dipen.dud...@freescale.com you
wrote:
The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of
We're trying to configure the PPC P2020 cpu to use the L2 cache
as SRAM so we can load the U-Boot code in there. However we
stumble into problems. Sometimes the cpu goes on trap when
trying to access this area. Sometimes there's no trap but we
seem to access a different area. That's probably
Dear Stefano Babic,
In message 1295513194-16158-2-git-send-email-sba...@denx.de you wrote:
The patch adds basic support for the Freescale's i.MX35
(arm1136 based) processor.
Signed-off-by: Stefano Babic sba...@denx.de
checkpatch says:
[U-Boot] [PATCH V2 01/11] Add support for MX35
Dear Stefano Babic,
In message 1295513194-16158-5-git-send-email-sba...@denx.de you wrote:
This driver accesses to processor's register
via __REG macros, that are removed (or are planned
to be removed) and replaced by C structures.
This patches replaces all occurrencies of __REG macros.
Dear Stefano Babic,
In message 1295513194-16158-6-git-send-email-sba...@denx.de you wrote:
There is sporadic failures when more as one I2C slave
is on the bus and the processor tries to communicate
with more as one slave.
The problem was seen on a mx35pdk (two I2C slaves,
PMIC controller and
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are only
ever connected on SERDES.
Updated MPC85xx_PORDEVSR_IO_SEL MPC85xx_PORDEVSR_IO_SEL_SHIFT
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Dear Stefano Babic,
In message 1295513194-16158-9-git-send-email-sba...@denx.de you wrote:
From: Anatolij Gustschin ag...@denx.de
We need to shift only one time in each cycle in the swapping loop
for unaligned tx case. Currently two byte shift operations are
performed in each loop cycle
Dear Stefano Babic,
In message 1295513194-16158-11-git-send-email-sba...@denx.de you wrote:
This patch cleans driver code replacing all accesses
to registers with fixed offsets with a corresponding
structure.
Checkpatch says:
[U-Boot] [PATCH V2 10/11] SPI: mxc_spi: replace fixed
Dear Stefano Babic,
In message 1295513194-16158-12-git-send-email-sba...@denx.de you wrote:
The patch adds suupport for the Freescale's mx35pdk board
(known as well as mx35_3stack).
Checkpatch says:
[U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board.
total: 0
Dear Dudhat Dipen-B09055,
In message
57d3ab35efb0e542a4326dbd78e17e950a5...@039-sn1mpn1-005.039d.mgd.msft.net you
wrote:
Please find my comment inline with your comment.
Please do not full quote.
Checkpatch says:
[Dudhat Dipen-B09055] Now all the architecture related header files are
Dear Stefano Babic,
In message 1295513194-16158-1-git-send-email-sba...@denx.de you wrote:
Patchset V2 contain patches for SPI sent previously independently to ML
and additional patches for I2C.
I just learned that I was running an old version of checkpatch, which
turned out some false
Dear Prabhakar Kushwaha,
In message 1295515858-4011-1-git-send-email-prabha...@freescale.com you wrote:
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are only
ever connected on SERDES.
...
+void
On 01/20/2011 10:25 AM, Wolfgang Denk wrote:
Dear Stefano Babic,
In message 1295513194-16158-2-git-send-email-sba...@denx.de you wrote:
The patch adds basic support for the Freescale's i.MX35
(arm1136 based) processor.
Signed-off-by: Stefano Babic sba...@denx.de
checkpatch says:
On 01/20/2011 10:27 AM, Wolfgang Denk wrote:
Dear Stefano Babic,
In message 1295513194-16158-5-git-send-email-sba...@denx.de you wrote:
This driver accesses to processor's register
via __REG macros, that are removed (or are planned
to be removed) and replaced by C structures.
This patches
On 01/20/2011 10:30 AM, Wolfgang Denk wrote:
Dear Stefano Babic,
In message 1295513194-16158-6-git-send-email-sba...@denx.de you wrote:
There is sporadic failures when more as one I2C slave
is on the bus and the processor tries to communicate
with more as one slave.
The problem was seen on
On 01/20/2011 10:32 AM, Wolfgang Denk wrote:
Dear Stefano Babic,
In message 1295513194-16158-9-git-send-email-sba...@denx.de you wrote:
From: Anatolij Gustschin ag...@denx.de
We need to shift only one time in each cycle in the swapping loop
for unaligned tx case. Currently two byte shift
On 01/20/2011 10:33 AM, Wolfgang Denk wrote:
Dear Stefano Babic,
In message 1295513194-16158-11-git-send-email-sba...@denx.de you wrote:
This patch cleans driver code replacing all accesses
to registers with fixed offsets with a corresponding
structure.
Checkpatch says:
[U-Boot]
On 01/20/2011 10:41 AM, Wolfgang Denk wrote:
Dear Stefano Babic,
In message 1295513194-16158-12-git-send-email-sba...@denx.de you wrote:
The patch adds suupport for the Freescale's mx35pdk board
(known as well as mx35_3stack).
Checkpatch says:
[U-Boot] [PATCH V2 11/11] Add
On 01/20/2011 10:52 AM, Wolfgang Denk wrote:
Dear Stefano Babic,
In message 1295513194-16158-1-git-send-email-sba...@denx.de you wrote:
Patchset V2 contain patches for SPI sent previously independently to ML
and additional patches for I2C.
I just learned that I was running an old version
The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.
Features supported by IFC are,
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are only
ever connected on SERDES.
Updated MPC85xx_PORDEVSR_IO_SEL MPC85xx_PORDEVSR_IO_SEL_SHIFT
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are only
ever connected on SERDES.
Updated MPC85xx_PORDEVSR_IO_SEL MPC85xx_PORDEVSR_IO_SEL_SHIFT
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are only
ever connected on SERDES.
Updated MPC85xx_PORDEVSR_IO_SEL MPC85xx_PORDEVSR_IO_SEL_SHIFT
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
DM365 DM644X builds 'davinci_emac_mii_mode_sel()',
which uses 'davinci_syscfg_regs' macro, and the
macro is valid iff CONFIG_SOC_DA8XX is defined.
Fix: Before compiling 'davinci_emac_mii_mode_sel()', make sure that
CONFIG_SOC_DA8XX is defined.
Signed-off-by: Mohammed Afzal af...@ti.com
---
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are only
ever connected on SERDES.
Updated MPC85xx_PORDEVSR_IO_SEL MPC85xx_PORDEVSR_IO_SEL_SHIFT
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Dear Stefano Babic,
In message 4d380c25.20...@denx.de you wrote:
+ if (readl(ccm-pdr3) MXC_CCM_PDR3_UART_M_U)
+ freq = get_mcu_main_clk();
+ else
+ freq = decode_pll(readl(ccm-ppctl),
+ CONFIG_MX35_HCLK_FREQ);
Braces needed
checkpatch (and
Dear U-Boot Users,
I am using successfully U-boot for many years. So far I was dealing with the
system which has the Flash memory on board.
The u-boot binary and u-boot config parameters were stored in Flash.
Currently I am dealing with the new board which has Xilinx Virtex05 chip (with
built
Sehr geehrte
Ich heibe Chris Collinson und ich habe ein Angebot fur Sie!
Unser Unternehmen Jasckson Logistic sucht im Moment neue Arbeitskrafte! Wir
haben Ihre Bewerbungsunterlagen bei uns vor einige Zeit
liegen gefunden und jetzt mochten wir Ihnen eine Stelle von unseren
AuBendienstvertreter
Dear Stefano Babic,
In message 4d380e7f.60...@denx.de you wrote:
[U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add
total: 0 errors, 1 warnings, 22 lines checked
WARNING: braces {} are not necessary for single statement blocks
#31: FILE: drivers/spi/mxc_spi.c:375:
Dear Stefano Babic,
In message 4d381237.9040...@denx.de you wrote:
+ /* Print board revision */
+ puts(board_detect() ? 2.0 : 1.0);
+
+ /* Print CPU revision */
+ puts( i.MX35 );
I mentioned this before: If you make board_detect() return 1 or 2,
you can combine the calls
Dear Stefano Babic,
In message 4d381387.50...@denx.de you wrote:
[U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add
total: 0 errors, 1 warnings, 22 lines checked
Braces, braces...do you agree to follow checkpatch's rule (no braces for
single statement) ?
Try it out :-)
Dear Dach Miroslaw,
In message 1b4f8000449511488d1a640dd6deca350392a...@mailbox0a.psi.ch you
wrote:
Compact Flash has few partitions (ie. FAT and EXT2).
Is it possible to configure u-boot to access (ie. read/write) u-boot
parameters which are on Compact Flash as a file?
What do you mean
On 13 January 2011 19:14, Minkyu Kang mk7.k...@samsung.com wrote:
S5PC210 is a 32-bit RISC and Cortex-A9 Dual Core based micro-processor.
Signed-off-by: Minkyu Kang mk7.k...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
v2
fixtypo: RSIC - RISC, Coretex - Cortex
S5PC210 is a 32-bit RISC and Cortex-A9 Dual Core based micro-processor.
Signed-off-by: Minkyu Kang mk7.k...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
v3
support s5pc210 EVT1 cpu_id
v2
fix typo: RSIC - RISC, Coretex - Cortex
arch/arm/cpu/armv7/s5pc2xx/Makefile
This patch adds support for Samsung s5pc210 universal board
Signed-off-by: Minkyu Kang mk7.k...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
v3
remove config.mk
don't add board to MAKEALL
v2
remove debug message
MAINTAINERS |5 +-
Hello Wolfgang,
Thank you for your quick answer.
What do you mean my u-boot parameters?
To be clear I mean u-boot parameters the environment variables which are denied
for example:
CFG_ENV_IS_IN_FLASH
or
CFG_ENV_IS_IN_EEPROM
Note however that the opposite direction is harder: there is no FAT
Dear Minkyu Kang,
In message 4d382f3e.6080...@samsung.com you wrote:
S5PC210 is a 32-bit RISC and Cortex-A9 Dual Core based micro-processor.
...
new file mode 100644
index 000..69011fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-s5pc2xx/uart.h
...
+static int use_divslot = 0;
This is
Dear Dach Miroslaw,
In message 1b4f8000449511488d1a640dd6deca350392a...@mailbox0a.psi.ch you
wrote:
What do you mean my u-boot parameters?
To be clear I mean u-boot parameters the environment variables which are
denied for example:
CFG_ENV_IS_IN_FLASH
or
CFG_ENV_IS_IN_EEPROM
CFG_* ?
On 01/13/2011 06:16 PM, Minkyu Kang wrote:
This patch adds support for Samsung s5pc210 universal board
Signed-off-by: Minkyu Kangmk7.k...@samsung.com
Signed-off-by: Kyungmin Parkkyungmin.p...@samsung.com
---
v2
remove debug message
MAINTAINERS |5
From: Po-Yu Chuang ratb...@faraday-tech.com
This patch also update get_timer() usage.
Signed-off-by: Po-Yu Chuang ratb...@faraday-tech.com
---
drivers/net/ftmac100.c | 20 +---
1 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ftmac100.c
Hello.
Po-Yu Chuang wrote:
From: Po-Yu Chuang ratb...@faraday-tech.com
This patch also update get_timer() usage.
This seems like a material for a separate patch.
Signed-off-by: Po-Yu Chuang ratb...@faraday-tech.com
---
drivers/net/ftmac100.c | 20 +---
1 files
Dear Wolfgang,
Thank you again for your hints.
Then #define CONFIG_ENV_IS_NOWHERE
What would be than your suggestion
to access (read/write) u-boot (parameters) environ variables?
Reserve some space (like a tiny partition) somewhere on your CF card;
say 32 sectors for 16 kB environment data.
Dear seedshope,
In message 4d3841b2.8050...@gmail.com you wrote:
...
+int dram_init(void)
+{
+ gd-ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE;
It is shoule to use get_ram_size() function
This, like the others, are valid comments - but:
Can you please explain why you have to quote
On 01/19/2011 03:47 PM, Wolfgang Denk wrote:
Dear Peter Barada,
In message 4d371208.3090...@logicpd.com you wrote:
The hash delete code is in error; instead of just removing the deleted
key, it should instead allocate a new hashtable, hash all the keys into
the new table except for the
This patch serie fixes a problem in the UBI layer. The min I/O size has
currently a fixed value of 1 for NOR flashes. But for NOR flashes the min I/O
size has to be equal to the size of the writebuffer of the flash. Therefore the
mtd layer was enhanced with the writebuffer which was later on used
This field will be used to indicate the write buffer size
of the MTD device. UBI will set it's minimal I/O unit size
(min_io_size) to the indicated write buffer size. By this
change we intend to fix failed recovery of UBIFS partitions
we currently observe on NOR flash when mounting the partition
Initialize mtd-writebufsize to the value obtained by
by the CFI informations.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
---
drivers/mtd/cfi_mtd.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c
index
Initialize mtd-writebufsize to be equal to mtd-writesize.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
---
drivers/mtd/onenand/onenand_base.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/onenand/onenand_base.c
Initialize mtd-writebufsize to be equal to mtd-writesize.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
---
drivers/mtd/nand/nand_base.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index
Propagate the writebufsize to the partition's MTD object so
that UBI can set correct value for it's minimal I/O size
using the writebufsize field of MTD object of the partition.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
---
drivers/mtd/mtdconcat.c |1 +
drivers/mtd/mtdpart.c |
Previously we used mtd-writesize field to set UBI's minimal
I/O unit size. This sometimes caused UBIFS recovery issues
when mounting an uncleanly unmounted UBIFS partition on NOR
flash since mtd-writesize is 1 byte for NOR flash. The
MTD CFI driver however often performs writing multiple
bytes in
On Wed, Jan 19, 2011 at 5:04 PM, Peter Tyser pty...@xes-inc.com wrote:
Hi Tom,
Some last minutes nits:
It looks like some of the new functions can be declared statically.
It'd be nice to do so where possible.
Which functions, Peter? Please point them out specifically, thanks.
snip
---
Graeme,
On Wed, Jan 19, 2011 at 5:20 PM, Graeme Russ graeme.r...@gmail.com wrote:
On Thu, Jan 20, 2011 at 8:19 AM, Tom Warren twarren.nvi...@gmail.com wrote:
+
+/*
+ * Routine: uart_clock_init
+ * Description: init the PLL and clock for the UART in uart_num
+ */
+void uart_clock_init(int
Wolfgang,
On Thu, Jan 20, 2011 at 1:40 AM, Wolfgang Denk w...@denx.de wrote:
Dear Tom Warren,
In message 1295471986-2395-2-git-send-email-twar...@nvidia.com you wrote:
Signed-off-by: Tom Warren twar...@nvidia.com
checkpatch.pl reports:
total: 6 errors, 12 warnings, 1155 lines
On Thu, 2011-01-20 at 09:41 -0700, Tom Warren wrote:
On Wed, Jan 19, 2011 at 5:04 PM, Peter Tyser pty...@xes-inc.com wrote:
Hi Tom,
Some last minutes nits:
It looks like some of the new functions can be declared statically.
It'd be nice to do so where possible.
Which functions, Peter?
This driver accesses to processor's register
via __REG macros, that are removed (or are planned
to be removed) and replaced by C structures.
This patches replaces all occurrencies of __REG macros.
Signed-off-by: Stefano Babic sba...@denx.de
CC: Heiko Schocher h...@denx.de
---
Changes:
-
There is sporadic failures when more as one I2C slave
is on the bus and the processor tries to communicate
with more as one slave.
The problem was seen on a mx35pdk (two I2C slaves,
PMIC controller and CAN/RTC chip).
The current driver uses the IIF bit in the status register
to check if the bus
From: Anatolij Gustschin ag...@denx.de
We need to shift only one time in each cycle in the swapping loop
for unaligned tx case. Currently two byte shift operations are
performed in each loop cycle causing zero gaps in the transmited
data, so not all data scheduled for transmition is actually
The patch adds suupport for the Freescale's mx35pdk board
(known as well as mx35_3stack).
The board boots from the NOR flash. Following devices
are supported:
- two ethernet devices (FEC and SMC911x on debug board)
- I2C
- PMIC (MC13892) via I2C interface
- UART
- NOR flash (64MB)
- NAND
The patch adds suupport for the Freescale's mx35pdk board
(known as well as mx35_3stack).
The board boots from the NOR flash. Following devices
are supported:
- two ethernet devices (FEC and SMC911x on debug board)
- I2C
- PMIC (MC13892) via I2C interface
- UART
- NOR flash (64MB)
- NAND
Le 18/01/2011 08:27, Andreas Bießmann a écrit :
Dear Jason Liu,
Dear Albert Aribaud,
Am 17.01.2011 um 20:54 schrieb Jason Liu:
Hi, Albert,
2010/12/23 Jason Liur64...@freescale.com:
Remove the useless code from start.S
Signed-off-by: Jason Liur64...@freescale.com
---
Changes for v2:
Le 19/12/2010 09:45, Heiko Schocher a écrit :
Hello Wolfgang,
Wolfgang Denk wrote:
Dear Albert Heiko,
In message4d01e031.3090...@free.fr you wrote:
Reuse the gd-tbl value for timestamp and add gd-lastinc for lastinc bss
values in the arm1136 timer driver for mx31 and omap24xx
The usage
I'm trying to build Kumar's repository, and I'm getting this error. Is anyone
else seeing this?
$ make P4080DS_config
awk '(NF $1 !~ /^#/) { print $1 : $1 _config; $(MAKE) }' boards.cfg
.boards.depend
Configuring for P4080DS board...
$ make -s
powerpc-linux-gnu-ld: Warning:
Le 10/12/2010 10:33, Heiko Schocher a écrit :
Reuse the gd-tbl value for timestamp and add gd-lastinc for lastinc bss
values in the arm926ejs timers implementation.
The usage of bss values in drivers before initialisation of bss is forbidden.
In that special case some data in .rel.dyn gets
Le 20/01/2011 21:43, Albert ARIBAUD a écrit :
Le 10/12/2010 10:33, Heiko Schocher a écrit :
Reuse the gd-tbl value for timestamp and add gd-lastinc for lastinc bss
values in the arm926ejs timers implementation.
The usage of bss values in drivers before initialisation of bss is forbidden.
In
On Thu, 20 Jan 2011 14:37:35 -0600
Timur Tabi ti...@freescale.com wrote:
I'm trying to build Kumar's repository, and I'm getting this error. Is anyone
else seeing this?
$ make P4080DS_config
awk '(NF $1 !~ /^#/) { print $1 : $1 _config; $(MAKE) }' boards.cfg
.boards.depend
Configuring
Le 18/12/2010 13:08, Jens Scharsig a écrit :
* remove LED initialization in front of relocation and bss init
Signed-off-by: Jens Scharsigjs_at...@scharsoft.de
---
* prevents run C function on an uninitialized environment
arch/arm/cpu/arm920t/start.S |3 ---
1 files changed, 0
Scott Wood wrote:
I'm not sure what you mean by Kumar's
repository (u-boot-mpc85xx.git?),
Yes.
but there hasn't been a
lib_powerpc for a while now.
Then what's this:
On Thu, 20 Jan 2011 14:59:02 -0600
Timur Tabi ti...@freescale.com wrote:
Scott Wood wrote:
I'm not sure what you mean by Kumar's
repository (u-boot-mpc85xx.git?),
Yes.
but there hasn't been a
lib_powerpc for a while now.
Then what's this:
Le 18/01/2011 11:20, Stefano Babic a écrit :
On 01/18/2011 10:24 AM, Wolfgang Denk wrote:
It is not too late. I will not pull this into mainline as is. You
can rebase your tree.
No problem on my side. Albert should also drop this patch, because it is
already merged into u-boot-arm. I will
Le 20/01/2011 12:27, Mohammed Afzal a écrit :
DM365 DM644X builds 'davinci_emac_mii_mode_sel()',
which uses 'davinci_syscfg_regs' macro, and the
macro is valid iff CONFIG_SOC_DA8XX is defined.
Fix: Before compiling 'davinci_emac_mii_mode_sel()', make sure that
CONFIG_SOC_DA8XX is defined.
Dear Tom Warren,
In message AANLkTi=yMzEztQ5p=dosj4ukkfvx8gmrzoaxjbwbj...@mail.gmail.com you
wrote:
...
Are all these uart functions board-specific? They look more
CPU-specific. If that's the case they should be moved somewhere in
arch/arm/*. Other boards that use the Tegra2 don't want
Dear Tom Warren,
In message AANLkTimcTq74=jz0hjcmsumye3tf2zeuy9r9f7qvt...@mail.gmail.com you
wrote:
I'll take a look at the ARM asm code generated, but you are probably right.
But shouldn't the compiler have complained if I wasn't passing the
struct address?
I'm surprised about this, too.
Dear Tom Warren,
In message AANLkTi=ujj5teeyqq8q4rw7qaicjvav4xs83pdcxh...@mail.gmail.com you
wrote:
I run checkpatch.pl (v 0.31) on every patch before I submit it, and I
did see 12 warnings but
no errors. The warnings were minor - new typedefs and volatile
structs. Could you please
Seems this is already fixed by commit
51861a953aa10fde5c861ca022f0833f326e3041 which is in u-boot-ti/master,
right?
Yes that is correct I believe. Before my vacation I was getting the entire
Davinci series of SOCs compiling as they were broken for various reasons and
this is one of the
I now have some more information on the performance issue. It appears to be
filesystem related. If I format the drive as FAT32 I am getting a transfer
rate of approximately 10MB/second. However, if I format it as ext3 I am seeing
a transfer rate of only 101KB/second! The only difference is
On Fri, Jan 21, 2011 at 9:50 AM, Wolfgang Denk w...@denx.de wrote:
Dear Tom Warren,
In message AANLkTimcTq74=jz0hjcmsumye3tf2zeuy9r9f7qvt...@mail.gmail.com you
wrote:
I'll take a look at the ARM asm code generated, but you are probably right.
But shouldn't the compiler have complained if I
On Jan 20, 2011, at 3:06 PM, Scott Wood wrote:
On Thu, 20 Jan 2011 14:59:02 -0600
Timur Tabi ti...@freescale.com wrote:
Scott Wood wrote:
I'm not sure what you mean by Kumar's
repository (u-boot-mpc85xx.git?),
Yes.
but there hasn't been a
lib_powerpc for a while now.
Then
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Move serial driver to separate patch
common/serial.c |3 ++-
include/serial.h |3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/common/serial.c b/common/serial.c
index 051ae4e..8ebf9a5 100644
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Coding style cleanup
- Move serial driver changes to separate patch
- Use board/nvidia instead of board/tegra
- Remove TRUE/FALSE defines
- Use standard NS16550 registers/bit defines in UART
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Use board/nvidia/ instead of /board/tegra
- Change nv-common.h config file to tegra2-common.h
MAINTAINERS |4 +
board/nvidia/harmony/Makefile | 50
boards.cfg
Signed-off-by: Tom Warren twar...@nvidia.com
---
Changes for V2:
- Remove mach-types.h change; wait for ARM kernel sync-up
- Use board/nvidia instead of board/tegra
MAINTAINERS|1 +
board/nvidia/seaboard/Makefile | 50
1 - 100 of 116 matches
Mail list logo
