I'm creating a SPL u-boot image for our board. In the file
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c is the setup for
the L2 cache as SRAM. In the end is a loop that fills the
cache with 0 (512KB in this case).
1. Why is the access byte-wise and not dword-wise? This
is only for mpc85xx and
- Original Message -
From: Prafulla Wadaskar prafu...@marvell.com
To: Julian Pidancet julian.pidan...@citrix.com, u-boot@lists.denx.de
Cc: tanmay upadhyay tanmay.upadh...@einfochips.com, Prabhanjan Sarnaik
sarn...@marvell.com, Ashish Karkare akark...@marvell.com
Sent: Wednesday,
- Original Message -
From: Julian Pidancet julian.pidan...@citrix.com
To: u-boot@lists.denx.de
Cc: tanmay upadhyay tanmay.upadh...@einfochips.com, prafu...@marvell.com
Sent: Tuesday, February 8, 2011 11:50:54 PM
Subject: [PATCH] Kirkwood: Add support for OpenRD-Client
-Original Message-
From: Tanmay Upadhyay - Embedded [mailto:tanmay.upadh...@einfochips.com]
Sent: Wednesday, February 09, 2011 1:18 AM
To: Prafulla Wadaskar
Cc: Prabhanjan Sarnaik; Ashish Karkare; Julian Pidancet; u-
b...@lists.denx.de
Subject: Re: [PATCH] Kirkwood: Add support
-Original Message-
From: Lei Wen [mailto:lei...@marvell.com]
Sent: Friday, January 28, 2011 1:19 AM
To: Albert ARIBAUD; Wolfgang Denk; u-boot@lists.denx.de; Prafulla
Wadaskar; Yu Tang; Ashish Karkare; Prabhanjan Sarnaik; Lei Wen
Subject: [PATCH V8 0/5] Add Pantheon soc and dkb
Hi Albert/Wolfgang
Please pull
The following changes since commit 97a85b223ab316d11f3a374fecc5d449a1c8a694:
Scott Wood (1):
powerpc/nand spl: link libgcc
are available in the git repository at:
u-boot-marvell.git on next branch.
Lei Wen (5):
mv: seperate kirkwood and armada
Hi Aaron
Am 07.02.2011 23:02, schrieb Aaron Williams:
5. Fix for Micron NAND flash MT29F32G08CBABA which erroneously reports a 16-
bit bus when it has an 8-bit BUS.
Can you send that patch separately? I have a iMX25 board here with the
2GiB version of that chip which also reports a 16 bit bus
Dear Tanmay Upadhyay - Embedded,
In message 726556893.71716.1297242968960.javamail.r...@ahm.einfochips.com you
wrote:
--===1012086174==
Content-Type: multipart/alternative;
boundary==_Part_71715_1073465620.1297242968958
--=_Part_71715_1073465620.1297242968958
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/freescale/mx31pdk/mx31pdk.c | 10 -
include/configs/mx31pdk.h |6 +++
nand_spl/board/freescale/mx31pdk/u-boot.lds | 59 +++---
3 files changed, 66 insertions(+), 9
Use board_early_init_f so that the full boot log output can be displayed.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/freescale/mx31pdk/mx31pdk.c |7 ++-
include/configs/mx31pdk.h |1 +
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Signed-off-by: Magnus Lilja lilja.mag...@gmail.com
---
arch/arm/cpu/arm1136/start.S | 16
1 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index
2011/2/6 Kim Phillips kim.phill...@freescale.com:
On Wed, 19 Jan 2011 19:50:47 +0800
Leo Liu liucai@gmail.com wrote:
This patch fix a problem for the pcie enumeration when the mpc83xx pcie
controller is
connected with switch or we use both of the two pcie controller.
Signed-off-by:
Name.
Location...
Tell...___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Hi Albert,
On 2/8/2011 6:50 PM, Albert ARIBAUD wrote:
Le 08/02/2011 21:18, stefano babic a écrit :
Am 08.02.2011 20:26, schrieb Magnus Lilja:
Patch reposted as a separate mail a couple of minutes ago.
As I mention in the patch I think Fabio's patch has to be applied first.
I think your
Hi
Since 2011.03-rc1, the eNET / x86 build fails with:
[...]
ld --cref -pic --emit-relocs -Bsymbolic -Bsymbolic-functions --cref -pic
--emit-relocs -Bsymbolic -Bsymbolic-functions -r -o
On Wednesday 09 February 2011 03:47 PM, Wolfgang Denk wrote:
Dear Tanmay Upadhyay - Embedded,
In message726556893.71716.1297242968960.javamail.r...@ahm.einfochips.com
you wrote:
--===1012086174==
Content-Type: multipart/alternative;
On Wednesday, February 9, 2011, Loïc Minier l...@dooz.org wrote:
Hi
Since 2011.03-rc1, the eNET / x86 build fails with:
[...]
ld --cref -pic --emit-relocs -Bsymbolic -Bsymbolic-functions --cref -pic
--emit-relocs -Bsymbolic -Bsymbolic-functions -r -o
On Wed, Feb 09, 2011, Graeme Russ wrote:
This has been fixed in the latest x86 patch series sent to the list
Great! I had flagged this patch series, but for some reason I thought
this had been merged already. I had checked the u-boot-x86.git tree
before reporting this to the mailing-list,
FTR, the patch I picked for the Debian package was:
x86: Align config.mk and linker scripts with other arches
--
Loïc Minier
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
This patch fixes following warning message:
---8---
cmd_bdinfo.c:458: warning: initialization from incompatible pointer type
---8---
There was a prototype change in 54841ab50c20d6fa6c9cc3eb826989da3a22d934 for
argv[] pointer type to const. This change was not made for AVR32 cause this
code came
Signed-off-by: Wolfgang Denk w...@denx.de
Cc: Anatolij Gustschin ag...@denx.de
---
common/cmd_bmp.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c
index f2a48f7..23fc82f 100644
--- a/common/cmd_bmp.c
+++ b/common/cmd_bmp.c
@@ -79,7
This patch series make avr32 boards compile again. They where broken by
partial linking changes.
Additionally two warnings fixed. MAKEALL complained broken boards cause of
these warnings.
In my opinion these changes are fixes and should go into v2011.03. Some more
changes will follow for
This patch fixes following error:
---8---
avr32-linux-ld: --gc-sections and -r may not be used together
---8---
Since 8aba9dceebb14144e07d19593111ee3a999c37fc all avr32 boards are broken due
to linking error as seen above.
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
This patch fixes warnings in MAKEALL for avr32:
---8---
cmd_nvedit.c: In function 'do_env_export':
cmd_nvedit.c:663: warning: format '%zX' expects type 'size_t', but argument 3
has type 'ssize_t'
---8---
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
common/cmd_nvedit.c |4
Dear Andreas Bießmann,
This patch series make avr32 boards compile again. They where broken by
partial linking changes.
Additionally two warnings fixed. MAKEALL complained broken boards cause of
these warnings.
In my opinion these changes are fixes and should go into v2011.03. Some more
This patch move the atstk100x linker script to $(CPUDIR) and delete other
pure copies of this file in each board directory.
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
arch/avr32/config.mk |2 +
.../atmel/atstk1000 = arch/avr32/cpu}/u-boot.lds |
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
include/configs/mimc200.h | 56 ++--
1 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h
index f004ec8..66b9477 100644
---
This series do some cleanup all avr32 boards. This series is on top of 'Get
AVR32 boards working with partial linking' rebased to
u-boot-atmel/rework110202.
In summary the board specific config.mk and u-boot.lds files are deleted in
favor of a version at architecture level. Theses files had all
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
include/configs/atstk1004.h | 42 +-
1 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index 344ba8f..a225395 100644
---
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
board/atmel/atngw100/config.mk |1 -
include/configs/atngw100.h |1 +
2 files changed, 1 insertions(+), 1 deletions(-)
delete mode 100644 board/atmel/atngw100/config.mk
diff --git a/board/atmel/atngw100/config.mk
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
include/configs/hammerhead.h | 48 +-
1 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h
index 1f20fff..5a2d146 100644
This patch removes PLATFORM_RELFLAGS from board specific config.mk files and
define them in arch specific config.mk file.
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
arch/avr32/config.mk |2 ++
board/atmel/atngw100/config.mk |1 -
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
board/miromico/hammerhead/config.mk |1 -
include/configs/hammerhead.h|1 +
2 files changed, 1 insertions(+), 1 deletions(-)
delete mode 100644 board/miromico/hammerhead/config.mk
diff --git
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
include/configs/atngw100.h | 54 ++--
1 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index a93ba8b..70f1e8a 100644
---
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
include/configs/atstk1003.h | 42 +-
1 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index 85337bf..9cc5cb9 100644
---
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
include/configs/atstk1006.h | 48 +-
1 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
index e8553fc..d681929 100644
---
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
include/configs/atstk1002.h | 48 +-
1 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index ba1b56c..997e9dd 100644
---
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
include/configs/favr-32-ezkit.h | 46 +++---
1 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h
index e723ad1..f364dad
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
board/atmel/atstk1000/config.mk |1 -
include/configs/atstk1002.h |1 +
include/configs/atstk1003.h |1 +
include/configs/atstk1004.h |1 +
include/configs/atstk1006.h |1 +
5 files changed, 4
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
board/earthlcd/favr-32-ezkit/config.mk |1 -
include/configs/favr-32-ezkit.h|1 +
2 files changed, 1 insertions(+), 1 deletions(-)
delete mode 100644 board/earthlcd/favr-32-ezkit/config.mk
diff --git
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
board/mimc/mimc200/config.mk |1 -
include/configs/mimc200.h|1 +
2 files changed, 1 insertions(+), 1 deletions(-)
delete mode 100644 board/mimc/mimc200/config.mk
diff --git a/board/mimc/mimc200/config.mk
Hello,
I'm using u-boot to boot a Linux-based device.
I created some MTD partitions for my NOR and NAND flashes.
Here is the configuration:
device nor0 NOR, # parts = 4
#: namesizeoffset mask_flags
0: U-Boot 0x0008
Hello,
I'm using U-Boot with a NOR and a NAND Flash.
U-Boot is stored into the NOR flash.
The NOR flash is setup as :
0xA000 - 0xA008 - 512k - 8 sectors - reserved for U-Boot.bin
0xA008 - 0xA00A - 128k - 2 sectors - reserved for U-Boot
environment
If I use the command `flinfo`
Hello,
thanks for your reply.
I'm running u-boot 1.3.1. I got it from STLinux.
I will try to set CONFIG_JFFS2.
But does it mean it will erase the partition using JFFS2 ?
Will it support to read and write the environment settings with this
file format ?
Alex
On 02/09/2011 05:10 PM, Alexander
On Feb 9, 2011, at 2:06 AM, Fabian Cenedese wrote:
I'm creating a SPL u-boot image for our board. In the file
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c is the setup for
the L2 cache as SRAM. In the end is a loop that fills the
cache with 0 (512KB in this case).
1. Why is the access
Hello,
On Wednesday 09 February 2011, 16:52:35 Alexandre Gambier wrote:
I'm using u-boot to boot a Linux-based device.
Which version og u-boot are you running?
I created some MTD partitions for my NOR and NAND flashes.
Here is the configuration:
device nor0 NOR, # parts = 4
#: name
Hello,
On Wednesday 09 February 2011, 17:16:37 Alexandre Gambier wrote:
thanks for your reply.
I'm running u-boot 1.3.1. I got it from STLinux.
ouch, that's pretty old.
I will try to set CONFIG_JFFS2.
But does it mean it will erase the partition using JFFS2 ?
No, the feature depended on
Dear Alexandre Gambier,
In message 4d52ba80.4060...@ftemaximal.fr you wrote:
Hello,
I'm using U-Boot with a NOR and a NAND Flash.
U-Boot is stored into the NOR flash.
The NOR flash is setup as :
0xA000 - 0xA008 - 512k - 8 sectors - reserved for U-Boot.bin
0xA008 -
Dear Alexandre Gambier,
In message 4d52b843.5010...@ftemaximal.fr you wrote:
I'm using u-boot to boot a Linux-based device.
I created some MTD partitions for my NOR and NAND flashes.
Here is the configuration:
device nor0 NOR, # parts = 4
#: namesize
The mac id command is used to initialize the EEPROM data to a specific
format, but it was not updating the CRC. This didn't cause any real
problems, because writing the data to the EEPROM will always update the
CRC anyway, but it did result in a bogus CRC warning.
Signed-off-by: Timur Tabi
Dear Stefan Roese,
In message 201102071138.38372...@denx.de you wrote:
Hi Wolfgang
please pull the following patch (initial version posted before the
merge-window closed):
The following changes since commit 42d44f631c4e8e5359775bdc098f2fffde4e5c05:
Prepare v2011.03-rc1 (2011-02-02
Dear Scott McNutt,
In message 4d514868.6060...@psyent.com you wrote:
Dear Wolfgang,
The following changes since commit 8d4addc3c3fe1a9ea160a5a1a20a1f934ff3fe97:
Wolfgang Denk (1):
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
are available in the git repository
The following changes since commit 8d4addc3c3fe1a9ea160a5a1a20a1f934ff3fe97:
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx (2011-02-06
22:41:53 +0100)
are available in the git repository at:
git://git.denx.de/u-boot-nand-flash.git master
Scott Wood (1):
NAND: env:
On Thursday, February 10, 2011, Loïc Minier l...@dooz.org wrote:
On Wed, Feb 09, 2011, Graeme Russ wrote:
This has been fixed in the latest x86 patch series sent to the list
Great! I had flagged this patch series, but for some reason I thought
this had been merged already. I had checked
We have a system with a P1022 connected to a 5461S in SGMII mode.
In order to make it work in SGMII mode, I set TBI ANA to 0x4001 as per
AN3869. Note that those bit are described as reserved in the P1022 doc
that I have.
I was then able to transfer data at 100/1000 (10 not tested).
As per
Correction: P1013
On 09/02/11 20:21, Renaud Barbier wrote:
We have a system with a P1022 connected to a 5461S in SGMII mode.
In order to make it work in SGMII mode, I set TBI ANA to 0x4001 as per
AN3869. Note that those bit are described as reserved in the P1022 doc
that I have.
I was then
Dear Scott Wood,
In message 20110209195903.ga10...@schlenkerla.am.freescale.net you wrote:
The following changes since commit 8d4addc3c3fe1a9ea160a5a1a20a1f934ff3fe97:
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx (2011-02-06
22:41:53 +0100)
are available in the git
Hello Wolfgang,
On Wed, 9 Feb 2011 15:11:10 +0100
Wolfgang Denk w...@denx.de wrote:
Signed-off-by: Wolfgang Denk w...@denx.de
Cc: Anatolij Gustschin ag...@denx.de
---
common/cmd_bmp.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
Applied to u-boot-video/master. Thanks.
Hallo Wolfgang,
The following changes since commit 494a7d215bfba17f1a94736df40c332c8713c30e:
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash (2011-02-09
21:22:58 +0100)
are available in the git repository at:
git://git.denx.de/u-boot-video.git master
Wolfgang Denk (1):
Le 09/02/2011 10:49, Prafulla Wadaskar a écrit :
Hi Albert/Wolfgang
Please pull
The following changes since commit 97a85b223ab316d11f3a374fecc5d449a1c8a694:
Scott Wood (1):
powerpc/nand spl: link libgcc
are available in the git repository at:
u-boot-marvell.git on next
On Wed, Feb 9, 2011 at 1:40 PM, Timur Tabi ti...@freescale.com wrote:
The mac id command is used to initialize the EEPROM data to a specific
format, but it was not updating the CRC. This didn't cause any real
problems, because writing the data to the EEPROM will always update the
CRC anyway,
From hints by Wolfgang, this patch adds the ability to handle +len
argument for spi flash erase, which will round up the length to the
nearest [sector|page|block]_size.
This is done by adding a new member to
struct spi_flash::u32 block_size
The name 'block_size' is chosen to mean:
the smallest
On Wed, 9 Feb 2011 07:40:44 +0100
Albert ARIBAUD albert.arib...@free.fr wrote:
Le 09/02/2011 07:19, Chris Moore a écrit :
I also noticed this in some of my (rare) posts.
I am using TB 3.1.5.
I am too ashamed to admit my OS ;-)
A nonsense test case written with correct spacing: a = (b
On Thu, Feb 10, 2011 at 12:58 AM, Loïc Minier l...@dooz.org wrote:
FTR, the patch I picked for the Debian package was:
x86: Align config.mk and linker scripts with other arches
Can you add your acked-by
Thanks,
Graeme
___
U-Boot mailing list
Hi Renaud,
On Wed, 2011-02-09 at 20:21 +, Renaud Barbier wrote:
We have a system with a P1022 connected to a 5461S in SGMII mode.
In order to make it work in SGMII mode, I set TBI ANA to 0x4001 as per
AN3869. Note that those bit are described as reserved in the P1022 doc
that I have.
Add the 'pixis_reset dump' command, which displays the contents of the PIXIS
registers. This command is only available if DEBUG is defined.
Signed-off-by: Timur Tabi ti...@freescale.com
---
board/freescale/common/ngpixis.c | 58 ++
1 files changed, 58
Hello all,
I was wondering if anyone has implemented a working NAND biterr
command for U-Boot (presently running a rather customized variant of
1.3.3).
I'm trying to test some automatic NAND error recovery code, and this
seemed like an appropriate way to verify it.
I found an older
Hi,
I'm using the 2010.12 u-boot source code. I use a JFFS2 partition on a
NAND flash to store the kernel image as well as an FGPA images for my
platform. I also mount this partition inside the kernel because I need
the ability to overwrite the contents during a field-upgrade of the
embedded
On Tuesday, February 08, 2011 10:08:12 pm Albert ARIBAUD wrote:
Hi Aaron,
Le 08/02/2011 22:58, Aaron Williams a écrit :
Hi,
I'm trying to compile AHCI support but I'm running into a lot of
problems. It looks like AHCI is based off of SCSI whereas other SATA
drivers appear not to be.
I got it working, thanks to the patch. I had to make a few minor patches for
our platform to map pointers to 64-bit physical addresses and a wrapper to
access the PCI BAR address space and it works well.
-Aaron
On Wednesday, February 02, 2011 10:05:52 pm Aaron Williams wrote:
Disregard my
Hi,
When writing a JFFS2 image to NAND flash, any bad blocks in the BBT is
skipped. However, while scanning a JFFS2 partition, bad blocks are not
skipped. Is this intended or am I mis-configuring u-boot somehow?
I'm using the 2010.12 u-boot source code. The BBT table for my system
Dear Wolfgang,
Since the Linux Driver still under clean up, I will modify the copyright
statement
of this driver for u-boot and send patch v3.
I have modified copyright statement for this patch ftwdt010_wdt v3
http://patchwork.ozlabs.org/patch/77564/
and send patch v4
Hi there
How are you doing over there?! 2011 off to a good start?!
We're pleased to inform you that your organisation has been invited to
participate in the exclusive Art of England Magazine, April 2011 edition, copy
deadline for which is almost here.
Now seven years old, the Art of England
On Jan 29, 2011, at 5:20 PM, Kumar Gala wrote:
From: Jerry Huang chang-ming.hu...@freescale.com
We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 GPIO9
respectively).
We enable EXT2, FAT, and parition support for both MMC USB configs.
Signed-off-by: Jerry Huang
On Jan 29, 2011, at 5:21 PM, Kumar Gala wrote:
From: Li Yang le...@freescale.com
Read MAC address from EEPROM. Add hwconfig settings.
Modified the default othbootargs to include the cache-sram-size
parameter. This parameter is needed as the L2 as SRAM is ON by
default in the P2020RDB
On Jan 31, 2011, at 4:15 PM, Kumar Gala wrote:
We've been utilizing board_lmb_reserve to reserve the boot page for MP
systems. We can just move this into arch_lmb_reserve for 85xx 86xx
systems rather than duplicating in each board port.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
On Jan 31, 2011, at 10:53 PM, Kumar Gala wrote:
Move the include of mpc85xx/u-boot-nand.lds to utilize
CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Use $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds so we should work in O=
*
On Jan 31, 2011, at 10:54 PM, Kumar Gala wrote:
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and
On Feb 4, 2011, at 2:44 PM, Kumar Gala wrote:
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing. The only variations are in how many
controllers or DIMMs per controller exist. To make this work we
standardize on the names of the
On Jan 31, 2011, at 11:16 PM, Kumar Gala wrote:
Move some processor specific QE defines into config_mpc85xx.h and use
QE_MURAM_SIZE to cleanup some ifdef mess in the QE immap struct.
Also fixed up some comment style issues in immap_qe.h
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
On Feb 2, 2011, at 12:21 PM, Kumar Gala wrote:
We can simplify some cpu/SoC level initialization by moving it to be
after the environment and non-volatile storage is setup as there might
be dependancies on such things in various boot configurations.
For example for FSL SoC's with QE if we
On Feb 3, 2011, at 8:22 PM, Kumar Gala wrote:
Slim down NAND SPL build a bit as we don't need read_tlbcam_entry.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/cpu/mpc85xx/tlb.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
applied to 85xx next
- k
On Feb 4, 2011, at 2:41 PM, Kumar Gala wrote:
From: Roy Zang tie-fei.z...@freescale.com
Add P1023 (dual core) P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list
(fixed issue with P1013 not being sorted correctly).
* Added
On Feb 4, 2011, at 2:41 PM, Kumar Gala wrote:
From: Haiying Wang haiying.w...@freescale.com
There are some differences between CoreNet (P2040, P3041, P5020, P4080)
and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
the memory maps.
* Rename various immap defines to
On Feb 4, 2011, at 3:57 PM, York Sun wrote:
Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.
Signed-off-by: York Sun york...@freescale.com
On Feb 4, 2011, at 3:58 PM, York Sun wrote:
Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers
embedded in SPD.
Signed-off-by: York Sun york...@freescale.com
---
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c| 11 +++
1 files changed, 7
On Feb 9, 2011, at 3:08 PM, Timur Tabi wrote:
On Wed, Feb 9, 2011 at 1:40 PM, Timur Tabi ti...@freescale.com wrote:
The mac id command is used to initialize the EEPROM data to a specific
format, but it was not updating the CRC. This didn't cause any real
problems, because writing the data
On Feb 7, 2011, at 3:39 AM, Poonam Aggrwal wrote:
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Cc: York Sun york...@freescale.com
---
P1014 processor supports maximum 16bit DDR data width.
Based of: git://git.am.freescale.net/mirrors/u-boot.git (branch, master)
On Feb 7, 2011, at 3:38 AM, Poonam Aggrwal wrote:
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
Based of: git://git.am.freescale.net/mirrors/u-boot.git (branch, master)
include/configs/P1_P2_RDB.h |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
applied to
From: Priyanka Jain priyanka.j...@freescale.com
Board EEPROM is used to read/save Ethernet MAC addresses.
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
include/configs/P1_P2_RDB.h |3 +--
1 files changed, 1 insertions(+), 2
We should have been defining the actual board name in the options, not
the processor. Fix this for P1011RDB, P1020RDB, P2010RDB, and P2020RDB.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
boards.cfg | 26 +-
1 files changed, 13 insertions(+), 13 deletions(-)
On Feb 8, 2011, at 2:51 PM, Haiying Wang wrote:
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth
mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
On Feb 7, 2011, at 3:14 PM, haiying.w...@freescale.com
haiying.w...@freescale.com wrote:
From: Haiying Wang haiying.w...@freescale.com
In the case the QE's microcode is stored in nand flash, we need to load it
from
NAND flash to ddr first then the qe_init can get the ucode correctly.
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because
On Jan 29, 2011, at 5:29 PM, Kumar Gala wrote:
From: Mingkai Hu mingkai...@freescale.com
On some boards the environment may not be located at a fixed address in
the MMC/SDHC card. This allows those boards to implement their own
means to report what address the environment is located at.
Hi,
Le 09/02/2011 22:17, Scott Wood a écrit :
On Wed, 9 Feb 2011 07:40:44 +0100
Albert ARIBAUDalbert.arib...@free.fr wrote:
Le 09/02/2011 07:19, Chris Moore a écrit :
I also noticed this in some of my (rare) posts.
I am using TB 3.1.5.
I am too ashamed to admit my OS ;-)
A nonsense test
On Feb 4, 2011, at 2:42 PM, Kumar Gala wrote:
From: Prabhakar Kushwaha prabha...@freescale.com
FSL PCIe controller v2.1:
- New MSI inbound window
- Same Inbound windows address as PCIe controller v1.x
Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
On Feb 4, 2011, at 3:14 PM, Kumar Gala wrote:
If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW
entries consider them good and mark them used.
In the NAND SPL case we skip re-initializing based on the law_table
since the SPL phase already did that.
Signed-off-by:
Hi,
Me again.
Le 10/02/2011 07:16, Chris Moore a écrit :
Hi,
Le 09/02/2011 22:17, Scott Wood a écrit :
On Wed, 9 Feb 2011 07:40:44 +0100
Albert ARIBAUDalbert.arib...@free.fr wrote:
Le 09/02/2011 07:19, Chris Moore a écrit :
I also noticed this in some of my (rare) posts.
I am using TB
Dear Chris Moore,
Hi,
Me again.
Le 10/02/2011 07:16, Chris Moore a écrit :
Hi,
Le 09/02/2011 22:17, Scott Wood a écrit :
On Wed, 9 Feb 2011 07:40:44 +0100
Albert ARIBAUDalbert.arib...@free.frwrote:
Le 09/02/2011 07:19, Chris Moore a écrit :
I also noticed this in some of my (rare)
1 - 100 of 102 matches
Mail list logo
