Device tree support is required for working USB host support, which in
turn enables ethernet support.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
Acked-by: Stephen Warren swar...@wwwdotorg.org
---
Changes in v3:
- none
Changes in v2:
- drop chosen and sdhci@c8000600 nodes from
Device tree support is required for working USB host support, which in
turn enables ethernet support.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
Acked-by: Stephen Warren swar...@wwwdotorg.org
---
Changes in v3:
- none
Changes in v2:
- drop chosen and sdhci@c8000600 nodes from
The PI4 GPIO is used on Tamonten to reset carrier board peripherals.
Power sequencing hardware on the carrier pulls the reset low before
powering up the Tegra, and the CPU is supposed to signal readiness,
and therefore bring peripherals out of reset by pulling PI4 high.
Signed-off-by: Thierry
GPIO PI6 can be used to obtain the write-protect status of an SD card
inserted into the SD slot.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
Acked-by: Stephen Warren swar...@wwwdotorg.org
---
Changes in v3:
- none
Changes in v2:
- new patch
This commit uses the common Tegra board implementation instead of
duplicating a lot of the code. In addition, the Plutux and Medcom
specific board files can be removed as the MMC/SD setup is common
among all Tamonten-based boards.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
The Tamonten Evaluation Carrier is an evaluation board for the Tamonten
processor board. More information is available here:
http://www.avionic-design.de/en/products/nvidia-tegra-tamonten-system-en/nvidia-tegra-tamonten-evboard-en.html
Signed-off-by: Thierry Reding
The new gpio_early_init() function, which does nothing by default, can
be overridden by boards to configure GPIOs at an early stage.
Signed-off-by: Thierry Reding thierry.red...@avionic-design.de
Acked-by: Stephen Warren swar...@wwwdotorg.org
---
Changes in v3:
- none
Changes in v2:
- new patch
This patch moves all bootcount implementations into a common
directory: drivers/bootcount. The generic bootcount driver
is now usable not only by powerpc platforms, but others as well.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Heiko Schocher h...@denx.de
Cc: Valentin Longchamp
Hi Albert!
I have collected all of the remaining ARM/SPEAr patches in my
staging repository. There are some dependencies between the
patches, so I also added the NOR, NAND and ethernet patches
in this pull request. The patches have the Acked-by from the
corresponding custodians (Joe for
On Sat, 28 Apr 2012 17:04:07 +0200
Anatolij Gustschin ag...@denx.de wrote:
Data cache flushing is required for frame buffer in RAM to fix the
distorted console text output. Currently this text distortion is
observed with cfb on beageboard and N900 when running with data
cache enabled.
Hi,
On Sat, 28 Apr 2012 19:26:47 +0200
Pali Rohár pali.ro...@gmail.com wrote:
Signed-off-by: Pali Rohár pali.ro...@gmail.com
---
drivers/video/cfb_console.c |3 +++
1 file changed, 3 insertions(+)
Applied to u-boot-video/master. Thanks!
Anatolij
Hello Wolfgang,
The following changes since commit 4398d55991eb3c2484a2a8e991d701e5d7a64874:
net: sh-eth: Add support Gigabit of SH7734 (2012-05-23 17:53:09 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-video.git master
Anatolij Gustschin (6):
Ping..
Thanks,
Sricharan
-Original Message-
From: R, Sricharan [mailto:r.sricha...@ti.com]
Sent: Tuesday, May 29, 2012 8:24 PM
To: U-Boot@lists.denx.de; albert.u.b...@aribaud.net
Cc: tr...@ti.com
Subject: Re: [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register
read before
Hello,
Please help me to configure u-boot in my NC600 board. I have reached near
to u-boot, but the kernel is not booting. After the kernel image upload via
serial boot mode it is giving no response. If the kernel image upload
become complete it is not giving any command line in the u-boot as
Hi,
On Fri, Jun 1, 2012 at 4:30 PM, Prabhakar Lad prabhakar@ti.com wrote:
From: Lad, Prabhakar prabhakar@ti.com
This patch adds support for MMC/SD on DA850/OMAP-L138.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Hi,
On Fri, Jun 1, 2012 at 3:48 PM, Prabhakar Lad prabhakar@ti.com wrote:
From: Rajashekhara, Sudhakar sudhakar@ti.com
According to DA850/OMAP-L138 schematics, GP2[6] line has to be driven
high for RMII mode to work. In RMII mode, SPI flash becomes un-usable.
But during testing it
Hi,
On Fri, Jun 1, 2012 at 4:30 PM, Prabhakar Lad prabhakar@ti.com wrote:
From: Lad, Prabhakar prabhakar@ti.com
This patch adds support for NAND SPL on DA850/OMAP-L138.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Hi,
On Fri, Jun 1, 2012 at 3:34 PM, Prabhakar Lad prabhakar@ti.com wrote:
From: Rajashekhara, Sudhakar sudhakar@ti.com
On DA850/OMAP-L138 it was observed that in RMII mode,
auto negotiation was not performed. This patch enables
auto negotiation in RMII mode. Without this patch, EMAC
On 06/05/2012 01:37 AM, Stefan Roese wrote:
This patch moves all bootcount implementations into a common
directory: drivers/bootcount. The generic bootcount driver
is now usable not only by powerpc platforms, but others as well.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Heiko Schocher
-Original Message-
From: Michael Walle [mailto:mich...@walle.cc]
Sent: 05 June 2012 16:39
To: Prafulla Wadaskar
Cc: u-boot@lists.denx.de; Joe Hershberger
Subject: Re: [PATCH v8 0/4] Kirkwood: add lschlv2 and lsxhl board
support
Hi Prafulla,
do you have any additional
-Original Message-
From: Valentin Longchamp [mailto:valentin.longch...@keymile.com]
Sent: 01 June 2012 17:01
To: Prafulla Wadaskar
Cc: u-boot@lists.denx.de; Valentin Longchamp; Holger Brunck
Subject: [PATCH v4 5/5] kw_spi: add weak functions
board_spi_claim/release_bus
This
-Original Message-
From: Prafulla Wadaskar
Sent: 05 June 2012 19:41
To: 'Michael Walle'
Cc: u-boot@lists.denx.de; Joe Hershberger
Subject: RE: [PATCH v8 0/4] Kirkwood: add lschlv2 and lsxhl board
support
-Original Message-
From: Michael Walle
Hi Prafulla,
On Jun 5, 2012, at 9:10 AM, Prafulla Wadaskar prafu...@marvell.com wrote:
-Original Message-
From: Michael Walle [mailto:mich...@walle.cc]
Sent: 05 June 2012 16:39
To: Prafulla Wadaskar
Cc: u-boot@lists.denx.de; Joe Hershberger
Subject: Re: [PATCH v8 0/4] Kirkwood:
Recent toolchains default to using the hardware feature for unaligned access on
ARM v7, rather than doing the software fallback. According to ARM this is safe
as all v7 implementations have to support this feature.
On 06/05/2012 12:35 AM, Xie Shaohui-B21989 wrote:
+++ b/board/freescale/corenet_ds/config.mk
@@ -0,0 +1,26 @@
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data for P4080, replace it when building image #for
+P3041DS or P5020DS.
+4c58 18185218
On 06/05/2012 11:47 AM, Lucas Stach wrote:
Recent toolchains default to using the hardware feature for unaligned access
on
ARM v7, rather than doing the software fallback. According to ARM this is safe
as all v7 implementations have to support this feature.
Hi Stephen,
Am Dienstag, den 05.06.2012, 12:42 -0600 schrieb Stephen Warren:
On 06/05/2012 11:47 AM, Lucas Stach wrote:
Recent toolchains default to using the hardware feature for unaligned
access on
ARM v7, rather than doing the software fallback. According to ARM this is
safe
as
Dear Zeyad A,
Hello,
Please help me to configure u-boot in my NC600 board.
What's this board? Is it supported mainline? What CPU does it have, what
version
of uboot etc?
I have reached near
to u-boot, but the kernel is not booting. After the kernel image upload via
serial boot mode it
Dear Sricharan R,
Ping..
+1
Thanks,
Sricharan
-Original Message-
From: R, Sricharan [mailto:r.sricha...@ti.com]
Sent: Tuesday, May 29, 2012 8:24 PM
To: U-Boot@lists.denx.de; albert.u.b...@aribaud.net
Cc: tr...@ti.com
Subject: Re: [U-Boot] [PATCH 1/5] ARM: cache: Move
Add support for specifying a differnt CPU for main u-boot and SPL
u-boot builds. This is done by adding an optional SPL CPU after the
main CPU in boards.cfg as follows:
normal_cpu:spl_cpu
This this case CPU will be set to normal_cpu during the main u-boot
build and spl_cpu during the SPL
This patch series fixes a long standing problem with the tegra20
u-boot build. Tegra20 contains an ARM7TDMI boot processor and a
Cortex A9 main processor. Prior to this patch series this was
accomplished by #ifdefing out any armv7 code from the early boot
sequence and creating a single binary
Add target for tegra20 u-boot image. This is a concatenation of tegra
spl and normal u-boot binaries.
Signed-off-by: Allen Martin amar...@nvidia.com
---
.gitignore |1 +
Makefile| 11 +++
board/nvidia/seaboard/config.mk |1 +
3
Don't use timer_init from tegra board.c. This comes out of arm720t
for the SPL build.
Signed-off-by: Allen Martin amar...@nvidia.com
---
board/nvidia/common/board.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index
Add support for tegra20 arm7 boot processor. This processor is used
to power on the Cortex A9 and transfer control to it.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/cpu/arm720t/cpu.c |2 +
arch/arm/cpu/arm720t/interrupts.c|4 +
Add SPL options to tegra20 config files and enable SPL build for
seaboard in boards.cfg
Signed-off-by: Allen Martin amar...@nvidia.com
---
boards.cfg |2 +-
include/configs/seaboard.h |6 +++
include/configs/tegra2-common.h | 17
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/cpu/armv7/{tegra2 = tegra20}/Makefile|0
arch/arm/cpu/armv7/{tegra2 = tegra20}/ap20.c |0
In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
Signed-off-by: Allen Martin amar...@nvidia.com
---
Makefile
This code is now included in the tegra20 SPL
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/cpu/armv7/start.S |2 -
arch/arm/cpu/tegra20-common/ap20.c | 262 +--
arch/arm/cpu/tegra20-common/board.c | 27 +---
Take a few SPL fixes from armv7 and apply them to arm720t:
-Use dummy exception handlers for SPL build
-Initialize relocation register r9 to 0 for the case of no relocation
-ifdef out interrupt handler code
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/cpu/arm720t/start.S | 13
These flags were necessary when building tegra20 as a single binary
that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support
is split into a separate SPL, this is no longer necessary.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/cpu/armv7/tegra20/config.mk |7
Allen,
-Original Message-
From: Allen Martin [mailto:amar...@nvidia.com]
Sent: Tuesday, June 05, 2012 2:20 PM
To: Tom Warren; swar...@wwwdotorg.org; s...@chromium.org
Cc: u-boot@lists.denx.de
Subject: [PATCH v2 0/10] split tegra20 arm7 code into separate SPL
This patch series
Changes:
v9:
- rebase to marvell custodian tree, merged with wolfgangs master
v8:
- revert CONFIG_RAND to old CONFIG_RANDOM_MACADDR
- the features CONFIG_BOOTP_RANDOM_DELAY and CONFIG_CMD_LINK_LOCAL pulls
rand.o implicitly now as suggested by Joe Hershberger
- remove reset_phy() from board
Replace rand() with the functions from lib/. The link-local network code
stores its own seed, derived from the MAC address. Thus making it
independent from calls to srand() in other modules.
Signed-off-by: Michael Walle mich...@walle.cc
Acked-by: Joe Hershberger joe.hershber...@ni.com
---
It's a PRNG using the simple and fast xorshift method.
Signed-off-by: Michael Walle mich...@walle.cc
Cc: Wolfgang Denk w...@denx.de
---
include/common.h |8
lib/Makefile |1 +
lib/rand.c | 48
3 files changed, 57
Add new function eth_random_enetaddr() to generate a locally administered
ethernet address.
Signed-off-by: Michael Walle mich...@walle.cc
Acked-by: Joe Hershberger joe.hershber...@gmail.com
---
include/net.h | 17 +
net/eth.c | 22 ++
2 files changed,
This patch adds support for both the Linkstation Live (LS-CHLv2) and
Linkstation Pro (LS-XHL) by Buffalo.
Signed-off-by: Michael Walle mich...@walle.cc
Cc: Prafulla Wadaskar prafu...@marvell.com
---
MAINTAINERS |5 +
board/buffalo/lsxl/Makefile | 44
Hi Prafulla,
Am Dienstag 05 Juni 2012, 23:33:13 schrieb Michael Walle:
Changes:
v9:
- rebase to marvell custodian tree, merged with wolfgangs master
[..snip..]
I had to merge your tree with wolfgangs master, because my second net patch
depends on the latest net patches by Joe.
So please
Signed-off-by: Simon Guinot simon.gui...@sequanux.org
---
No changes for v2.
include/configs/lacie_kw.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 5746fc4..4f8bc8f 100644
--- a/include/configs/lacie_kw.h
Signed-off-by: Simon Guinot simon.gui...@sequanux.org
---
No changes for v2.
include/configs/lacie_kw.h |4
1 file changed, 4 deletions(-)
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 6cbc752..5746fc4 100644
--- a/include/configs/lacie_kw.h
+++
This patch series provides bug fixes for LaCie devices (mostly for
Internet Space v2 and 2Big Network v2).
Changes for v2:
- Move bug fixes into a separate patch set.
Simon Guinot (3):
lacie_kw: fix SDRAM banks number for net2big_v2
lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
The command miiphy_read(name, 0xEE, 0xEE, (u16 *) devadr) always
returns 8 for the PHY address. It is the reset value for the PHY
Address Register. Obviously, this default value could be incorrect.
Moreover, as the PHY address is well known, there is no need to
auto-detect it.
Now, the PHY
Changes for v2:
- Move board support and feature into a separate patch set.
- Move mach-types update into a separate patch.
Simon Guinot (4):
lacie_kw: add support for EFI partitions
ARM: add netspace_mini_v2 to mach-types.h
ARM: add support for Network Space v2 Lite and Mini
ARM: add
Defines CONFIG_EFI_PARTITION for LaCie boards.
Additionally this patch defines CONFIG_DOS_PARTITION. Note that this
definition is implicit in mv_common.h when CONFIG_CMD_USB is enabled.
Signed-off-by: Simon Guinot simon.gui...@sequanux.org
---
No changes for v2.
include/configs/lacie_kw.h |
This patch adds the Network Space Mini v2 machine to mach-types.h.
Signed-off-by: Simon Guinot simon.gui...@sequanux.org
---
arch/arm/include/asm/mach-types.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/include/asm/mach-types.h
This patch adds support for the LaCie board d2 Network v2 which share
a lot of hardware caracteristics with the 2Big Network v2.
- CPU: Marvell 88F6281 1200Mhz
- SDRAM memory: 256MB DDR2 400Mhz
- 2 SATA ports: internal and eSATA
- Gigabit ethernet: PHY Marvell 88E1116R
- Flash memory: SPI NOR
This patch adds support for the LaCie boards Network Space v2 (Lite and
Mini). This two boards are derived from the Network Space v2 and a lot
of hardware caracteristics are shared.
- CPU: Marvell 88F6192 800Mhz
- SDRAM memory: 128MB DDR2 200Mhz
- 1 SATA port: internal
- Gigabit ethernet: PHY
On Tue, Jun 05, 2012 at 02:25:12PM -0700, Tom Warren wrote:
Did you use the -C option for format-patch? I'd expect a lot of these file
moves to show up as simple renames.
Yes, if you look inside [PATCH v2 01/10] tegra20: rename tegra2 -
tegra20 for example, all the renames came out ok, I
Hi Prafulla,
On Tue, Jun 5, 2012 at 4:36 PM, Michael Walle mich...@walle.cc wrote:
Hi Prafulla,
Am Dienstag 05 Juni 2012, 23:33:13 schrieb Michael Walle:
Changes:
v9:
- rebase to marvell custodian tree, merged with wolfgangs master
[..snip..]
I had to merge your tree with wolfgangs
When support sh7734 of sh-ether, ECSIPR_BRCRXIP and other were removed.
Therefore SH7757 and SH7724 can not build. This revise this probelem.
Signed-off-by: Nobuhiro Iwamatsu iwama...@nigauri.org
---
drivers/net/sh_eth.h |7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, June 06, 2012 2:14 AM
To: Xie Shaohui-B21989
Cc: Wood Scott-B07421; u-boot@lists.denx.de; Tabi Timur-B04825
Subject: Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support pbl
image build.
On 06/05/2012 12:35 AM, Xie
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