This patch set enables I2C support for EXYNOS5.
This patchset modifies the s3c24x0 I2C driver to use same for EXYNOS5.
Multichannel support has been added to the s3c24x0 I2C driver.
s3c24x0_i2c struct has been moved to a common place as it can used
by different SOC's.
Changes in V2:
-
This adds i2c clock information for EXYNOS5.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
changes in V2:
- Incorporated comments
This patch adds the base address for I2C.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
arch/arm/include/asm/arch-exynos/cpu.h |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
This patch adds pinmux code for I2C.
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- Aligned the pinmux functionality as per the latest comments.
This patch depends on the following patch:
[U-Boot] [PATCH 1/2 V6]
This adds multiple i2c channel support for I2C.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
drivers/i2c/s3c24x0_i2c.c | 27 +++
1 files changed, 27
This patch modifies the S3C I2C driver to suppport EXYNOS5.
The cahnges made to driver are as follows:
- I2C base address is passed as a parameter to many
functions to avoid multiple #ifdef
- I2C init for Exynos5 is made as different function.
- Channel
This enables I2C support on smdk5250.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
include/configs/smdk5250.h |8
1 files
struct s3c24x0_i2c is being moved to common local header file so that
the same can be used by s3c series and exynos series SoCs.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
As exynos has more than one i2c channels. This patch adds offset padding
for struct s3c24x0_i2c, in order to get the new base address of next i2c
channel.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.
This has the following advantages:
1. No longer need to rebuild an image when change
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
bootmaster to SRIO1 or SRIO2 using the following command:
setenv bootmaster SRIO1
saveenv
The bootmaster will
Update some descriptions due to the implementation changes:
For master:
Get rid of the SRIOBOOT_MASTER build target, and to support
for serving as a SRIO boot master via environment variable.
For slave:
1. When compile the slave image for boot from SRIO, no longer
Added descriptions about boot from PCIE in the files README and
doc/README.srio-pcie-boot-corenet, and changed the name of the
doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang gang@freescale.com
---
README| 12 ++--
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the
For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.
The processor
On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
snip
diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your
Dear Zang Roy-R61911,
The patch [PATCH V2] MPC8xxx: Define cache ops for USB wasn't applied yet for
some reason. It fixes the issue.
Hi, Marek
When I build P5020DS_config with the current u-boot head, I got:
/home/roy/CVS/upstream/u-boot/drivers/usb/host/ehci-hcd.c:346: undefined
Hi Prafulla,
On 06/05/2012 04:21 PM, Prafulla Wadaskar wrote:
-Original Message-
From: Valentin Longchamp [mailto:valentin.longch...@keymile.com]
Sent: 01 June 2012 17:01
To: Prafulla Wadaskar
Cc: u-boot@lists.denx.de; Valentin Longchamp; Holger Brunck
Subject: [PATCH v4 5/5]
From: Lad, Prabhakar prabhakar@ti.com
This series adds MMC/SD, NAND and NOR SPL support
for Logic PD's DA850/OMAP-L138 EVM. This series
also fixes some issues found on the EVM during
testing. The patches are sent in a series as these
patches need to be applied in the order they are sent.
From: Lad, Prabhakar prabhakar@ti.com
This patch adds support for MMC/SD on DA850/OMAP-L138.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
Changes for v2:
1:Removed
From: Rajashekhara, Sudhakar sudhakar@ti.com
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
MMC and NOR to work on DA850/OMAP-L138 Rev.3 EVM. When
GP0[11] is low, the SD0 interface will not work, but NOR
flash will. When GP0[11] is high, SD0 will work but NOR
flash will not.
From: Lad, Prabhakar prabhakar@ti.com
DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
do the low level initialization and then loads the u-boot image
from MMC/SD card.
Define the CONFIG_SPL_MMC_LOAD macro in
From: Rajashekhara, Sudhakar sudhakar@ti.com
On Logic PD Rev.3 DA850/OMAP-L138 EVM, NOR and MMC/SD cannot
work together. This patch enables the MMC/SD support only
when NOR support is disabled. NOR Flash identification works
even without this patch, but erase and write will have issues.
From: Lad, Prabhakar prabhakar@ti.com
Though Commit id a3f88293ddd13facd734769c1664d35ab4ed681f (da850evm:
setup the NAND flash timings) has configured the AEMIF timings, they
are not exactly in sync with the timings used in Linux. Linux is
configuring the timing register as 0x0804, where
From: Lad, Prabhakar prabhakar@ti.com
This patch adds support for NAND SPL on DA850/OMAP-L138.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
Changes for v2:
1:Added a
From: Lad, Prabhakar prabhakar@ti.com
This patch adds support for direct NOR boot mode on
da850/omap-l138. added da850evm_direct_nor entry in
boards.cfg to allow to build targets.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
This series adds support for 2 new Kirkwood boards at Keymile: kmnusa and
kmcoge5un. All the previously supported boards that had a proper config file
now are all supported by the generic km_kirkwood.h config file.
This series also adds support for the environment variables in the SPI NOR
Flash,
This used to be done with registers direct access, which is not clear
and optimal.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Gerlando Falauto gerlando.fala...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
This is required for all our keymile ARM boards. The selected MPPs are
the default one for the SPI controller, thus the 0x0 definition.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
cc: Holger Brunck holger.bru...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
So that they can be redefined by some boards specific values.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Gerlando Falauto gerlando.fala...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
This is achieved thanks to the support read/write regs for the external
88e6352 switch. The functions for this are added into an own file
managed_switch.c. This is compiled if the define CONFIG_KM_MANAGED_SW_ADDR
was set in the board setup. This define specifies the phy address.
Signed-off-by:
They are needed on all km_arm boards where we have the environement
variables in the NOR Flash. First boards using this feature are
kmcoge5un and kmnusa.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Gerlando Falauto
From: Holger Brunck holger.bru...@keymile.com
This board is similar to portl2, but it has the u-boot environment
in a SPI NOR flash and not in an i2c eeprom like portl2 have.
Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352
From: Holger Brunck holger.bru...@keymile.com
Remove config options from boards.cfg and simply add one switch
per board and differ afterwards in km_kirkwood.h between the features.
More boards are upcoming and therefore it's easier to have this
at one place.
Signed-off-by: Holger Brunck
This can be used if we do not want to use an EEPROM for the
configuration.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
board/keymile/common/common.h |7 --
board/keymile/km_arm/managed_switch.c | 169 +++--
This adds a first support of the FPGA download for a PCIe FPGA based
on the BOCO2 CPLD.
This takes place in 3 steps, all done accessing the SPICTRL reg of the
BOCO2:
1) start the FPGA config with an access to the FPGA_PROG bit
2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to
From: Holger Brunck holger.bru...@keymile.com
Now we toggle between SPI and NAND flash automatically if
we claim the SPI bus. So we can get rid of this command.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
cc: Prafulla
In order to be able to perform board resets without interrupting the
traffic, the configuration of an already properly configured FPGA is
skipped.
This is because some PCIe FPGAs embed some other function that must
continue to work over reset.
It is then the responsibility of the application to
Some very similar #defines for reg addresses are used in a later patch
(managed_switch support for km_arm).
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
cc: Holger Brunck holger.bru...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
board/keymile/km_arm/km_arm.c |
The PCIe FPGAs now have to support 2 resets: one for the non traffic
affecting part (PCIe) and one for the traffic affecting part.
When the FPGA is not reconfigured, we only reset the PCIe part.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
From: Holger Brunck holger.bru...@keymile.com
For u-boot this board is similar to mgcoge3un. But some differences
are present. We have a different SDRAM on it and therefore a new
SDRAM config file. Additionaly this board has a direct MAC/MAC
connection from the kirkwood to a marvell simple switch
The configuration EEPROM should be removed for P1B.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
board/keymile/km_arm/km_arm.c | 11 +--
board/keymile/km_arm/managed_switch.c |3 ++-
board/keymile/km_arm/managed_switch.h |7 +++
3 files
From: Thomas Herzmann thomas.herzm...@keymile.com
Add a function to read the dip_switch on kmcoge5un. If the
switch is set the actual_bank is set to 0 and this SW is
booted.
Signed-off-by: Thomas Herzmann thomas.herzm...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
---
From: Holger Brunck holger.bru...@keymile.com
Use the generic header km_kirkwood.h and get rid of the
board specific header.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
cc: Gerlando Falauto gerlando.fala...@keymile.com
These functions tried to access two static tables before relocation
(board_early_init_f is executed before relocation). But these static
tables lie in the bss section which is not valid before relocation.
These accesses then overwrote some parts of u-boot binary before it was
relocated. For the
From: Holger Brunck holger.bru...@keymile.com
The additional headerfile is unneeded here, we can use the generic
km_kirkwood.h instead. And we can use the better config option
KM_PIGGY4_88E6061 for the specific features for boards with this
design in km_arm.c.
Signed-off-by: Holger Brunck
From: Thomas Herzmann thomas.herzm...@keymile.com
On kmcoge5un unfortunately the HW wiring is differently to
other km arm boards.
Signed-off-by: Thomas Herzmann thomas.herzm...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
---
board/keymile/km_arm/km_arm.c |4
1
From: Rajashekhara, Sudhakar sudhakar@ti.com
On DA850/OMAP-L138 it was observed that in RMII mode,
auto negotiation was not performed. This patch enables
auto negotiation in RMII mode. Without this patch, EMAC
initialization takes more time and sometimes tftp fails
in RMII mode.
Hi Eric,
On Wed, Jun 06, 2012 at 22:47:46, Eric Bénard wrote:
Hi Prabhakar,
Le Fri, 1 Jun 2012 19:04:37 +0530,
Prabhakar Lad prabhakar@ti.com a écrit :
From: Rajashekhara, Sudhakar sudhakar@ti.com
On DA850/OMAP-L138 it was observed that in RMII mode,
auto negotiation was
Hi all,
On Sun, May 27, 2012 at 11:44:51PM +0200, Luka Perkov wrote:
The kwboot program boots boards based on Marvell's Kirkwood platform
via Xmodem over their integrated UART.
Signed-off-by: Daniel Stodden daniel.stod...@googlemail.com
Acked-by: Luka Perkov ub...@lukaperkov.net
Tested-By:
Hi Albert,
On Tue, May 15, 2012 at 09:42:59PM +0200, Albert ARIBAUD wrote:
On Sun, Apr 29, 2012 at 10:19:41PM +0200, Luka Perkov wrote:
On Thu, Apr 19, 2012 at 08:38:19AM +0200, Albert ARIBAUD wrote:
Not my main area of expertise here, but I am not sure how this plays
on Marvell non-kirkwood
Albert,
On Thu, May 31, 2012 at 9:47 AM, Tom Warren twarren.nvi...@gmail.com wrote:
Albert,
Please pull u-boot-tegra/master into ARM master. Thanks!
Haven't seen a reply, so repinging you.
Thanks,
Tom
The following changes since commit 2ca4a209a5b961ad1be8782c68dabe326d77dfaf:
SRICHARAN
On 06/07/2012 01:15 AM, Sughosh Ganu wrote:
On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
snip
diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h
+ * published by the Free Software Foundation; either
On 06/06/2012 10:16 PM, Xie Shaohui-B21989 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, June 07, 2012 2:19 AM
To: Xie Shaohui-B21989
Cc: Wood Scott-B07421; u-boot@lists.denx.de; Tabi Timur-B04825
Subject: Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support
On Wed, Jun 06, 2012 at 07:02:45PM -0700, Stephen Warren wrote:
On 06/06/2012 04:00 PM, Allen Martin wrote:
Yes, that's the intention. Although I do have plans down the road for
adding memory initialization to the SPL so I can use it for
boot/flashing when in recovery mode and there's no
On Thu Jun 07, 2012 at 10:36:53AM -0600, Stephen Warren wrote:
On 06/07/2012 01:15 AM, Sughosh Ganu wrote:
On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
snip
diff --git a/include/configs/tegra2-spl.h
Commit 418396e212b59bf907dbccad997ff50f7eb61b16 introduced a
bug that causes nand read and nand write to crash in strcmp
due to a null pointer.
Root cause is that strchr(cmd, '.') returns a null pointer when
the input string does not contain a '.'
The strcmp function does not check for null
On 06/07/2012 12:19 PM, Steve Sakoman wrote:
Commit 418396e212b59bf907dbccad997ff50f7eb61b16 introduced a
bug that causes nand read and nand write to crash in strcmp
due to a null pointer.
Root cause is that strchr(cmd, '.') returns a null pointer when
the input string does not contain a
From: Fabio Estevam fabio.este...@freescale.com
CONFIG_MII_GASKET is not defined anywhere, so remove it.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
include/configs/mx53ard.h |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/include/configs/mx53ard.h
On 06/07/2012 11:04 AM, Sughosh Ganu wrote:
On Thu Jun 07, 2012 at 10:36:53AM -0600, Stephen Warren wrote:
On 06/07/2012 01:15 AM, Sughosh Ganu wrote:
On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote:
On 06/05/2012 03:20 PM, Allen Martin wrote:
snip
diff --git
Dear Xie Shaohui-B21989,
In message
ed492cceaf882048bc2237de806547c907968...@039-sn2mpn1-012.039d.mgd.msft.net
you wrote:
I want to get rid if config.mk files to the extend possible - and here I
see no need for a new one.
[Xie Shaohui] Actually, I was hesitate to use the config.mk file, I
Dear Zang Roy-R61911,
In message 201206071134.02455.ma...@denx.de Marek Vasut wrote:
The patch [PATCH V2] MPC8xxx: Define cache ops for USB wasn't applied yet
for
some reason. It fixes the issue.
Hi, Marek
When I build P5020DS_config with the current u-boot head, I got:
...
Do
Dear Marek Vasut,
In message 1337955286-22345-1-git-send-email-ma...@denx.de you wrote:
This patch conditionally defines flush_dcache_range() and
invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining,
resulting in the following output:
$ ARCH=powerpc
Dear Nobuhiro Iwamatsu,
In message cabmqnvj7_tzmnk6gv+wz9yebrugn2cc_oj8enr2byhpve3k...@mail.gmail.com
you wrote:
Dear Wolfgang Denk.
Please pull from git://git.denx.de/u-boot-sh master.
Best regards,
Nobuhiro
The following changes since commit
Dear Daniel Schwierzeck,
In message
1338761093-27598-1-git-send-email-daniel.schwierz...@googlemail.com you wrote:
Dear Wolfgang,
please pull some checkpatch.pl cleanups for MIPS.
The following changes since commit 4398d55991eb3c2484a2a8e991d701e5d7a64874:
net: sh-eth: Add support
Dear Andreas =?iso-8859-1?Q?Bie=DFmann?=,
In message 20120604104547.ga29...@azuregos.er.corscience.de you wrote:
The following changes since commit 4398d55991eb3c2484a2a8e991d701e5d7a64874:
net: sh-eth: Add support Gigabit of SH7734 (2012-05-23 17:53:09 -0500)
are available in the git
Dear Rudy,
In message
7a6a685f2ad2c242812385088f128c121c5a332...@ausp01vmbx02.collaborationhost.net
you wrote:
The latest version does not appear to contain support for the the
twrmpc5125 processor because the following command issued in the
u-boot installation directory yields nothing.
Dear Anatolij Gustschin,
In message 20120605095753.0b080872@wker you wrote:
Hello Wolfgang,
The following changes since commit 4398d55991eb3c2484a2a8e991d701e5d7a64874:
net: sh-eth: Add support Gigabit of SH7734 (2012-05-23 17:53:09 -0500)
are available in the git repository at:
This commit is an add-on to f6c4191f. There are a few other registers where
consecutive writes must have a delay.
Signed-off-by: Dinh Nguyen dingu...@altera.com
---
drivers/net/designware.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/designware.c
On Thu, 2012-06-07 at 15:27 +0200, Luka Perkov wrote:
Hi all,
On Sun, May 27, 2012 at 11:44:51PM +0200, Luka Perkov wrote:
The kwboot program boots boards based on Marvell's Kirkwood platform
via Xmodem over their integrated UART.
Signed-off-by: Daniel Stodden
Dear Dinh,
In message 1339104480-6191-1-git-send-email-dingu...@altera.com you wrote:
This commit is an add-on to f6c4191f. There are a few other registers where
consecutive writes must have a delay.
Sorry, but this commit message is misleading - I was expecting to see
something like udelay()
Dear Dinh,
In message
71b37e0559ac6849a68c5ba94c509fb458298d3...@sj-itmsg02.altera.priv.altera.com
you wrote:
Sorry, but this commit message is misleading - I was expecting to see
something like udelay() in the code, but there wasn't any...
Combining the 2 individual writes into a
The controller can control high capacity cards. So, the patch adds
the flag. If the flag is not set, mmcinfo will fail when a high
capacity card is used.
Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com
---
drivers/mmc/sh_mmcif.c |2 +-
1 files changed, 1 insertions(+), 1
On 06/06/2012 10:16 PM, Xie Shaohui-B21989 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, June 07, 2012 2:19 AM
To: Xie Shaohui-B21989
Cc: Wood Scott-B07421; u-boot@lists.denx.de; Tabi Timur-B04825
Subject: Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support
Since the type of ext_csd was array of char, the following
calculation might fail when the value of ext_csd[EXT_CSD_SEC_CNT]
was minus.
capacity = ext_csd[EXT_CSD_SEC_CNT] 0
| ext_csd[EXT_CSD_SEC_CNT + 1] 8
| ext_csd[EXT_CSD_SEC_CNT + 2]
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