Dear Tom Rini,
In message 1340146475-15969-2-git-send-email-tr...@ti.com you wrote:
Exactly one board has defined CONFIG_SYS_PROMPT_HUSH_PS2 to a value
different than which is vision2. I have Cc'd the maintainer here
as I strongly suspect this is a bug rather than intentional behavior.
Dear Tom Rini,
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum. We add a cpp check to usb.h to define USB_DMA_MINALIGN and
On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote:
Dear Tom Rini,
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
Dear Tom Rini,
On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote:
Dear Tom Rini,
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for
cache coherency. In those cases, use that value rather
On Wed, Jun 20, 2012 at 11:15:26PM +0200, Marek Vasut wrote:
Dear Tom Rini,
On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote:
Dear Tom Rini,
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum
Hey all,
In commit b8adb12 the cache flushing behavior was changed for the EHCI
stack. This change showed a few different problems on TI platforms
(where our cacheline size is 64 not 32). First, the dcache_off call
that ehci-omap had been doing was now not happening soon enough to paper
over
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum. We add a cpp check to usb.h to define USB_DMA_MINALIGN and
make use of it in
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Ilya Yanok ya...@emcraft.com
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/mcx.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Cc: Marek Vasut ma...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
---
drivers/usb/host/ehci-omap.c |1 -
1 file changed, 1 deletion(-)
diff --git
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/omap3_beagle.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Sricharan R r.sricha...@ti.com
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/omap4_panda.h |1 +
1 file changed, 1 insertion(+)
diff --git
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Stefano Babic sba...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/tam3517-common.h |1 +
1 file changed, 1 insertion(+)
diff --git
Hi Rajeshwari,
On 06/20/2012 07:40 PM, Rajeshwari Shinde wrote:
This patch set adds support for Exynos5250 Rev 1.0.
Exynos5250 Rev 1.0 supports DDR3 Memory configuration and
support for LPDDR2 is removed.
Exynos5250 Rev 1.0 supports DWMMC driver but the support for same is
not yet gone into
Dear Tom Rini,
On Wed, Jun 20, 2012 at 11:15:26PM +0200, Marek Vasut wrote:
Dear Tom Rini,
On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote:
Dear Tom Rini,
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a
On Mon, Jun 04, 2012 at 08:34:39AM -0700, Steve Sakoman wrote:
This patch sets up pinmux, enables fclk, and
defines CONFIG_I2C_MULTI_BUS
You add, but don't use the pinmux for i2c1:
mux.c:283: warning: 'i2c1_pin_mux' defined but not used
v2 please? :)
--
Tom
On Thu, Jun 14, 2012 at 10:29:47AM +0200, Stefano Babic wrote:
Signed-off-by: Stefano Babic sba...@denx.de
[snip]
+static GraphicDevice panel;
+static const struct panel_config lcd_cfg = {
+ .timing_h = 0x01101d1b, /* Horizontal timing */
+ .timing_v = 0x01400b02, /*
http://amaiko.net/files/live/google.html?sdm=ef.sxfsony=yug.jygydl=tsuw
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
ARMv7 has global timer. This provides the register definition of this timer.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/arm/include/asm/arch-armv7/globaltimer.h | 36 +
1 file changed, 36 insertions(+)
create mode 100644
This patch adds minimum support for R-Mobile. Only minimal support with timer.
This CPU can uses the peripheral of Renesas SuperH.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/arm/cpu/armv7/rmobile/Makefile | 48 +
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like usb reset in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we clear that bit after Port Reset in order to
Hi, Rajeshwari.
2012/6/20 Rajeshwari Shinde rajeshwar...@samsung.com:
Define additional registers for clock control in Exynos5250 Rev 1.0
Many registers for clock is missed for EVT1 and exist for EVT0 still
in this patch.
Please make using all registers of clock for EVT1 only.
Thanks.
Hi,
2012/6/20 Rajeshwari Shinde rajeshwar...@samsung.com:
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali hatim...@samsung.com
Signed-off-by: Rajeshwari Shinde
Hi Joonyoung Shim,
Thank you for comments.
On Thu, Jun 21, 2012 at 10:25 AM, Joonyoung Shim dofm...@gmail.com wrote:
Hi, Rajeshwari.
2012/6/20 Rajeshwari Shinde rajeshwar...@samsung.com:
Define additional registers for clock control in Exynos5250 Rev 1.0
Many registers for clock is missed
On 06/20/2012 09:24 PM, Jim Lin wrote:
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like usb reset in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we
res1[] size is wrong.
It didn't consider the s5p_gpio_bank size.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/include/asm/arch-exynos/gpio.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git
Hi Rajeshwari,
I just considered the EVT1 board.
I will resend the patch for this.
Best Regards,
Jaehoon Chung
On 06/20/2012 02:55 PM, Rajeshwari Birje wrote:
Hi Jaehoon Chung,
Had few comments...
Is this changes for EVT1 board?
As per the EVT1 Manual I have it is:
MMC0: Correct as
Sorry Luka (and all), been tied up pretty heavily recently, had to
adjust to find some free time again.
I will test your patch today and post results tonight.
2012/6/7 Luka Perkov ub...@lukaperkov.net
Hi Albert,
On Tue, May 15, 2012 at 09:42:59PM +0200, Albert ARIBAUD wrote:
On Sun, Apr
Dear Rajeshwari Birje,
On 19 June 2012 19:57, Rajeshwari Birje rajeshwari.bi...@gmail.com wrote:
Hi Joonyoung Shim,
On Tue, Jun 19, 2012 at 1:20 PM, Joonyoung Shim dofm...@gmail.com wrote:
Hi,
I add some comments at the below.
-- ok
And current SMDK5250 uses Exynos5250 EVT0 base codes,
Hi Minkyu Kang,
This being I2C driver code should not have any dependency on EVT0 or EVT1.
Regards,
Rajeshwari Shinde.
On Wed, Jun 20, 2012 at 2:01 PM, Minkyu Kang proms...@gmail.com wrote:
Dear Rajeshwari Birje,
On 19 June 2012 19:57, Rajeshwari Birje rajeshwari.bi...@gmail.com wrote:
Hi
On 20/06/2012 00:54, Tom Rini wrote:
Exactly one board has defined CONFIG_SYS_PROMPT_HUSH_PS2 to a value
different than which is vision2. I have Cc'd the maintainer here
as I strongly suspect this is a bug rather than intentional behavior.
Cc: Stefano Babic sba...@denx.de
Signed-off-by:
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like usb reset in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we clear that bit after Port Reset in order to
Hi Prabhakar,
On Tue, Jun 19, 2012 at 7:06 AM, Lad, Prabhakar prabhakar@ti.com wrote:
Hi Christian,
On Tue, Jun 19, 2012 at 01:09:08, Christian Riesch wrote:
Hi,
Sorry for the delay, had a lot of other work to do :-/
On Thursday, June 7, 2012, Prabhakar Lad wrote:
From: Lad,
2012/6/20 Rajeshwari Birje rajeshwari.bi...@gmail.com:
Hi Minkyu Kang,
This being I2C driver code should not have any dependency on EVT0 or EVT1.
I mean *all* arch and driver codes for Exynos5250 should support EVT1 only.
Thanks.
Regards,
Rajeshwari Shinde.
On Wed, Jun 20, 2012 at 2:01
Hi Christian,
On Wed, Jun 20, 2012 at 14:50:41, Christian Riesch wrote:
Hi Prabhakar,
On Tue, Jun 19, 2012 at 7:06 AM, Lad, Prabhakar prabhakar@ti.com wrote:
Hi Christian,
On Tue, Jun 19, 2012 at 01:09:08, Christian Riesch wrote:
Hi,
Sorry for the delay, had a lot of other work
This patch set adds support for Exynos5250 Rev 1.0.
Exynos5250 Rev 1.0 supports DDR3 Memory configuration and
support for LPDDR2 is removed.
Exynos5250 Rev 1.0 supports DWMMC driver but the support for same is
not yet gone into Mainline. After DWMMC driver is added to Mainline
support for generic
Add a structure for table-driven configuration mechanism such that no
recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.
Signed-off-by: Che-Liang Chiou clch...@chromium.org
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Define table-driven configuration mechanism for SMDK5250
rather than hard-coding board initialization parameters.
Signed-off-by: Che-Liang Chiou clch...@chromium.org
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Tom Wai-Hong Tam waih...@chromium.org
Signed-off-by: Simon
Define additional registers for clock control in Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali hatim...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
arch/arm/include/asm/arch-exynos/clock.h | 36 +
1 files changed, 26 insertions(+), 10
Default spl/u-boot-spl.lds created by spl/Makefile resolves
the spl text load addr to 0x0. As 0x0 belongs to iROM addr so
Global variables can not be used.
Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables
in spl.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Add new clock values for Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali hatim...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
board/samsung/smdk5250/clock_init.c | 714 --
board/samsung/smdk5250/clock_init.h | 149
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali hatim...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
arch/arm/cpu/armv7/exynos/clock.c| 12
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
arch/arm/cpu/armv7/exynos/pinmux.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git
The patch adds the memory initialization sequence of DDR3.
Signed-off-by: Hatim Ali hatim...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
arch/arm/include/asm/arch-exynos/dmc.h | 65 +
board/samsung/smdk5250/Makefile|2 +-
This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
board/samsung/smdk5250/smdk5250.c |6 +++---
include/configs/smdk5250.h|2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git
This patch set adds support for Exynos5250 Rev 1.0.
Exynos5250 Rev 1.0 supports DDR3 Memory configuration and
support for LPDDR2 is removed.
Exynos5250 Rev 1.0 supports DWMMC driver but the support for same is
not yet gone into Mainline. After DWMMC driver is added to Mainline
support for generic
Add a structure for table-driven configuration mechanism such that no
recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.
Signed-off-by: Che-Liang Chiou clch...@chromium.org
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Define table-driven configuration mechanism for SMDK5250
rather than hard-coding board initialization parameters.
Signed-off-by: Che-Liang Chiou clch...@chromium.org
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Tom Wai-Hong Tam waih...@chromium.org
Signed-off-by: Simon
Default spl/u-boot-spl.lds created by spl/Makefile resolves
the spl text load addr to 0x0. As 0x0 belongs to iROM addr so
Global variables can not be used.
Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables
in spl.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Define additional registers for clock control in Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali hatim...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Chnages in V2:
- None
arch/arm/include/asm/arch-exynos/clock.h | 36 +
1 files
Add new clock values for Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali hatim...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Chnages in V2:
- None
board/samsung/smdk5250/clock_init.c | 714 --
board/samsung/smdk5250/clock_init.h
The patch adds the memory initialization sequence of DDR3.
Signed-off-by: Hatim Ali hatim...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Chnages in V2:
- None
arch/arm/include/asm/arch-exynos/dmc.h | 65 +
board/samsung/smdk5250/Makefile|2
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali hatim...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Chnages in V2:
- None
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Chnages in V2:
- None
arch/arm/cpu/armv7/exynos/pinmux.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git
This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Chnages in V2:
- None
board/samsung/smdk5250/smdk5250.c |6 +++---
include/configs/smdk5250.h|2 +-
2 files changed, 4 insertions(+), 4
Hi Rajeshwari,
On 06/20/2012 08:11 PM, Rajeshwari Shinde wrote:
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Chnages in V2:
- None
arch/arm/cpu/armv7/exynos/pinmux.c | 18
Hi Jaehoon Chung
On Wed, Jun 20, 2012 at 5:28 PM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi Rajeshwari,
On 06/20/2012 08:11 PM, Rajeshwari Shinde wrote:
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde
On 06/19/2012 01:50 PM, Wolfgang Denk wrote:
Dear Tom Rini,
In message 1335480396-29478-1-git-send-email-tr...@ti.com you wrote:
We provide a default table of { 9600, 19200, 38400, 57600, 115200 }
in config_fallbacks.h which mkconfig places after configs/...h in
the generated config file.
Hey all,
In commit b8adb12 the cache flushing behavior was changed for the EHCI
stack. This change showed a few different problems on TI platforms
(where our cacheline size is 64 not 32). First, the dcache_off call
that ehci-omap had been doing was now not happening soon enough to paper
over
This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Cc: Marek Vasut ma...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
---
drivers/usb/host/ehci-omap.c |1 -
1 file changed, 1 deletion(-)
diff --git
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum. We add a cpp check to usb.h to define USB_DMA_MINALIGN and
make use of it in
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Sricharan R r.sricha...@ti.com
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/omap4_panda.h |1 +
1 file changed, 1 insertion(+)
diff --git
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Ilya Yanok ya...@emcraft.com
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/mcx.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Stefano Babic sba...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/tam3517-common.h |1 +
1 file changed, 1 insertion(+)
diff --git
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/omap3_beagle.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 06/20/2012 03:15 AM, Jim Lin wrote:
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like usb reset in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we
Hi Sricharan,
On 06/15/2012 07:48 AM, R, Sricharan wrote:
Hi,
On Fri, Jun 15, 2012 at 12:31 AM, Tom Rinitr...@ti.com wrote:
If we are built with D-CACHE enabled but have run 'dcache off' and then
attempt to flush unaligned regions we spam the console with problems
that aren't true (as the
Dear Tom Rini,
In message 1340146475-15969-1-git-send-email-tr...@ti.com you wrote:
We provide a default table of { 9600, 19200, 38400, 57600, 115200 }
in config_fallbacks.h which mkconfig places after configs/...h in
the generated config file. This is used when a board has not set its
own
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