There is only one pio_word in this DMA transaction so data field must be 1.
Signed-off-by: Luca Ellero luca.ell...@brickedbrain.com
---
drivers/mtd/nand/mxs_nand.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
Hi Przemyslaw,
The function mmc_block_op() is the last function before
the physicall data write, but the mmc device pointer is not
checked. If mmc device not exists, then data abort will occur.
To avoid this, first the mmc device pointer is checked.
Signed-off-by: Przemyslaw Marczak
Hi Przemyslaw,
Some pointers in function download_tail() were not checked
before the use. This could possibly cause the data abort.
To avoid this, check if the pointers are not null is added.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
drivers/usb/gadget/f_thor.c | 16
Hi Luca,
On 10.12.2014 09:24, Luca Ellero wrote:
There is only one pio_word in this DMA transaction so data field must be 1.
Signed-off-by: Luca Ellero luca.ell...@brickedbrain.com
---
drivers/mtd/nand/mxs_nand.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
For B4 the LIODN register for PCIe is in PCIe address space and not in
GUTs
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Shaveta Leekha shav...@freescale.com
Signed-off-by: Laurentiu Tudor
CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
arch/powerpc/include/asm/fsl_secure_boot.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h
On 08.11.2014 12:31, Marek Vasut wrote:
On Friday, November 07, 2014 at 04:53:48 PM, Rene Griessl wrote:
This patch adds driver support for the ASIX AX88179 USB3.0 to GbE network
adapter.
Driver has been tested on the RECS5250 COM module (similar to ARDALE5250).
Testcase was DHCP and PXE
Hi Luca,
On 12.12.2014 13:40, Luca Ellero wrote:
On 10.12.2014 09:24, Luca Ellero wrote:
There is only one pio_word in this DMA transaction so data field must
be 1.
Signed-off-by: Luca Ellero luca.ell...@brickedbrain.com
---
drivers/mtd/nand/mxs_nand.c |2 +-
1 file changed, 1
This patch series add the Intel Queensbay platform support. The Queensbay
platform includes an Atom E6xx processor (codename Tunnel Creek) and a
Platform Controller Hub EG20T (codename Topcliff). The support depends
on Intel Firmware Support Package (FSP) to initialize the processor and
chipset
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.
Signed-off-by: Bin Meng bmeng...@gmail.com
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3:
Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_
macros. Also make writing mrc.bin and pci option rom to u-boot.rom
optional and remove mrc.bin from its dependent file list as not
every x86 board port needs mrc binary blob.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by:
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
arch/x86/dts/Makefile | 3 ++-
arch/x86/dts/crownbay.dts | 53 +++
2 files changed, 55 insertions(+), 1 deletion(-)
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
include/pci_ids.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/pci_ids.h b/include/pci_ids.h
index ee98bee..26f4748 100644
---
Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 1 +
arch/x86/include/asm/post.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/cpu.c
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two
Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/queensbay/M0220661105.inc | 1288
1 file changed, 1288 insertions(+)
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 7f09db5..5033d2b 100644
---
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.
Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v3:
- Update
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- Fix several typos in queensbay/Kconfig
- Change FSP_FILE and CMC_FILE description to indicate the file is
in the board directory
- Add help for FSP_TEMP_RAM_ADDR
- Add
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- New patch to use consistent name XXX_ADDR for binary blobs
Makefile | 2 +-
arch/x86/cpu/ivybridge/sdram.c | 2 +-
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Add a commit
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
configs/crownbay_defconfig | 6 ++
include/configs/crownbay.h | 52 ++
2 files changed, 58 insertions(+)
create mode
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- New patch to rename coreboot-serial to x86-serial
arch/x86/dts/coreboot.dtsi | 2 +-
drivers/serial/Makefile| 2 +-
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- Remove the 'make menuconfig' in the crownbay build instructions
- Indicate all the binary blobs should be put in the board directory
doc/README.x86 | 126
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- Use
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- Update ifdtool flags to indicate FSP and CMC files are in
the board directory
- Use consistent XXX_FILE name for binary blob file
Makefile | 10
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3: None
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.
For more details, check http://www.intel.com/fsp.
Note: U-Boot coding convention was applied to these codes, so it
On Friday, December 12, 2014 at 01:43:22 PM, Stefan Roese wrote:
Hi Luca,
On 12.12.2014 13:40, Luca Ellero wrote:
On 10.12.2014 09:24, Luca Ellero wrote:
There is only one pio_word in this DMA transaction so data field must
be 1.
Signed-off-by: Luca Ellero
Signed-off-by: Pierre Aubert p.aub...@staubli.com
---
arch/arm/imx-common/spl.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index 477c38c..ac6e40e 100644
--- a/arch/arm/imx-common/spl.c
+++
This patch-set added byte program support for sst flashes
and some implementation changes in sf to support array slow
and byte program specific controllers.
Changes for v2:
- commit message fixes
Bin Meng (3):
spi: sf: Support byte program for sst spi flash
x86: ich-spi: Set the rx
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.
So this fix on sf will correctly handle the slow read supported
controllers.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Tested-by: Bin Meng
From: Simon Glass s...@chromium.org
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.
Reported-by: Jens Rottmann jens.rottm...@adlinktech.com
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by:
From: Bin Meng bmeng...@gmail.com
ICH 7 SPI controller only supports byte program (02h) for SST flash.
Word program (ADh) is not supported.
Signed-off-by: Bin Meng bmeng...@gmail.com
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/spi/ich.c | 9 +++--
1 file
Enabled byte program support for sst flashes in sf.
Few controllers will only support BP, so this patch gives
a tx transfer flag to set the BP so-that sf will operate
on byte program transfer.
A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for
From: Bin Meng bmeng...@gmail.com
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
From: Bin Meng bmeng...@gmail.com
ICH 7 SPI controller only supports array read command (03h).
Fast array read command (0Bh) is not supported.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
Reviewed-by: Jagannadha
On 12 December 2014 at 19:36, Jagannadha Sutradharudu Teki
jagannadh.t...@gmail.com wrote:
This patch-set added byte program support for sst flashes
and some implementation changes in sf to support array slow
and byte program specific controllers.
Changes for v2:
- commit message
From: Fabio Estevam fabio.este...@freescale.com
As per the mx51evk schematics MX51EVK_USB_CLK_EN_B is GPIO2_1, not GPIO2_2.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/freescale/mx51evk/mx51evk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi Jagan,
On Fri, Dec 12, 2014 at 10:09 PM, Jagan Teki jagannadh.t...@gmail.com wrote:
On 12 December 2014 at 19:36, Jagannadha Sutradharudu Teki
jagannadh.t...@gmail.com wrote:
This patch-set added byte program support for sst flashes
and some implementation changes in sf to support array
Hello,
On 12/12/2014 01:32 AM, Simon Glass wrote:
Hi Przemyslaw,
On 11 December 2014 at 05:01, Przemyslaw Marczak p.marc...@samsung.com wrote:
The present fat implementation ignores FAT16 long name
directory entries which aren't placed in a single sector.
This was becouse of the buffer was
-
mktest_files: script for generating random size long name files
-
Usage:
./1_mktest_files.sh count
count - number of files to be generated
The output directory is: ./test_files
Hello,
On 12/12/2014 04:52 PM, Przemyslaw Marczak wrote:
-
mktest_files: script for generating random size long name files
-
Usage:
./1_mktest_files.sh count
count - number of files
On Thu, Dec 11, 2014 at 10:48:43AM +0100, Linus Walleij wrote:
Hi folks
(David Steve listed as AArch64/v8 maintainers),
are you actively maintaining and reviewing ARM64 board
patches?
I am working on support for the ARM Juno Development
Platform real hardware, which is now up and
On 12/12/2014 12:41 AM, Laurentiu Tudor wrote:
For B4 the LIODN register for PCIe is in PCIe address space and not in
GUTs
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Shaveta Leekha shav...@freescale.com
On 14-12-11 01:48 AM, Linus Walleij wrote:
Hi folks
(David Steve listed as AArch64/v8 maintainers),
are you actively maintaining and reviewing ARM64 board
patches?
Sadly, no.
If you would take over being maintainer for the vexpress_aemv8a_semi
board, that would be appreciated.
Thanks,
Hi All,
I did not get any feedback on the original posting of these series, can
I please get some feedback ?
If I can get acks for this from people involved in config_distro_bootcmd
(Warren, Dennis ?) then I can queue this up in u-boot-sunxi/next unless
people want to see this merged through
When using usb-keyboard support, typically usb will already get started from
preboot. In this case doing it again in the bootcmd is undesirable.
Allow the user of config_distro_bootcmd to indicate that usb is inited in
preboot through the user setting BOOTENV_PREBOOT_INITS_USB.
Signed-off-by:
Use the new BOOTENV_PREBOOT_INITS_USB define to avoid usb being scanned twice
when using usb kbd + usb boot.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
include/configs/sunxi-common.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/configs/sunxi-common.h
Acked-by: Steve Rae s...@broadcom.com
On 14-11-20 02:25 AM, Linus Walleij wrote:
The semihosting code exposes internal file handle handling
functions to read(), open(), close() and get the length of
a certain file handle.
However the code using it is only interested in either
reading and
From: Nikolay Dimitrov picmas...@mail.bg
Fix issue in parse_verify_sum() which swaps handling of env-var and *address.
Move hash_command() argc check earlier.
Cosmetic change on do_hash() variable declaration.
Improved help message for hash command.
Signed-off-by: Nikolay Dimitrov
On 14-11-20 02:25 AM, Linus Walleij wrote:
There is currently a regression when using newer ARM64 compilers
for semihosting: the way long types are inferred from context
is no longer the same.
The semihosting runtime uses long and size_t, so use this
explicitly in the semihosting code and
Acked-by: Steve Rae s...@broadcom.com
On 14-11-20 02:25 AM, Linus Walleij wrote:
By rearranging the functions in the semihosting code we can
avoid forward-declaration of the internal static functions.
This puts the stuff in a logical order: read/open/close/len
and then higher-order functions
On 12/12/2014 10:50 AM, Hans de Goede wrote:
When using usb-keyboard support, typically usb will already get started from
preboot. In this case doing it again in the bootcmd is undesirable.
Allow the user of config_distro_bootcmd to indicate that usb is inited in
preboot through the user
From: Nikolay Dimitrov picmas...@mail.bg
Signed-off-by: Nikolay Dimitrov picmas...@mail.bg
---
include/configs/embestmx6boards.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/embestmx6boards.h
b/include/configs/embestmx6boards.h
index 185edbe..28099a8
Hi Jagan,
On 12 December 2014 at 07:09, Jagan Teki jagannadh.t...@gmail.com wrote:
On 12 December 2014 at 19:36, Jagannadha Sutradharudu Teki
jagannadh.t...@gmail.com wrote:
This patch-set added byte program support for sst flashes
and some implementation changes in sf to support array slow
Hi Nobuhiro,
Very good state, just a few niggles.
On Nov 12, 2014, at 06:35 , Nobuhiro Iwamatsu
nobuhiro.iwamatsu...@renesas.com wrote:
This adds Renesas rmobile ARM SoC's SD/MMC host support.
This drivers tested with Gose board and Koelsch board.
Signed-off-by: Yoshiyuki Ito
Hi Lubomic,
On Nov 11, 2014, at 12:25 , Lubomir Popov lpo...@mm-sol.com wrote:
If print_mmc_devices() was called with a '\n' separator (as done
for example by the mmc list command), it offset the 2-nd and
all subsequent lines by one space. Fixing this.
Signed-off-by: Lubomir Popov
Hi Markus,
Looks good to me.
On Nov 18, 2014, at 16:11 , Markus Niebel list-09_u-b...@tqsc.de wrote:
From: Markus Niebel markus.nie...@tq-group.com
if the card claims to be high capacity and the card
is partitioned the capacity shall still be read from
ext_csd SEC_COUNT even if the
Hi Markus,
On Nov 18, 2014, at 16:13 , Markus Niebel list-09_u-b...@tqsc.de wrote:
From: Markus Niebel markus.nie...@tq-group.com
Signed-off-by: Markus Niebel markus.nie...@tq-group.com
---
drivers/mmc/mmc.c | 3 +++
include/mmc.h | 1 +
2 files changed, 4 insertions(+)
diff --git
Hi Jaehoon,
On Nov 28, 2014, at 13:42 , Jaehoon Chung jh80.ch...@samsung.com wrote:
To debug more exactly, add the index for device.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
drivers/mmc/exynos_dw_mmc.c | 22 --
1 file changed, 12 insertions(+), 10
On Thu, Dec 11, 2014 at 06:00:02PM -0700, Simon Glass wrote:
Hi Tom Rini,
Here is the I2C driver model work at last along with the first conversion.
The following changes since commit 9b416a9f4ca7cf5ac4d5f7143d67edde7f7d7326:
Merge branch 'master' of
Hi Bin,
On 12 December 2014 at 06:05, Bin Meng bmeng...@gmail.com wrote:
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v3:
- Move license
Hi Andrew,
Looks good. I don’t have a DDR capable board to test, but at first glance
it’s fine.
On Dec 1, 2014, at 14:59 , Andrew Gabbasov andrew_gabba...@mentor.com wrote:
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode
Hi Andrew,
On Dec 1, 2014, at 14:59 , Andrew Gabbasov andrew_gabba...@mentor.com wrote:
Since the driver doesn't work in 1.2V or 1.8V signaling level modes,
Dual Data Rate mode can be supported by the driver only if it is supported
by the card in regular 3.3V mode. So, check for a
Hi Andrew,
On Dec 1, 2014, at 14:59 , Andrew Gabbasov andrew_gabba...@mentor.com wrote:
The card_caps bit should denote the card capability to use DDR mode,
but we need the flag indicating that the DDR mode is active.
Signed-off-by: Andrew Gabbasov andrew_gabba...@mentor.com
---
Hi Andrew,
On Dec 1, 2014, at 14:59 , Andrew Gabbasov andrew_gabba...@mentor.com wrote:
Block length for write and read commands is fixed to 512 bytes
when the card is in Dual Data Rate mode. If block length read from CSD
is different, make sure the driver will use correct length
in all
Hi Diego,
On Dec 4, 2014, at 19:01 , Diego Santa Cruz diego.santac...@spinetix.com
wrote:
I have the need to hardware partition eMMC devices from U-Boot along
with setting enhanced and reliable write attributes.
This series of patches adds this support to U-Boot via a new mmc
API, a
Hi Tom,
The following changes since commit fc9b0b80435cda721fbdbe507c9e4f388b0ea62b:
Merge branch 'master' of git://git.denx.de/u-boot-usb (2014-12-11 18:40:49
-0500)
are available in the git repository at:
git://git.denx.de/u-boot-mmc.git master
for you to fetch changes up to
On Sun, 23 Nov 2014 14:43:14 +0100
Hans de Goede hdego...@redhat.com wrote:
Sorry for a late reply. I was not on CC for these patches and don't
properly keep track of the u-boot mailing list activity lately.
Allwinner tells us that this bit of code is the rtc ram being used to detect
coming
On Sun, 23 Nov 2014 14:43:13 +0100
Hans de Goede hdego...@redhat.com wrote:
The A31s only has one dram channel, so do not bother with trying to initialize
a second channel.
Signed-off-by: Hans de Goede hdego...@redhat.com
Ian Campbell has already noticed in the earlier review. In the case
On Sun, 23 Nov 2014 14:43:11 +0100
Hans de Goede hdego...@redhat.com wrote:
It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.
On 11/10/2014 10:10 PM, Zhao Qiang wrote:
Deep sleep for generic board is supported now,
and it use CONFIG_FSL_DEEP_SLEEP instead of CONFIG_DEEP_SLEEP,
so modify it for qe.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Qiang,
Can you rebase this patch and verify it on boards?
Hi Bin,
On 12 December 2014 at 06:05, Bin Meng bmeng...@gmail.com wrote:
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.
For more details, check
On Tue, Nov 18, 2014 at 3:44 AM, Guillaume GARDET
guillaume.gar...@free.fr wrote:
In SPL MMC, boot modes are exclusive. So, if MMCSD_MODE_RAW fails, the board
hangs. This patch allows to
try MMCSD_MODE_FS then, if available.
It has been tested on a pandaboard (rev. A3).
HI Guillaume,
What
Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR and the Primary GUID
Partition Table.
Additionally, prepare and write the Backup GUID Partition Table.
Signed-off-by: Steve Rae s...@broadcom.com
---
Changes in v4:
fix bug with
Signed-off-by: Steve Rae s...@broadcom.com
---
Changes in v4:
- move common code to static functions
Changes in v3: None
Changes in v2: None
disk/part_efi.c | 175 +---
1 file changed, 102 insertions(+), 73 deletions(-)
diff --git
Hi Simon,
On Sat, Dec 13, 2014 at 2:49 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 12 December 2014 at 06:05, Bin Meng bmeng...@gmail.com wrote:
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.
Hi Simon
On Sat, Dec 13, 2014 at 5:27 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 12 December 2014 at 06:05, Bin Meng bmeng...@gmail.com wrote:
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub),
Hi Marek,
On 12/12/2014 13:58, Marek Vasut wrote:
On Friday, December 12, 2014 at 01:43:22 PM, Stefan Roese wrote:
Hi Luca,
On 12.12.2014 13:40, Luca Ellero wrote:
On 10.12.2014 09:24, Luca Ellero wrote:
There is only one pio_word in this DMA transaction so data field must
be 1.
Hi Stefan,
On 12/12/2014 09:43, Stefan Roese wrote:
Hi Luca,
On 10.12.2014 09:24, Luca Ellero wrote:
There is only one pio_word in this DMA transaction so data field must
be 1.
Signed-off-by: Luca Ellero luca.ell...@brickedbrain.com
---
drivers/mtd/nand/mxs_nand.c |2 +-
1 file
88 matches
Mail list logo
