The current "simple" address translation simple_bus_translate() is not
working on some platforms (e.g. MVEBU). As here more complex "ranges"
properties are used in many nodes (multiple tuples etc). This patch
enables the optional use of the common fdt_translate_address() function
which handles
Hi Michael,
On 01/09/2015 23:58, Michael Heimpold wrote:
> Running mxsboot on a big-endian system produces a sd image which
> cannot be started by the i.MX28 ROM. It complains on the debug
> uart as following:
I confess that I never tested mxsboot and/or mkimage on a big endian
host. I am
From: Albert ARIBAUD
When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.
This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to
Generic function for spi-flash memory reading.
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/sf.c | 23 +++
drivers/mtd/spi/sf_internal.h | 3 +++
2 files changed, 26 insertions(+)
From: Hou Zhiqiang
The clear flag status register operation is required by Micron
SPI-NOR chips, which support FSR. And if an error bit of FSR
have been set like protection, voltage, erase, and program,
it must be cleared by the clear FSR operation.
Signed-off-by: Hou
Use flash_read directly instead of spi_flash_read_common.
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/sf_internal.h | 7 ---
drivers/mtd/spi/sf_ops.c | 25 +
2 files changed, 1
This patch uses flash_read_reg routine for all respective
read register calls.
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/sf_internal.h | 4 +--
drivers/mtd/spi/sf_ops.c | 63
spi_flash_cmd_read_status -> read_sr
spi_flash_cmd_read_config -> read_cr
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/sf_internal.h | 5 +
drivers/mtd/spi/sf_ops.c | 8
On Tue, 2015-09-01 at 10:52 +0200, Hans de Goede wrote:
> Hi,
>
> On 01-09-15 09:05, Ian Campbell wrote:
> > On Mon, 2015-08-31 at 17:42 +0200, Hans de Goede wrote:
> >> We know when u-boot is written to its own partition, in this case
> the
> >> layout always is:
> >>
> >> eb 0 spl
> >> eb 1
This series converts to use driver model for PCI/USB/ETH on Intel
Galileo board, as well as optimizing the boot time.
Boot time performance degradation is observed with the conversion
to use dm pci. Intel Quark SoC has a low end x86 processor with
only 400MHz frequency and the most time consuming
This board is equipped with a Micron NAND chip (MT29F1G08ABADAH4) that
needs 4-bit ECC. But the SPEAr600 only supports 1-bit HW ECC internally.
This patch enables the SW 4-bit BCH support for this board.
Signed-off-by: Stefan Roese
Cc: Viresh Kumar
---
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC strength.
The SPEAr600 HW ECC only supports 1-bit ECC strength.
To enable SW BCH4, you need to specify this in your config header:
And use the command
This patch adds the "nandecc" command to switch between the SPEAr600 internal
1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND
chips with a stronger ECC than 1-bit, as on the x600. And to dynamically
switch between both ECC schemes for backwards compatibility.
To reduce the size of the U-Boot image on the x600 board, lets enable
the THUMB mode. This reduces the overall size to less than 0x6000
bytes. Fitting it again in the onboard NOR flash.
Signed-off-by: Stefan Roese
Cc: Viresh Kumar
---
Convert to use DM version of Designware ethernet driver on Intel
quark/galileo.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v2: None
arch/x86/cpu/quark/quark.c | 19 ---
configs/galileo_defconfig | 2 +-
2 files
On 09/01/2015 07:03 PM, Paul Kocialkowski wrote:
> Le vendredi 28 août 2015 à 10:29 +0200, Andreas Bießmann a écrit :
>> The SOURCE_DATE_EPOCH mechanism for reproducible builds require some date(1)
>> with -d switch to print the relevant date and time strings of another point
>> of
>> time.
>>
>>
Add spi_flash_read_bar function for reading bar and discovering
bar commands at probe time.
Signed-off-by: Jagan Teki
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
Changes for v3:
- none
Changes for v2:
-
If computed bank_sel is same as flash->bank_curr which is
computed at probe time, then return the bank_sel instead of zero.
Signed-off-by: Jagan Teki
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
Changes for v3:
-
Optimized spi-flash bar writing code and also removed
unnecessary bank_sel in read_ops.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
Changes for v3:
-
BAR and spi_flash_cmd_wait_ready are updated to make more
module to add new status checks.
Hou Zhiqiang (1):
sf: Add clear flag status register support
Jagan Teki (12):
spi: zynq_spi: Remove unneeded headers
sf: Return bank_sel, if flash->bank_curr == bank_sel
sf: Make BAR discovery, as
Use the flash->flags for generic usage, not only for dm-spi-flash,
this will be used for future flag additions.
Signed-off-by: Jagan Teki
Cc: Bin Meng
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/sf_internal.h | 4
- Removed unneeded inclusion of header files
- Add "Xilinx" on license text
Signed-off-by: Jagan Teki
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
Changes for v3:
- none
Changes for v2:
- none
Generic function for all spi-flash register reads.
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/sf.c | 23 +++
drivers/mtd/spi/sf_internal.h | 3 +++
2 files changed, 26
Current flash wait_ready logic is not modular to add new
register status check, hence updated the status check for
adding few more register checks in future.
Below are the sf speed runs with 'sf update' on whole flash, 16MiB.
=> sf update 0x100 0x0 0x100
device 0 whole chip
16777216 bytes
This patch adds flag status register reading support to
spi_flash_cmd_wait_ready.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Marek Vasut
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Cc:
Hi Mchal,
On 1 September 2015 at 03:10, Michal Simek wrote:
> Hi Simon,
>
> On 08/28/2015 10:50 PM, Simon Glass wrote:
>> This series collects the previous RFT patches I sent out.
>>
>> https://patchwork.ozlabs.org/patch/508167/
>> https://patchwork.ozlabs.org/patch/508168/
>>
Add support for DENX MCV SoM, which is CycloneV based and the
associated DENX MCVEVK baseboard. The board can boot from eMMC.
Ethernet and USB is supported.
Signed-off-by: Marek Vasut
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/socfpga_cyclone5_mcvevk.dts |
Add support for Terasic SoCkit, which is CycloneV based board.
The board can boot either from SD/MMC or QSPI. Ethernet is also
supported.
Signed-off-by: Marek Vasut
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/socfpga_cyclone5_sockit.dts | 92 +
On Wednesday, September 02, 2015 at 09:42:03 AM, Stefano Babic wrote:
> Hi Michael,
>
> On 01/09/2015 23:58, Michael Heimpold wrote:
> > Running mxsboot on a big-endian system produces a sd image which
> > cannot be started by the i.MX28 ROM. It complains on the debug
>
> > uart as following:
>
On Tuesday, September 01, 2015 at 06:22:08 PM, Pantelis Antoniou wrote:
> Hi Marek,
Hi!
[...]
> >> So you suggest adding board_mmc_getcd() in several places in the mmc
> >> subsystem driver to detect removal of the SD card?
> >
> > H, I'm not sure about this one. Panto ?
>
> I’m fine with
On Wednesday, September 02, 2015 at 08:09:51 AM, Jagan Teki wrote:
> This patch adds flag status register reading support to
> spi_flash_cmd_wait_ready.
>
> Signed-off-by: Jagan Teki
> Cc: Simon Glass
> Cc: Marek Vasut
> Cc: Michal Simek
On Tuesday, September 01, 2015 at 11:37:20 PM, Dinh Nguyen wrote:
> On Tue, Sep 1, 2015 at 10:36 AM, Marek Vasut wrote:
> > On Tuesday, September 01, 2015 at 05:12:40 PM, Dinh Nguyen wrote:
> >> On 09/01/2015 03:33 AM, Marek Vasut wrote:
> >> > On Tuesday, September 01, 2015 at
On Wednesday, September 02, 2015 at 12:41:52 AM, dingu...@opensource.altera.com
wrote:
> From: Dinh Nguyen
>
> Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV
> based board. The board can boot from SD/MMC. Ethernet is also supported.
>
>
Move to driver model for USB on Intel Galileo.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v2:
- Update commit message to remove "USB not working" statement,
as in v2, full USB support has been added.
configs/galileo_defconfig | 2 ++
Move to driver model pci for Intel quark/galileo.
Signed-off-by: Bin Meng
Acked-by: Simon Glass
---
Changes in v2:
- Remove arch/x86/cpu/quark/pci.c completely
arch/x86/cpu/quark/Makefile | 1 -
arch/x86/cpu/quark/pci.c| 70
USB PHY needs to be properly initialized per Quark firmware writer
guide, otherwise the EHCI controller on Quark SoC won't work.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch to add USB PHY initialization support
arch/x86/cpu/quark/quark.c | 41
If we convert to use driver model pci on quark, we will encounter
some chicken and egg problems like below:
- To enable PCIe root ports, we need program some registers on the
message bus via pci bus. With driver model, the first time to
access pci bus, the pci enumeration process will be
Intel Quark SoC has a low end x86 processor with only 400MHz
frequency. Currently it takes about 15 seconds for U-Boot to
boot to shell and the most time consuming part is with MRC,
which is about 12 seconds. MRC programs lots of registers on
the SoC internal message bus indirectly accessed via
Introduce device_is_on_pci_bus() which can be utilized by driver
to test if a device is on a PCI bus.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch to add an inline API to test if a device is on a PCI bus
drivers/pci/pci-uclass.c | 4 ++--
include/pci.h
This adds static register programming for PCIe and USB after memory
init as required by Quark firmware writer guide. Although not doing
this did not cause any malfunction, just do it for safety.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch to add PCIe/USB static
The Designware ethernet controller is also seen on PCI bus, e.g.
on Intel Quark SoC. Add this support in the DM version driver.
Signed-off-by: Bin Meng
---
Changes in v2:
- Change to use device_is_on_pci_bus()
drivers/net/designware.c | 39
When building dm version of designware eth driver on a platform
with 64-bit phys_addr_t, it reports the following warnings:
drivers/net/designware.c: In function 'designware_eth_probe':
drivers/net/designware.c:599:2:
warning: format '%lx' expects argument of type 'long unsigned int',
Hi ED,
The setting can meet most needs of EP device.
It is similar with setting for RC mode which we assign 1G outbound space not
256M 512M ... 32G.
Thanks,
Minghuan
> -Original Message-
> From: Swarthout Edward L-SWARTHOU
> Sent: Wednesday, September 02, 2015 1:16 AM
> To: Sun
This series provides a fix necessary for early models of Utilite, a miniature
desktop based on CM-FX6. It implements a dynamic modification to the device tree
that is necessary for mmc boot.
Cc: Stefano Babic
Cc: Igor Grinberg
Nikita Kiryanov (3):
Introduce cl_eeprom_get_product_name() for obtaining product name
from the eeprom.
Cc: Stefano Babic
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov
---
board/compulab/common/eeprom.c | 19 +++
Add support for selecting which eeprom is queried for board revision by
extending cl_eeprom_get_board_rev() to accept an i2c bus number.
Cc: Stefano Babic
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov
---
Re-enabling OCRAM ECC can cause some value changes in SRAM. Just
clear fake interrupt status and keep other bits intact.
Signed-off-by: Jian Luo
---
arch/arm/mach-socfpga/spl.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git
Re-enabling OCRAM ECC can cause some value changes in SRAM. Just
clear fake interrupt status and keep other bits intact.
Signed-off-by: Jian Luo
---
Changes for v2:
- add CC to custodian
arch/arm/mach-socfpga/spl.c | 14 --
1 file changed, 8
Hi Tom,
On 2 September 2015 at 10:52, Tom Warren wrote:
> Simon, et al,
>
>> -Original Message-
>> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
>> Sent: Friday, August 14, 2015 3:05 AM
>> To: Bin Meng
>> Cc: Michal Suchanek; Tom Rini;
On Wednesday, September 02, 2015 at 07:02:55 PM, Jian Luo wrote:
> Re-enabling OCRAM ECC can cause some value changes in SRAM. Just
> clear fake interrupt status and keep other bits intact.
>
> Signed-off-by: Jian Luo
> ---
> Changes for v2:
> - add CC to
Hi Simon,
Apologies for the delay. I will try to rework this patch end of this
week and send it back to you middle of next week.
Best Regards
Christophe
Le 31/08/2015 00:45, Simon Glass a écrit :
Hi Chrisophe,
On 13 August 2015 at 09:55, Simon Glass wrote:
On 9 August
On Wednesday, September 02, 2015 at 04:18:24 PM, Dinh Nguyen wrote:
> On 9/2/15 3:18 AM, Marek Vasut wrote:
> > On Wednesday, September 02, 2015 at 12:41:52 AM,
> > dingu...@opensource.altera.com
> >
> > wrote:
> >> From: Dinh Nguyen
> >>
> >> Add support for the
Simon, et al,
> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: Friday, August 14, 2015 3:05 AM
> To: Bin Meng
> Cc: Michal Suchanek; Tom Rini; Stephen Warren; U-Boot Mailing List; Tom
> Warren; Thierry Reding
> Subject: Re: [U-Boot]
On Wed, Sep 02, 2015 at 09:08:48AM -0400, Tom Rini wrote:
> On Wed, Sep 02, 2015 at 02:07:41PM +0200, Simon Guinot wrote:
> > On Mon, Aug 31, 2015 at 07:16:16AM -0600, Simon Glass wrote:
> > > Hi Simon,
> > >
> > > On 31 August 2015 at 01:51, Simon Guinot
> > > wrote:
Hi!
this error comes again. It isn't a compiler error after all. :(
JTAG inspection shows that the problem is located in
arch/arm/mach-socfpga/spl.c line94.
It seems that re-enable ECC on OCRAM can cause some strange value
changes in SRAM.
Disabling ECC might also cause value changes, which
On 08/18/2015 02:35 PM, York Sun wrote:
> Convert MPC8540ADS, MPC8541CDS, MPC8544CDS, MPC8548CDS, MPC8555CDS,
> MPC8560ADS, MPC8568MDS, MPC8569MDS, MPC8610HPCD to use generic board
> structure.
>
> Signed-off-by: York Sun
>
Applied to u-boot-mpc85xx master. Awaiting
On 08/17/2015 03:31 PM, York Sun wrote:
> For e6500 and e5500 SoCs, it was intended to put init_ram address in
> ccsr reserved space. It is no longer true since SerDes module took the
> space. Move it to another reserved space at CCSR + 0x03c000.
>
> Signed-off-by: York Sun
On 08/17/2015 03:31 PM, York Sun wrote:
> MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write
> through cache on E6500. L2 cache is enabled to to hold the data. This
> patch locks/unlocks L2 cache to ensure no data cast out from L2 cache.
>
> Signed-off-by: York Sun
On 08/18/2015 06:47 AM, Igal.Liberman wrote:
> From: Igal Liberman
>
> Recently the FMan Port and MAC compatibles were changed.
> This patch aligns the FMan Port and MAC compatibles
> to the new FMan device tree binding document.
> The FMan device tree binding
Old revisions of Utilite (a miniature PC based on cm-fx6) do not have
a card detect for mmc, and thus the kernel needs to be told that
there's a persistent storage on usdhc3 to force it to probe the mmc
card.
Check the baseboard revision and modify the device tree accordingly
if needed.
Cc:
On 09/02/2015 09:05 AM, Simon Glass wrote:
> Hi York,
>
> On 1 September 2015 at 22:01, York Sun wrote:
>> FIT image supports more than 32 bits in addresses by using #address-cell
>> field. However the address length is not handled when parsing FIT images.
>> Beside, the
Tom,
The following changes since commit b7e84c93c450480ca4ff51ad2eb56bd83c1dc368:
Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2015-08-31 12:12:27
-0400)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
for you to fetch changes up to
From: Simon Guinot
On the LaCie boards netspace_max_v2 and net2big_v2, two internal hard
drives are available. Additionally on the d2net_v2 board, an extra hard
drive can be plugged via eSATA.
This patch updates CONFIG_SYS_IDE_MAXBUS and CONFIG_SYS_IDE_MAXDEVICE
On 08/21/2015 02:19 AM, Shengzhou Liu wrote:
> Per new requirement, change default core frequency
> from previous 1400MHz to 1200MHz to save power.
>
> Signed-off-by: Shengzhou Liu
Applied to u-boot-mpc85xx master. Awaiting upstream.
York
On 08/13/2015 12:22 PM, York Sun wrote:
> Previously the DDR4 targets were named with _D4. Rename them with
> _DDR4 for easy identification.
>
> Signed-off-by: York Sun
>
> ---
>
> Changes in v2:
> Drop changes for RDB boards because DDR4 version is actually
On 08/07/2015 10:41 AM, York Sun wrote:
> T1024QDS with DDR4 has been supported. Add the missing defconfig.
>
> Signed-off-by: York Sun
> CC: Shengzhou Liu
> ---
Applied to u-boot-mpc85xx master. Awaiting upstream.
York
Hi,
While testing U-Boot v2015.10-rc2 on the Kirkwood-based LaCie boards
I noticed that the autoboot counter is not decrementing. It stays stuck
at '3' endlessly. After some digging, I found out that this regression
is due to the commit: ade741b3896b1a3872ff74437f04b50762d05849
"arm: mvebu: Call
On Wednesday, September 02, 2015 at 08:59:57 PM, Marek Vasut wrote:
> On Wednesday, September 02, 2015 at 08:57:52 PM, Sinan Akman wrote:
> > On 02/09/15 10:18 AM, Dinh Nguyen wrote:
> > > On 9/2/15 3:18 AM, Marek Vasut wrote:
> > >> On Wednesday, September 02, 2015 at 12:41:52 AM,
> > >>
In 2178282 we accidentally dropped out hilsilicon and cm_t43. Bring
these back in.
Signed-off-by: Tom Rini
---
arch/arm/Kconfig |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index de0d6fb..5feef97 100644
--- a/arch/arm/Kconfig
Currently some uninitialized padding bytes are written to the output
file, as can be confirmed with valgrind:
$ valgrind tools/mksunxiboot spl/u-boot-spl.bin spl/sunxi-spl.bin
==5581== Syscall param write(buf) points to uninitialised byte(s)
==5581==at 0x4F0F940: __write_nocancel (in
On 09/02/2015 01:54 PM, Stephen Warren wrote:
> On 09/02/2015 01:39 PM, Tom Warren wrote:
>>
>>
>>> -Original Message-
>>> From: Stephen Warren
>>> Sent: Wednesday, September 02, 2015 1:05 PM
>>> To: Tom Warren; Simon Glass
>>> Cc: Bin Meng; Thierry Reding; Tom Rini; U-Boot Mailing List
On Tue, Sep 1, 2015 at 1:22 PM, Adrian Alonso wrote:
> + * Boot Device : one of
> + * spi/sd/nand/onenand, qspi/nor
> + */
> +
> +#ifdef CONFIG_SYS_BOOT_QSPI
This config option does not exist in mainline. Please remove it.
> +BOOT_FROM qspi
> +#elif
On Wed, 2015-09-02 at 12:32 +0200, ma...@denx.de wrote:
> On Tuesday, September 01, 2015 at 04:53:44 PM, Dinh Nguyen wrote:
> > On 09/01/2015 05:12 AM, Jaehoon Chung wrote:
> > > On 09/01/2015 06:10 PM, Chin Liang See wrote:
> > >> On Tue, 2015-09-01 at 11:01 +0200, ma...@denx.de wrote:
> > >>> On
At present malloc.h is included everywhere since it recently was added to
common.h in this commit:
4519668 mtd/nand/ubi: assortment of alignment fixes
This seems wasteful and unnecessary. We have been trying to trim down
common.h and put separate functions into separate header files and that
Now that we have a new header file for cache-aligned allocation, we should
move the stack-based allocation macro there also.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add a new patch to move ALLOC_CACHE_ALIGN_BUFFER() to the new header
board/raspberrypi/rpi/rpi.c |
> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Wednesday, September 02, 2015 4:44 PM
> To: Tom Warren; Simon Glass
> Cc: U-Boot Mailing List; Thierry Reding; Tom Rini
> Subject: Re: [U-Boot] [PATCH] Revert "fdt: Fix fdtdec_get_addr_size() for 64-
> bit"
Hi Simon,
On 02.09.2015 17:49, Simon Guinot wrote:
While testing U-Boot v2015.10-rc2 on the Kirkwood-based LaCie boards
I noticed that the autoboot counter is not decrementing. It stays stuck
at '3' endlessly. After some digging, I found out that this regression
is due to the commit:
Hi Simon,
On Wed, Sep 2, 2015 at 10:05 PM, Simon Glass wrote:
> Hi Bin,
>
> On 2 September 2015 at 03:17, Bin Meng wrote:
>> Quark SoC holds the PCIe controller in reset following a power on.
>> U-Boot needs to release the PCIe controller from reset. The
Hi Simon,
On Wed, Sep 2, 2015 at 10:05 PM, Simon Glass wrote:
> Hi Bin,
>
> On 2 September 2015 at 03:17, Bin Meng wrote:
>> USB PHY needs to be properly initialized per Quark firmware writer
>> guide, otherwise the EHCI controller on Quark SoC won't work.
Hi,
On 09/03/2015 09:27 AM, Chin Liang See wrote:
> On Wed, 2015-09-02 at 12:32 +0200, ma...@denx.de wrote:
[snip]
>
> Would want to hear more from Jaehoon as Exynos and SOCFPGA are the one
> setting up these values.
Since this approach is not based on dwmmc TRM, it's
Hi Simon,
On Wed, Sep 2, 2015 at 10:05 PM, Simon Glass wrote:
> Hi Bin,
>
> On 2 September 2015 at 03:17, Bin Meng wrote:
>> Intel Quark SoC has a low end x86 processor with only 400MHz
>> frequency. Currently it takes about 15 seconds for U-Boot to
>>
Hi Simon,
On Wed, Sep 2, 2015 at 10:05 PM, Simon Glass wrote:
> Hi Bin,
>
> On 2 September 2015 at 03:17, Bin Meng wrote:
>> The Designware ethernet controller is also seen on PCI bus, e.g.
>> on Intel Quark SoC. Add this support in the DM version driver.
In 2178282 this config wasn't updated by accident, so update it.
Signed-off-by: Tom Rini
---
configs/titanium_defconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index d286fd6..de3c78d 100644
---
Hi Simon,
I've just finished bisecting a build error for the mx23_olinuxino platform.
git bisect points to:
http://git.denx.de/?p=u-boot.git;a=commit;h=92a655c326b22de58dcd5371ca1a62fdc57f8e04
to build:
make ARCH=arm CROSS_COMPILE=${CC} distclean
make ARCH=arm CROSS_COMPILE=${CC}
Hi,
When using u-boot's HEAD built with GCC 5, it hangs on the memcpy()
after reading u-boot.img from MMC card.
Unfortunately I won't be able to spend a lot of time debugging this, so
I thought I'd report.
cheers
--
balbi
signature.asc
Description: Digital signature
On Wednesday, September 02, 2015 at 08:57:52 PM, Sinan Akman wrote:
> On 02/09/15 10:18 AM, Dinh Nguyen wrote:
> > On 9/2/15 3:18 AM, Marek Vasut wrote:
> >> On Wednesday, September 02, 2015 at 12:41:52 AM,
> >> dingu...@opensource.altera.com
> >>
> >> wrote:
> >>> From: Dinh Nguyen
Am 02.09.2015 um 16:51 schrieb Siarhei Siamashka:
On Wed, 2 Sep 2015 15:17:11 +0200
Bernhard Nortmann wrote:
This patch follows up on a discussion of ways to improve support
for the sunxi FEL ("USB boot") mechanism, especially with regard
to boot scripts, see:
* Add Clock control module (CCM) support
* iMX7D SoC introduces 3 main clock sysmtem abstraction for clock
root frequency generation denominated clock slices.
Core clock slice: hihg speed clock for ARM core
Bus clock slice: for bus clocks
IP clock slice: Peripheral clocks
* At system boot
* Add i.MX7D SABRESD target board support with enabled modules:
UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.
Build target: mx7dsabresd_config
Signed-off-by: Peng Fan
Signed-off-by: Fugang Duan
Signed-off-by: Ye.Li
Add imx-common cpu support for imx7d SoC
- Update reset_cause for imx7d
- Enable watchdog driver built for imx7d
Signed-off-by: Adrian Alonso
Signed-off-by: Peng Fan
---
Changes for V2: Split patch to easier review process
- Add system arch
Rework imx_set_wdog_powerdown to be reused by imx6 and imx7
Signed-off-by: Adrian Alonso
---
Changes for V2:
Rework for common sys_proto header file
Changes for V3: Resend
arch/arm/cpu/armv7/mx6/soc.c| 14 --
arch/arm/imx-common/init.c
Add imx7 SoC thermal driver support
Signed-off-by: Adrian Alonso
---
Changes for V2: Fix build error for missin macro check ;P
Changes for V3: Resend
Changes for V4: Resend
drivers/thermal/imx_thermal.c | 90 ---
1 file changed, 84
Add imx7d basic SoC system support
Misc arch dependent functions for system bring up
Signed-off-by: Adrian Alonso
Signed-off-by: Peng Fan
Signed-off-by: Ye.Li
---
Changes for V2: Split from patch imx: imx7d: initial arch
Move common imx6 arch init setup, init.c can be extended
and reused to support imx7 SoC keeping init arch common
code.
Signed-off-by: Adrian Alonso
---
Changes for V2: Resend
Changes for V3: Resend
arch/arm/cpu/armv7/mx6/soc.c| 87
Add helper macro is_soc_type to identify iMX SoC family
Signed-off-by: Adrian Alonso
---
Changes for V2: Rework for common sys_proto header file
Changes for V3: Rework for latest master
arch/arm/include/asm/arch-imx/cpu.h | 2 ++
Add system counter driver for imx7d and mx6ul
imx7 and imx6ul supports system counter timer as well as
GPT timer (arch/arm/imx-common/timer.c); The default for
imx7 is systemcounter timer.
Signed-off-by: Ye.Li
Signed-off-by: Adrian Alonso
---
Changes
Extend init_aips to support imx7 SoC, use is_soc_type
and is_cpu_type to resolve at run time aips3 settings
Signed-off-by: Adrian Alonso
---
Changes for V2: Resend
Changes for V3: Resend
arch/arm/imx-common/init.c | 44
1 file
Marek Vasut wrote:
On Wednesday, September 02, 2015 at 08:59:57 PM, Marek Vasut wrote:
On Wednesday, September 02, 2015 at 08:57:52 PM, Sinan Akman wrote:
On 02/09/15 10:18 AM, Dinh Nguyen wrote:
On 9/2/15 3:18 AM, Marek Vasut wrote:
On Wednesday, September 02, 2015 at 12:41:52 AM,
On 09/02/2015 09:52 AM, Tom Warren wrote:
> Simon, et al,
>
>> Simon Glass wrote at Friday, August 14, 2015 3:05 AM:
>> I plan to apply this revert to u-boot-x86 (where SPI is currently
>> broken) and (once it has a bit more testing) also this patch which I think
>> makes
>> the change in a
On Wed, Sep 2, 2015 at 4:48 PM, Robert Nelson wrote:
> I've just finished bisecting a build error for the mx23_olinuxino platform.
>
> git bisect points to:
>
> http://git.denx.de/?p=u-boot.git;a=commit;h=92a655c326b22de58dcd5371ca1a62fdc57f8e04
I think it has been fixed
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