On 2/19/24 9:03 PM, Roger Quadros wrote:
> Some platforms have bus level Reset controlled
> by a GPIO line. If available then handle bus reset
> via GPIO.
>
> Signed-off-by: Roger Quadros
> ---
> include/phy.h | 7 +++
> net/mdio-uclass.c | 37 -
>
Hi all,
Looks like this patch was already merged to u-boot/master
https://lore.kernel.org/all/20240109084551.21155-1-nsek...@ti.com/T/#md1fd66ff9f1cb93dfaa0dfb5f67d7452416e2cc2
Sorry for the spam!
On 22/02/24 12:15, Neha Malcom Francis wrote:
From: Sekhar Nori
An entry in memory map table
In the Makefile there is a line that says this:
# the checker needs the correct machine size
CHECKFLAGS += $(if $(CONFIG_64BIT),-m64,-m32)
So set CONFIG_64BIT so that we don't pass -m32 to the static checker.
Signed-off-by: Dan Carpenter
---
arch/arm/Kconfig | 4
1 file changed,
From: Sekhar Nori
An entry in memory map table for MMU configuration is spilling over and
inadvertently mapping DDR available at higher address (above 4GB address
space) as device memory (nGnRnE).
Fix this by adjusting entry size. Tested on AM62A SK by enabling
CONFIG_CMD_TIME. Before this
Hi Bob,
On 2/21/24 19:27, Bob Wolff wrote:
If mixed rsa and ecdsa keys are specified in
dtsi, an rsa key can be sent into the ecdsa
verify. Without the ecdsa,curve property, this
function will crash due to lack of checking
the null pointer return.
You can wrap commit messages at 75 characters
If mixed rsa and ecdsa keys are specified in
dtsi, an rsa key can be sent into the ecdsa
verify. Without the ecdsa,curve property, this
function will crash due to lack of checking
the null pointer return.
Signed-off-by: Bob Wolff
---
lib/ecdsa/ecdsa-verify.c | 5 +
1 file changed, 5
On Wed, Feb 21, 2024 at 04:43:28PM +0100, Igor Opaniuk wrote:
> On Tue, Feb 20, 2024 at 7:31 PM Francesco Dolcini
> wrote:
> >
> > + sysinfo {
> > + compatible = "toradex,sysinfo";
> > + };
> > +
> Have you considered introducing some common *-u-boot.dtsi include
> and
Hi Quentin,
On 2024-02-21 19:18, Quentin Schulz wrote:
> Hi Jonas,
>
> On 2/17/24 19:35, Jonas Karlman wrote:
>> Port the RK3399 part of the Rockchip IO-domain driver from linux.
>>
>> This differs from linux version in that pmu io iodomain bit is enabled
>> in the write ops instead of in an
Hi Jonas,
On 2/17/24 19:35, Jonas Karlman wrote:
Port the RK3399 part of the Rockchip IO-domain driver from linux.
This differs from linux version in that pmu io iodomain bit is enabled
in the write ops instead of in an init ops as in linux, this way we can
avoid keeping a full state of all
Yo,
I mentioned this last night to Heinrich on IRC, supports_extension() is
broken for ISA strings longer than 32 characters. M-Mode U-Boot doesn't
parse a devicetree, so this doesn't apply there, but for S-mode
supports_extension() looks like:
static inline bool supports_extension(char ext)
{
Commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.
Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.
Signed-off-by: Fabio Estevam
---
From: Quentin Schulz
ADC support is implied by the Rockchip arch Kconfig but that means it
should be possible to disable ADC support and still be able to build.
However the weak implementation of rockchip_dnl_key_pressed() currently
blindly use functions from the ADC subsystem which do not
From: Quentin Schulz
The ADC controller drivers are obviously all depending on ADC symbol
being selected.
While they don't seem to fail to build without, they won't be useful
without that symbol selected, so let's make sure the options aren't
shown in menuconfig when ADC isn't selected.
Cc:
From: Quentin Schulz
The SARADC is used on Jaguar for multiple things:
- channel 0 is used (at runtime) as a BIOS button,
- channel 2 is exposed on the Mezzanine connector for customer specific
logic,
- channel 5 and 6 are used for identification,
Since the SARADC requires a vref-supply
From: Quentin Schulz
The BUTTON_ADC symbol guards the compilation of button-adc driver whose
name very well makes it explicit that it requires ADC support to be
enabled.
Fix build issue of button-adc driver when ADC support isn't enabled by
making sure it cannot be built without ADC support.
From: Quentin Schulz
This adds support for the SARADCv2 found on RK3588.
There is no stop callback as it is currently configured in single
conversion mode, where the ADC is powered down after a single conversion
has been made.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
From: Quentin Schulz
SARADC v1 and v2 have a different way of reading data, therefore let's
abstract this function so that it can be provided from the udevice.data
pointer.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
drivers/adc/rockchip-saradc.c | 37
From: Quentin Schulz
SPL_PMIC_RK8XX and PMIC_RK8XX both share the same prompt making it
difficult to know at first glance in menuconfig what's for what, let's
fix this by adding "in SPL" at the end of the prompt for the SPL symbol.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
From: Quentin Schulz
SARADC v2 doesn't have a stop mechanism once in single mode. In series
conversion, the logic is different anyway. Therefore, let's abstract
this function so that it can be provided from the udevice.data pointer.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
From: Quentin Schulz
The registers are entirely different between SARADC v1 and SARADC v2, so
let's prepare to add another struct for accessing v2 registers by adding
a union.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
drivers/adc/rockchip-saradc.c | 23 +--
1
From: Quentin Schulz
SARADC v1 and v2 have a different way of starting a channel, therefore
let's abstract this function so that it can be provided from the
udevice.data pointer.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
drivers/adc/rockchip-saradc.c | 30
From: William Wu
On RK809 in PMIC_POWER_ENX registers, in order to set or clear a bit N,
the bit at offset N + 4 needs to be set otherwise nothing is done.
This fixes the inability to modify the SWITCH state on RK809.
Cc: Quentin Schulz
Signed-off-by: William Wu
[reworded commit log]
From: Quentin Schulz
This adds support for RK806, only the SPI variant has been tested.
The communication "protocol" over SPI is the following:
- write three bytes:
- 1 byte: [0:3] length of the payload, [6] Enable CRC, [7] Write
- 1 byte: LSB register address
- 1 byte: MSB register
From: Quentin Schulz
By passing a rk8xx_reg_info directly to the internal get_value, it'd be
possible to call this same function with a logic for getting the
rk8xx_reg_info different from the current get_ldo_reg, e.g. for NLDO and
PLDO support for RK806.
No logic change is expected.
Cc:
From: Quentin Schulz
Reword the help text for the pmic read and pmic write commands to better
match what's expected from the user.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
cmd/pmic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cmd/pmic.c b/cmd/pmic.c
From: Quentin Schulz
Those two functions had their last user removed in commit f9c68a566c4d
("rockchip: phycore_rk3288: remove phycore_init() function") part of
v2023.01 release, so let's do some cleanup here.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
From: Quentin Schulz
The read-only mode is currently supported but only for 16b-aligned
buffers. For unaligned buffers, the last byte will be read in RW mode
right now, which isn't what is desired. Instead, let's put the
controller back into RO mode for that last byte and skip any write in
the
-boot/20240221-jaguar-v3-0-1f256a822...@theobroma-systems.com/T/#t
because of:
- remove of asm/io.h include in favor of asm/arch-rockchip/hardware.h
(both should be included if applied before the dependency)
- Jaguar defconfig modified in this patch series is added in the
aforementioned patch
On 2/21/24 08:25, Janne Grunau via B4 Relay wrote:
From: Janne Grunau
Discovered while trying to use the second interface in the USB keyboard
driver necessary on Apple USB keyboards.
Signed-off-by: Janne Grunau
---
drivers/usb/host/xhci-ring.c | 5 +
1 file changed, 5 insertions(+)
On 2/21/24 08:25, Janne Grunau via B4 Relay wrote:
From: Hector Martin
We currently only support one USB keyboard device, but some devices
emulate keyboards for other purposes. Most commonly, people run into
this with Yubikeys, so let's ignore those.
Even if we end up supporting multiple
On 2/21/24 08:25, Janne Grunau via B4 Relay wrote:
From: Janne Grunau
Those keyboards do not return the current device state. Polling will
timeout unless there are key presses. This is not a problem during
operation but the inital device state query during probing will fail.
Skip this step in
On 2/21/24 08:25, Janne Grunau via B4 Relay wrote:
From: Janne Grunau
Apple USB keyboards carry the HID keyboard boot protocol on the second
interface. Using the second interface in the USB keyboard driver does
not work since the xhci has not allocated a transfer ring.
So, what does this
On 2/21/24 08:25, Janne Grunau via B4 Relay wrote:
From: Janne Grunau
In the next step endpoints for multiple interfaces are set up. Move most
of the per endpoint initialization to separate function to avoid another
identation level.
Signed-off-by: Janne Grunau
Reviewed-by: Marek Vasut
Hello Francesco,
On Tue, Feb 20, 2024 at 7:31 PM Francesco Dolcini wrote:
>
> From: Emanuele Ghidoli
>
> This commit introduces support for the Toradex sysinfo driver in U-Boot,
> which uses information from Toradex config block to print correct
> board model.
> In case the Toradex config block
On Wed, Feb 21, 2024 at 02:24:23PM +, Marcel Ziswiler wrote:
> Hi Tom
>
> On Wed, 2024-02-21 at 08:10 -0500, Tom Rini wrote:
> > On Tue, Feb 20, 2024 at 07:51:35PM +, Marcel Ziswiler wrote:
> > > On Tue, 2024-02-20 at 21:14 +0200, Svyatoslav Ryhel wrote:
> > > > вт, 20 лют. 2024 р. о
On Wed, Feb 21, 2024 at 09:18:51AM +, Marcel Ziswiler wrote:
> On Wed, 2024-02-21 at 08:55 +0100, Francesco Dolcini wrote:
> > On Tue, Feb 20, 2024 at 06:40:56PM +0530, Sumit Garg wrote:
> > > Also, enable reset driver which is a prerequisite for PCIe support.
> > >
> > > Signed-off-by: Sumit
Hi Tom
On Wed, 2024-02-21 at 08:10 -0500, Tom Rini wrote:
> On Tue, Feb 20, 2024 at 07:51:35PM +, Marcel Ziswiler wrote:
> > On Tue, 2024-02-20 at 21:14 +0200, Svyatoslav Ryhel wrote:
> > > вт, 20 лют. 2024 р. о 20:29 Francesco Dolcini пише:
> > > >
> > > > From: Emanuele Ghidoli
> > > >
ring_idx was not correctly assigned in case of tflow_id is zero.
Which leads to wrong pairing of DMA for drivers like OSPI.
Fixes: 4312a1dfca26 ("dma: ti: k3-udma: Use ring_idx to pair k3 nav rings")
Reviewed-by: Jai Luthra
Signed-off-by: Udit Kumar
---
Changelog
Changes in v2
- Removed
On Wed, 21 Feb 2024, 11:30 Bob Wolff, wrote:
> Hi there,
> I have two separate but related pull requests I'd like to contribute. They
> both have to do with ECDSA support.
> - The simple one is a lack of null-pointer check that can cause a crash in
> certain situations. Easy peasy.
>
Just send
On 2/21/24 14:15, Adam Ford wrote:
On Wed, Feb 21, 2024 at 6:27 AM Marek Vasut wrote:
On 2/21/24 13:12, Sumit Garg wrote:
On Wed, 21 Feb 2024 at 16:11, Marek Vasut wrote:
On 2/21/24 10:18, Marcel Ziswiler wrote:
Hi Sumit
On Wed, 2024-02-21 at 08:55 +0100, Francesco Dolcini wrote:
Hello
On Wed, Feb 21, 2024 at 6:27 AM Marek Vasut wrote:
>
> On 2/21/24 13:12, Sumit Garg wrote:
> > On Wed, 21 Feb 2024 at 16:11, Marek Vasut wrote:
> >>
> >> On 2/21/24 10:18, Marcel Ziswiler wrote:
> >>> Hi Sumit
> >>>
> >>> On Wed, 2024-02-21 at 08:55 +0100, Francesco Dolcini wrote:
> Hello
On Tue, Feb 20, 2024 at 07:51:35PM +, Marcel Ziswiler wrote:
> On Tue, 2024-02-20 at 21:14 +0200, Svyatoslav Ryhel wrote:
> > вт, 20 лют. 2024 р. о 20:29 Francesco Dolcini пише:
> > >
> > > From: Emanuele Ghidoli
> > >
> > > This commit introduces support for the Toradex sysinfo driver in
On Mon, 12 Feb 2024 13:47:15 -0600, Nishanth Menon wrote:
> Hopefully the last time. Apologies on the screw ups. Ran CI loop[1] to be
> doubly sure that I have'nt yet again fat fingered something.
>
> This is a wide cleanup to switch to setting fdtfile using env_set
> instead of scripted magic.
The "bootflow" command currently doesn't support scanning a single
partition. This is inconvenient in setups with multiple bootable
partitions within a single disk, but only one is desired.
Support scanning a single disk partition. Specifically, support the
syntax:
bootflow scan mmc1:4
On 2/21/24 13:12, Sumit Garg wrote:
On Wed, 21 Feb 2024 at 16:11, Marek Vasut wrote:
On 2/21/24 10:18, Marcel Ziswiler wrote:
Hi Sumit
On Wed, 2024-02-21 at 08:55 +0100, Francesco Dolcini wrote:
Hello Sumit,
On Tue, Feb 20, 2024 at 06:40:56PM +0530, Sumit Garg wrote:
Also, enable reset
On Wed, 21 Feb 2024 at 16:11, Marek Vasut wrote:
>
> On 2/21/24 08:55, Francesco Dolcini wrote:
> > Hello Sumit,
> >
> > On Tue, Feb 20, 2024 at 06:40:56PM +0530, Sumit Garg wrote:
> >> Also, enable reset driver which is a prerequisite for PCIe support.
> >>
> >> Signed-off-by: Sumit Garg
> >>
On Wed, 21 Feb 2024 at 16:11, Marek Vasut wrote:
>
> On 2/21/24 10:18, Marcel Ziswiler wrote:
> > Hi Sumit
> >
> > On Wed, 2024-02-21 at 08:55 +0100, Francesco Dolcini wrote:
> >> Hello Sumit,
> >>
> >> On Tue, Feb 20, 2024 at 06:40:56PM +0530, Sumit Garg wrote:
> >>> Also, enable reset driver
Distro boot scripts are deprecated. Use standard boot instead.
Signed-off-by: Nam Cao
---
configs/starfive_visionfive2_defconfig | 2 +-
include/configs/starfive-visionfive2.h | 14 +-
2 files changed, 2 insertions(+), 14 deletions(-)
diff --git
Hi Bob,
On Wed, Feb 21, 2024 at 8:30 AM Bob Wolff wrote:
>
> Hi there,
> I have two separate but related pull requests I'd like to contribute. They
> both have to do with ECDSA support.
> - The simple one is a lack of null-pointer check that can cause a crash in
> certain situations. Easy peasy.
Hi there,
I have two separate but related pull requests I'd like to contribute. They
both have to do with ECDSA support.
- The simple one is a lack of null-pointer check that can cause a crash in
certain situations. Easy peasy.
- The less simple one (and hopefully not too controversial) adds an
Hi,
On Wed, 21 Feb 2024 at 10:19, Marcel Ziswiler
wrote:
>
> Hi Sumit
>
> On Wed, 2024-02-21 at 08:55 +0100, Francesco Dolcini wrote:
> > Hello Sumit,
> >
> > On Tue, Feb 20, 2024 at 06:40:56PM +0530, Sumit Garg wrote:
> > > Also, enable reset driver which is a prerequisite for PCIe support.
> >
Hi Udit,
Subject: Re: [PATCH] dma: ti: k3-udma: Fix ring_idx to pair k3 nav
rings"
Trailing quote in the subject
On Feb 21, 2024 at 12:58:25 +0530, Udit Kumar wrote:
> ring_idx was not correctly assigned in case of tflow_id is zero.
> Which leads to wrong pairing of DMA for drivers like OSPI.
Hi dan
This might be because I used the checkpatch.pl script.
Here's one without it.
Niek
=START PATCH ===
From de056f510156a2fa1b4b439e1fa1f44516aa8add Mon Sep 17 00:00:00 2001
From: Niek Nooijens
Date: Tue, 20 Feb 2024 13:42:57 +0900
Subject:
From: Quentin Schulz
There's only one user of rockchip_capsule_update_board_setup, which is
in board.c, and only one board defines it, so instead of having a header
only for one function symbol, let's just use a weak symbol instead.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Reviewed-by:
From: Quentin Schulz
This migrates the plaintext README in
board/theobroma-systems/puma_rk3399 to doc/board/theobroma-systems and
while doing so, update the instructions and rewrite it in rST.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
On 2/21/24 07:17, Sumit Garg wrote:
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote:
On 2/20/24 14:10, Sumit Garg wrote:
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.
Signed-off-by: Sumit Garg
Is this based
On 2/21/24 07:25, Sumit Garg wrote:
[...]
+static int wait_link_up(struct pcie_dw_imx8 *priv)
+{
+ unsigned long timeout;
+
+ timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
wait_for_bit() or read_poll_timeout()
They won't appropriately fit here as I would like to add delay in
On 2/21/24 06:25, Sumit Garg wrote:
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote:
On 2/20/24 14:10, Sumit Garg wrote:
pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
rather tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6
On 2/21/24 10:18, Marcel Ziswiler wrote:
Hi Sumit
On Wed, 2024-02-21 at 08:55 +0100, Francesco Dolcini wrote:
Hello Sumit,
On Tue, Feb 20, 2024 at 06:40:56PM +0530, Sumit Garg wrote:
Also, enable reset driver which is a prerequisite for PCIe support.
Signed-off-by: Sumit Garg
---
On 2/21/24 07:14, Sumit Garg wrote:
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote:
On 2/20/24 14:10, Sumit Garg wrote:
PCIe PHY can use it when there is no external refclock provided.
Commit message needs to be fixed.
How about the following?
Expose high performance PLL clock, so
From: Quentin Schulz
The original link returns a custom 404, so let's point to a link that
works today instead.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
board/theobroma-systems/ringneck_px30/MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 2/21/24 08:55, Francesco Dolcini wrote:
Hello Sumit,
On Tue, Feb 20, 2024 at 06:40:56PM +0530, Sumit Garg wrote:
Also, enable reset driver which is a prerequisite for PCIe support.
Signed-off-by: Sumit Garg
---
configs/verdin-imx8mp_defconfig | 9 +
1 file changed, 9
From: Quentin Schulz
This migrates the plaintext README in
board/theobroma-systems/ringneck_px30 to doc/board/theobroma-systems and
while doing so, update the instructions and rewrite it in rST.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
From: Quentin Schulz
There are multiple Device Trees in U-Boot git repo for Puma, so let's
make the MAINTAINERS entry match them all.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
board/theobroma-systems/puma_rk3399/MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 2/21/24 07:01, Sumit Garg wrote:
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote:
On 2/20/24 14:10, Sumit Garg wrote:
Pre-requisite to enable PCIe support on iMX8MP SoC.
This commit message is useless, write a proper one.
How about the following?
Add support for GPCv2 power
On 2/21/24 06:40, Sumit Garg wrote:
On Tue, 20 Feb 2024 at 21:02, Marek Vasut wrote:
On 2/20/24 14:10, Sumit Garg wrote:
Pre-requisite to enable PCIe support on iMX8MP SoC.
Please write a proper commit message .
How about the following?
Add support for i.MX8MP reset controller. It
From: Quentin Schulz
JAGUAR is a Single-Board Computer (SBC) based around the rk3588 SoC and
is targeting Autonomous Mobile Robots (AMR).
It features:
* LPDDR4X (up to 16GB)
* 1Gbps Ethernet on RJ45 connector (KSZ9031 or KSZ9131)
* PCIe 3.0 4-lane on M.2 M-key connector
* PCIe 2.1 1-lane on
From: Quentin Schulz
Rockchip SoCs have some jtag/sdmmc autoswitching that simply doesn't
work really well.[00] The Linux kernel disables it for all SoCs[01], so
U-Boot needs to do the same in order to fix issues related to SD card on
RK3588. This autoswitching is enabled (by default) via the
From: Quentin Schulz
The functions aren't used anywhere else than in board.c, therefore,
let's not expose them anymore at all.
This merges misc.c and board.c together and removes the functions from
the misc.h header file.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by: Quentin
From: Quentin Schulz
Since commit 9e644284ab81 ("dm: core: Report bootph-pre-ram/sram node as
pre-reloc after relocation"), bootph-pre-ram doesn't make U-Boot proper
bind the device before relocation.
While this is usually not much of an issue, it is when there's a lookup
for devices by code
From: Quentin Schulz
The different macros use writel which is defined in asm/io.h, so let's
include the header so users of hardware.h do not need to include
asm/io.h as well.
While at it, remove asm/io.h includes wherever
asm/arch-rockchip/hardware.h is included already.
Cc: Quentin Schulz
From: Quentin Schulz
It's one thing to have the register mapped via a well-defined struct but
it's another to be able to make use of it. For that to happen, one needs
to cast the physical address memory of the beginning of the register
address space with the struct. Since this cannot change,
From: Quentin Schulz
hardware.h is only defining macros which are "wrappers" around writel().
writel() is however not available in hardware.h, needs to be
included. This means in order to use the wrappers in hardware.h, one
also needs to include the header.
However, this cannot be done
From: Quentin Schulz
Only setup_iodomain() differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Reviewed-by: Dragan Simic
Reviewed-by:
From: Quentin Schulz
Only setup_boottargets differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by: Quentin Schulz
---
From: Quentin Schulz
Only setup_iodomain() differs from the original misc_init_r from
Rockchip mach code, so let's use rockchip_early_misc_init_r instead of
reimplementing the whole misc_init_r from Rockchip.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by: Quentin Schulz
---
From: Quentin Schulz
Only setup_iodomain() and setup_boottargets differ from the original
misc_init_r from Rockchip mach code, so let's use
rockchip_early_misc_init_r instead of reimplementing the whole
misc_init_r from Rockchip.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by:
From: Quentin Schulz
Compared to the original misc_init_r from Rockchip mach code,
setup_iodomain() is added and rockchip_setup_macaddr() is not called.
It is assumed adding rockchip_setup_macaddr() back is fine.
Let's use rockchip_early_misc_init_r instead of reimplementing the whole
From: Quentin Schulz
Compared to the original misc_init_r from Rockchip mach code,
setup_iodomain() is added and rockchip_setup_macaddr() is not called.
It is assumed adding rockchip_setup_macaddr() back is fine.
Let's use rockchip_early_misc_init_r instead of reimplementing the whole
This adds all the necessary bits for adding support for Theobroma's new
SBC.
JAGUAR is a Single-Board Computer (SBC) based around the rk3588 SoC and
is targeting Autonomous Mobile Robots (AMR).
It features:
* LPDDR4X (up to 16GB)
* 1Gbps Ethernet on RJ45 connector (KSZ9031 or KSZ9131)
* PCIe
From: Quentin Schulz
Most Rockchip boards who override misc_init_r do it only to call another
function and keep the rest unchanged. Therefore to allow for less
duplication, let's just add a weak function symbol that is called inside
misc_init_r.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
From: Quentin Schulz
The expected length of the cpuid, as passed with cpuid_length,
determines the size of cpuid_str string. Therefore, care should be taken
to make sure nothing is accessing data out-of-bounds.
Instead of using hardcoded values, derive them from cpuid_length.
Cc: Quentin
On Wed, 21 Feb 2024 at 15:06, Fathi Boudra wrote:
>
> Hi,
>
> On Wed, 21 Feb 2024 at 10:19, Marcel Ziswiler
> wrote:
> >
> > Hi Sumit
> >
> > On Wed, 2024-02-21 at 08:55 +0100, Francesco Dolcini wrote:
> > > Hello Sumit,
> > >
> > > On Tue, Feb 20, 2024 at 06:40:56PM +0530, Sumit Garg wrote:
> >
On Wed, 21 Feb 2024 at 14:19, Neil Armstrong wrote:
>
> On 20/02/2024 06:56, Sumit Garg wrote:
> > On Fri, 16 Feb 2024 at 02:22, Caleb Connolly
> > wrote:
> >>
> >> Some platforms hard reset when attempting to configure PMIC GPIOs. Add
> >> support for quirks specified in match data with a
On 21.02.24 10:10, Francesco Dolcini wrote:
> Hello Jan,
>
> On Mon, Feb 19, 2024 at 07:37:55PM +0100, Jan Kiszka wrote:
>> My personal observation is that continuous integration testings with
>> all-upstream components is not really a common thing. I saw that with
>> multiple active SoCs from
Hi Sumit
On Wed, 2024-02-21 at 08:55 +0100, Francesco Dolcini wrote:
> Hello Sumit,
>
> On Tue, Feb 20, 2024 at 06:40:56PM +0530, Sumit Garg wrote:
> > Also, enable reset driver which is a prerequisite for PCIe support.
> >
> > Signed-off-by: Sumit Garg
> > ---
> >
Hello Jan,
On Mon, Feb 19, 2024 at 07:37:55PM +0100, Jan Kiszka wrote:
> My personal observation is that continuous integration testings with
> all-upstream components is not really a common thing. I saw that with
> multiple active SoCs from various vendors.
With some limitation we have this
Hi Niek,
Thanks for the patch. The reason it's hard for us to apply it, is that
this patch seems copy-pasted on an email.
Instead, you should follow the guidelines here [0]. Till you get this
sorted, do you have it on a git branch somewhere, so I can cherry-pick
it and run it through the CI?
On 20/02/2024 06:56, Sumit Garg wrote:
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly wrote:
Some platforms hard reset when attempting to configure PMIC GPIOs. Add
support for quirks specified in match data with a single quirk to skip
this configuration. We rely on the GPIO already be
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