[PATCH] FSL DDR: Errata A009942 clears board cpo_sample

LSB in debug_28 register is cleared here so previous setting by errata A009942 is lost. Save and restore LSB in debug_28 Signed-off-by: Joakim Tjernlund --- drivers/ddr/fsl/fsl_ddr_gen4.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl

Re: [PATCH v2 00/11] Misc fixes + 8xx CPM relocation

On Fri, 2023-05-05 at 12:51 +0200, Christophe Leroy wrote: > This series adds misc fixes for cssi boards and activates > CPM relocation in order to enable the use of SCC4 in > QMC (QUICC Multi-Channel) mode. > > Changes in v2: > - Patch 5: Update r1 at once (From Joakim) Thanks Joakim

Re: [PATCH 05/10] powerpc: mpc8xx: Reorganise init RAM

On Thu, 2023-05-04 at 10:17 +, Christophe Leroy wrote: > > Le 04/05/2023 à 12:07, Joakim Tjernlund a écrit : > > On Thu, 2023-05-04 at 10:56 +0200, Christophe Leroy wrote: > > > Using SMC relocation microcode patch or USB-SOF microcode patch > > > will di

Re: [PATCH 05/10] powerpc: mpc8xx: Reorganise init RAM

On Thu, 2023-05-04 at 10:56 +0200, Christophe Leroy wrote: > Using SMC relocation microcode patch or USB-SOF microcode patch > will disable DPRAM memory from 0x2000 to 0x2400 and from 0x2f00 > to 0x3000. > > At the time being, init RAM is setup to use 0x2800-0x2e00, but > the stack pointer goes

Re: PRAM and reserved memory for Linux

On Wed, 2022-07-13 at 10:21 -0400, Tom Rini wrote: > On Wed, Jul 13, 2022 at 10:08:38AM +0000, Joakim Tjernlund wrote: > > > I added CONFIG_PRAM 4 and a reserved-memory DTS node for the same space but > > now u-boot complains when booting: > > ERROR: reserving fdt me

PRAM and reserved memory for Linux

I added CONFIG_PRAM 4 and a reserved-memory DTS node for the same space but now u-boot complains when booting: ERROR: reserving fdt memory region failed (addr=703ff000 size=1000) The error is caused by arch_lmb_reserve() in arm which seem to reserve command line and board info ? If I remove

[PATCH] ns16550: Respect CONFIG_BAUDRATE < 0 in _debug_uart_init

CONFIG_BAUDRATE less than 0 means do not touch baudrate settings. Signed-off-by: Joakim Tjernlund --- drivers/serial/ns16550.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 702109b23b..286d8aecca

Re: ARM A53 and initial MMU mapping for EL0/1/2/3 ?

I can see CNTVCT_EL0 counting in u-boot and I can see the relative timestamp in dmesg cont but timeofday is not moving, very odd. COUNTER_FREQUENCY is also there and correct. Jocke From: Andre Przywara Sent: 17 March 2022 01:32 To: Joakim Tjernlund Cc

Re: ARM A53 and initial MMU mapping for EL0/1/2/3 ?

32 bit user space with musl libc. Since I boot/reset directly into u-boot I guess I have forgotten to configure something. Any ideas? Jocke On Thu, 2022-02-17 at 15:13 +, Andre Przywara wrote: > On Fri, 11 Feb 2022 17:00:48 + > Joakim Tjernlund wrote: > > Hi, > >

Re: ARM A53 and initial MMU mapping for EL0/1/2/3 ?

On Thu, 2022-02-17 at 15:13 +, Andre Przywara wrote: > On Fri, 11 Feb 2022 17:00:48 + > Joakim Tjernlund wrote: > > Hi, > > > On Fri, 2022-02-11 at 15:00 +0100, Joakim Tjernlund wrote: > > > On Fri, 2022-02-11 at 01:26 +, Andre Przywara wrote: > &

Re: ARM A53 and initial MMU mapping for EL0/1/2/3 ?

On Fri, 2022-02-11 at 15:00 +0100, Joakim Tjernlund wrote: > On Fri, 2022-02-11 at 01:26 +, Andre Przywara wrote: > > On Fri, 11 Feb 2022 00:22:25 + > > Joakim Tjernlund wrote: > > > > > On Thu, 2022-02-10 at 22:43 +, Andre Przywara wrote: > > &g

Re: ARM A53 and initial MMU mapping for EL0/1/2/3 ?

On Fri, 2022-02-11 at 01:26 +, Andre Przywara wrote: > On Fri, 11 Feb 2022 00:22:25 + > Joakim Tjernlund wrote: > > > On Thu, 2022-02-10 at 22:43 +, Andre Przywara wrote: > > > On Thu, 10 Feb 2022 21:58:30 +0000 > > > Joakim Tjernlund wrote: > &g

Re: ARM A53 and initial MMU mapping for EL0/1/2/3 ?

On Thu, 2022-02-10 at 22:43 +, Andre Przywara wrote: > On Thu, 10 Feb 2022 21:58:30 + > Joakim Tjernlund wrote: > > Hi, > > > On Thu, 2022-02-10 at 10:22 +, Andre Przywara wrote: > > > On Wed, 9 Feb 2022 12:03:47 + > > > J

Re: ARM A53 and initial MMU mapping for EL0/1/2/3 ?

On Thu, 2022-02-10 at 10:22 +, Andre Przywara wrote: > On Wed, 9 Feb 2022 12:03:47 + > Joakim Tjernlund wrote: > > Hi, > > > On Wed, 2022-02-09 at 10:45 +, Andre Przywara wrote: > > > On Wed, 9 Feb 2022 08:35:04 + > > > J

Re: ARM A53 and initial MMU mapping for EL0/1/2/3 ?

On Wed, 2022-02-09 at 13:13 +, Andre Przywara wrote: > On Wed, 9 Feb 2022 14:05:57 +0100 > Michael Walle wrote: > > Hi, > > > > > The problem I have is that I boot a custom SOC into u-boot and when > > > > u-boot tries > > > > to boot linux I get an error exception when u-boot calls > >

Re: ARM A53 and initial MMU mapping for EL0/1/2/3 ?

On Wed, 2022-02-09 at 10:45 +, Andre Przywara wrote: > On Wed, 9 Feb 2022 08:35:04 + > Joakim Tjernlund wrote: > > Hi, > > > On Wed, 2022-02-09 at 00:33 +, Andre Przywara wrote: > > > On Tue, 8 Feb 2022 22:05:00 + > > > Joakim T

Re: ARM A53 and initial MMU mapping for EL0/1/2/3 ?

On Wed, 2022-02-09 at 00:33 +, Andre Przywara wrote: > On Tue, 8 Feb 2022 22:05:00 + > Joakim Tjernlund wrote: > > Hi Joakim, > > > Trying to figure out how I should map the MMU for normal RAM so it acessible > > from all ELx security states. > >

ARM A53 and initial MMU mapping for EL0/1/2/3 ?

Trying to figure out how I should map the MMU for normal RAM so it acessible from all ELx security states. So far I have this mem_map: /* memory mapped RAM. 32MB */ .virt = 0x6000UL, .phys = 0x6000UL, .size = 0x0200UL,

Re: [PATCH] fw_setenv: Unbreak fw_setenv caused by buggy MEMISLOCKED use

On Sun, 2021-12-19 at 14:20 +, Ivan Mikhaylov wrote: > On Sat, 2021-12-18 at 18:23 +0000, Joakim Tjernlund wrote: > > Ping? > > Maybe just revert commit 8a726b852502 ("fw_setenv: lock the flash > > only if it was locked before") ? > > > > __

Re: [PATCH] fw_setenv: Unbreak fw_setenv caused by buggy MEMISLOCKED use

Ping? Maybe just revert commit 8a726b852502 ("fw_setenv: lock the flash only if it was locked before") ? ____ From: Joakim Tjernlund Sent: 13 December 2021 18:22 To: u-boot@lists.denx.de; joe.hershber...@ni.com; fr0st6...@gmail.com Subject:

Re: [PATCH] fw_setenv: Unbreak fw_setenv caused by buggy MEMISLOCKED use

+Joe Hershberger Jocke On Wed, 2021-12-08 at 15:33 +0100, Joakim Tjernlund wrote: > Commit "fw_setenv: lock the flash only if it was locked before" > checks for Locked status with uninitialized erase data. > Address by moving the test for MEMISLOCKED. > > Fixes: 8a726

[PATCH] fw_setenv: Unbreak fw_setenv caused by buggy MEMISLOCKED use

Commit "fw_setenv: lock the flash only if it was locked before" checks for Locked status with uninitialized erase data. Address by moving the test for MEMISLOCKED. Fixes: 8a726b852502 ("fw_setenv: lock the flash only if it was locked before") Signed-off-by: Joakim Tjern

Re: debugging crash for arm64

Just had the same and you are probably missing to map that mem area to the MMU. grep for PTE_BLOCK_MEMTYPE in board and you will see how to. That said, I think the error msg in u-boot can be a bit better, some SEGV msg perhaps. Jocke From: U-Boot on

Re: [PATCH] mtd: cfi: Fix PPB lock status readout

On Thu, 2021-04-15 at 07:25 +0200, Stefan Roese wrote: > On 11.04.21 20:47, Marek Vasut wrote: > > According to S26KL512S datasheet [1] and S29GL01GS datasheet [2], > > the procedure to read out PPB lock bits is to send the PPB Entry, > > PPB Read, Reset/ASO Exit. Currently, the code does send

Re: [PATCH] mpc83xx: Fix dcache setup in lock_ram_in_cache

wrong with the CPUs cache and the CPU just RESET itself Jocke On Wed, 2020-11-11 at 13:54 +0100, Joakim Tjernlund wrote: > Lock dcache before clearing INIT_RAM. > More importantly, invalidate dcache contents before using it as RAM. > > Signed-off-by: Joakim Tjernlund > --- >

[PATCH] mpc83xx: Fix dcache setup in lock_ram_in_cache

Lock dcache before clearing INIT_RAM. More importantly, invalidate dcache contents before using it as RAM. Signed-off-by: Joakim Tjernlund --- Something odd happend, on a stable mpc8321 board, small unrelated code changes made the board unbootable. Debugging with an emulator it looked like

Re: U-Boot FIT Signature Verification

On Wed, 2020-09-16 at 13:55 +0200, Heinrich Schuchardt wrote: > On 16.09.20 13:40, Joakim Tjernlund wrote: > > On Wed, 2020-09-16 at 13:14 +0200, Heinrich Schuchardt wrote: > > > CAUTION: This email originated from outside of the organization. Do not > > > click links

Re: U-Boot FIT Signature Verification

On Wed, 2020-09-16 at 13:14 +0200, Heinrich Schuchardt wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On 16.09.20 10:13, AKASHI Takahiro wrote: > > On Wed,

Re: Changing U-boot relocation addres to SRAM (instead of DRAM)

On Mon, 2020-09-07 at 22:24 +0300, Yusuf Altıparmak wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > Hello, > > I want to modify U-boot to relocate itself to

eSPI was: [PATCH] Revert "mpc85xx: ddr: Always start DDR RAM in Self Refresh mode"

On Sun, 2020-04-12 at 04:22 +, Priyanka Jain wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > > -Original Message----- >

Re: [PATCH 00/24] spi: dm-conversion (part2)

On Wed, 2020-05-27 at 22:16 +0530, Jagan Teki wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > I believe some boards can directly enable DM_SPI if it has >

USB gadget ethernet status ?

I decided to check out USB gadget ethernet in u-boot and selected USB_ETHER/USB_ETH_RNDIS and tried to build it but that fails due to missing __constant_cpu_to_leXX() definitions. These are nowhere to find in u-boot so I wonder what shape above code is? Jocke

Re: [PATCH 2/2] env: add CONFIG_ENV_SECT_SIZE_AUTO

On Wed, 2020-05-06 at 13:06 +0200, Joakim Tjernlund wrote: > On Wed, 2020-05-06 at 12:47 +0200, Rasmus Villemoes wrote: > > On 06/05/2020 12.18, Joakim Tjernlund wrote: > > > On Wed, 2020-05-06 at 12:00 +0200, Joakim Tjernlund wrote: > > > > On Wed, 2020-05-06 at

Re: [PATCH 2/2] env: add CONFIG_ENV_SECT_SIZE_AUTO

On Wed, 2020-05-06 at 12:47 +0200, Rasmus Villemoes wrote: > On 06/05/2020 12.18, Joakim Tjernlund wrote: > > On Wed, 2020-05-06 at 12:00 +0200, Joakim Tjernlund wrote: > > > On Wed, 2020-05-06 at 11:37 +0200, Rasmus Villemoes wrote: > > > > CAUTION: This

Re: [PATCH 2/2] env: add CONFIG_ENV_SECT_SIZE_AUTO

On Wed, 2020-05-06 at 12:15 +0200, Rasmus Villemoes wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On 06/05/2020 12.00, Joakim Tjernlund

Re: [PATCH 2/2] env: add CONFIG_ENV_SECT_SIZE_AUTO

On Wed, 2020-05-06 at 12:00 +0200, Joakim Tjernlund wrote: > On Wed, 2020-05-06 at 11:37 +0200, Rasmus Villemoes wrote: > > CAUTION: This email originated from outside of the organization. Do not > > click links or open attachments unless you recognize the sender and know > >

Re: [PATCH 2/2] env: add CONFIG_ENV_SECT_SIZE_AUTO

On Wed, 2020-05-06 at 11:37 +0200, Rasmus Villemoes wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On 06/05/2020 11.21, Joakim Tjernlund w

Re: [PATCH 2/2] env: add CONFIG_ENV_SECT_SIZE_AUTO

On Wed, 2020-05-06 at 11:11 +0200, Rasmus Villemoes wrote: > > On 06/05/2020 10.59, Joakim Tjernlund wrote: > > On Wed, 2020-05-06 at 10:47 +0200, Rasmus Villemoes wrote: > > > At first, I wanted to allow setting CONFIG_ENV_SECT_SIZE to 0 to mean > > > "

Re: [PATCH 2/2] env: add CONFIG_ENV_SECT_SIZE_AUTO

On Wed, 2020-05-06 at 10:47 +0200, Rasmus Villemoes wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > This is roughly the U-Boot side equivalent to commit >

Re: [PATCH] Revert "mpc85xx: ddr: Always start DDR RAM in Self Refresh mode"

On Fri, 2020-04-10 at 11:40 +, Priyanka Jain wrote: > > > -Original Message- > > From: Joakim Tjernlund > > Sent: Thursday, April 9, 2020 6:24 PM > > To: Priyanka Jain ; Biwen Li (OSS) > > > > Cc: u-boot@lists.denx.de; Biwen Li ; Jiafei P

Re: [PATCH] Revert "mpc85xx: ddr: Always start DDR RAM in Self Refresh mode"

On Thu, 2020-04-09 at 20:44 +0800, Biwen Li wrote: This revert will bring back another bug, can you try finding out why it does work? May there are some minor tweaks needed ? Jocke > > From: Biwen Li > > This reverts commit 2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee. > After applied

Re: [PATCH] ddr: fsl: Impl. Erratum A008109

On Tue, 2019-12-17 at 08:55 +, Priyanka Jain wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > > -Original Message----- >

Re: [PATCH v2 1/2] common: fdt_support: add support for setting usable memory

On Tue, 2019-12-03 at 14:04 +0200, Igor Opaniuk wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > From: Igor Opaniuk > > Add support for setting

[U-Boot] [PATCH] mpc85xx: ddr: Always start DDR RAM in Self Refresh mode

unconditionally made all our boards stable again, regardless of Cold/Warm boot. Signed-off-by: Joakim Tjernlund --- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl

Re: [U-Boot] [PATCH] ddr: fsl: Impl. Erratum A008109

On Wed, 2019-11-20 at 17:07 +0100, Joakim Tjernlund wrote: > Impl. erratum as descibed in errata doc. > Enable A008109 for T1040 and T1024 > > Signed-off-by: Joakim Tjernlund > --- > arch/powerpc/cpu/mpc85xx/Kconfig | 2 ++ > drivers/ddr/fsl/Kconfig | 3 +

[U-Boot] [PATCH] ddr: fsl: Impl. Erratum A008109

Impl. erratum as descibed in errata doc. Enable A008109 for T1040 and T1024 Signed-off-by: Joakim Tjernlund --- arch/powerpc/cpu/mpc85xx/Kconfig | 2 ++ drivers/ddr/fsl/Kconfig | 3 +++ drivers/ddr/fsl/ctrl_regs.c | 6 ++ 3 files changed, 11 insertions(+) diff --git a/arch

Re: [U-Boot] [PATCH v5 2/5] dm: spi: Convert Freescale ESPI driver to driver model

On Wed, 2019-08-21 at 09:46 +, Xiaowei Bao wrote: > > -Original Message- > > From: Joakim Tjernlund > > Sent: 2019年8月21日 15:52 > > To: Prabhakar Kushwaha ; Ruchika Gupta > > ; Xiaowei Bao ; > > Shengzhou Liu ; w...@denx.de; > > ja...@amarula

Re: [U-Boot] [PATCH v5 2/5] dm: spi: Convert Freescale ESPI driver to driver model

On Wed, 2019-08-21 at 01:19 +, Xiaowei Bao wrote: > > > -Original Message- > > From: Joakim Tjernlund > > Sent: 2019年8月20日 19:04 > > To: Prabhakar Kushwaha ; Ruchika Gupta > > ; Xiaowei Bao ; > > Shengzhou Liu ; w...@denx.de; > &

Re: [U-Boot] [PATCH v5 2/5] dm: spi: Convert Freescale ESPI driver to driver model

On Tue, 2019-08-20 at 06:59 +, Xiaowei Bao wrote: > > From: Chuanhua Han > > Modify the Freescale ESPI driver to support the driver model. > Also resolved the following problems: > > = WARNING == > This board does not use CONFIG_DM_SPI. Please update

Re: [U-Boot] [PATCH v2 10/19] spi: mpc8xxx: Simplify logic a bit

On Wed, 2019-05-15 at 07:02 +0200, Mario Six wrote: > On Tue, May 14, 2019 at 3:53 PM Jagan Teki wrote: > > On Thu, May 2, 2019 at 2:37 PM Joakim Tjernlund > > wrote: > > > On Thu, 2019-05-02 at 07:31 +0200, Mario Six wrote: > > > > CAUTION: This email origina

Re: [U-Boot] [PATCH v2 10/19] spi: mpc8xxx: Simplify logic a bit

m vacation, so here's my answer: > > On Mon, Apr 29, 2019 at 12:41 PM Jagan Teki > wrote: > > + Mario > > > > On Mon, Apr 29, 2019 at 2:48 PM Joakim Tjernlund > > wrote: > > > On Mon, 2019-04-29 at 01:58 +0530, Jagan Teki wrote: > > > > From:

Re: [U-Boot] [PATCH v2 10/19] spi: mpc8xxx: Simplify logic a bit

On Mon, 2019-04-29 at 01:58 +0530, Jagan Teki wrote: > > From: Mario Six > > We do nothing in the loop if the "not empty" event was not detected. To > simplify the logic, check if this is the case, and skip the execution of > the loop early to reduce the nesting level and flag checking. Looked

[U-Boot] eMMC boot partition possible with an eMMC 4.2 controller ?

Trying to figure out if it will be possible to boot u-boot from an eMMC boot partition using an eMMC 4.2 controller(eMMC boot part. was introduced in 4.3) ? I know this might not be the best list to ask this but I have been unable to find this out using Google and I hope there is someone here

Re: [U-Boot] [PATCH 2/2] board: tbs2910: Remove FIT support in defconfig to reduce u-boot size

On Wed, 2019-01-09 at 17:39 -0500, Tom Rini wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On Wed, Jan 09, 2019 at 05:01:37PM +0100, Stefano Babic wrote: >

[U-Boot] [PATCH] mpc85xx: Add support for -msingle-pic-base

hex filename 288002 17868 24968 330838 50c56 u-boot.aft Signed-off-by: Joakim Tjernlund --- arch/powerpc/cpu/mpc85xx/config.mk | 1 + arch/powerpc/cpu/mpc85xx/start.S | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu

[U-Boot] [PATCH] mpc83xx: Add support for -msingle-pic-base

-msingle-pic-base is a new gcc(from 4.6) option for ppc and it reduces the size of my u-boot with about 4 KB. While at it, add -fno-jump-tables too to save a few more bytes. Signed-off-by: Joakim Tjernlund --- I think all PowerPC's can use this but I have only tested 83xx so just enable

Re: [U-Boot] [PATCH v2 1/9] powerpc, mpc8xx: clear top of stack

On Wed, 2018-11-21 at 08:51 +, Christophe Leroy wrote: > > Reported-by: Joakim Tjernlund > Signed-off-by: Christophe Leroy Reviewed-by: Joakim Tjernlund Leroy, if you need space, you may want to revive: https://github.com/u-boot/u-boot/commit/39768f7715ed637ef02f49fc7de664c

Re: [U-Boot] i2c: Fix pca953x endianess issue, commit daa75b34828d45b7c1d63009188d45f4a32d06ba

Okt. 2018 um 07:42 Uhr schrieb Heiko Schocher : > > > > Hello Joakim, > > > > Am 10.10.2018 um 19:34 schrieb Joakim Tjernlund: > > > This commit broke our pca953x usage(on ppc). > > > > > > I wonder why gpio pins here has an endia

[U-Boot] i2c: Fix pca953x endianess issue, commit daa75b34828d45b7c1d63009188d45f4a32d06ba

This commit broke our pca953x usage(on ppc). I wonder why gpio pins here has an endian, its not a number. If there must be an endian connected with this, should it not be a cpu_to_be16 instead, which will retain compatibility ? ___ U-Boot mailing list

Re: [U-Boot] [PATCH] fw_setenv: avoid writing environment when nothing has changed

On Mon, 2018-09-24 at 08:42 +0100, Alex Kiernan wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On Wed, Sep 5, 2018 at 8:23 PM Rasmus Villemoes > wrote: > >

Re: [U-Boot] Fwd: Parallel build is broken

On Tue, 2018-09-04 at 17:43 -0400, Tom Rini wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On Tue, Sep 04, 2018 at 09:05:55PM +0300, Andy Shevchenko wrote:

Re: [U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio

York, did this go anywhere? Jocke On Tue, 2018-02-27 at 19:54 +, York Sun wrote: > > On 02/27/2018 11:52 AM, Joakim Tjernlund wrote: > > On Tue, 2018-02-27 at 19:30 +, York Sun wrote: > > > > > > On 11/21/2017 10:20 AM, Joakim Tjernlund wrote: > > &

Re: [U-Boot] [PATCH] fs: btrfs: Fix wrong comparison in logical to physical mapping

On Wed, 2018-07-04 at 19:10 +0200, Marek Behún wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > The comparison > logical > item->logical + item->length > in

Re: [U-Boot] [PATCH] Makefile: Ensure we build with -std=gnu11

On Tue, 2018-06-19 at 23:57 -0400, Tom Rini wrote: > > > With the move to using at least gcc-6 for many targets we now have C > code that requires the GNU11 C standard to be used in all cases. Requiring gcc-6 is a bit much I think, there are lots of cross gcc's out there that is older. I don't

Re: [U-Boot] [PATCH RFCv2 0/6] Beginning of migration of MPC8xx to DM model

On Fri, 2018-05-04 at 12:33 +0200, Christophe LEROY wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > Hi Mario, > > Le 04/05/2018 à 11:56, Mario Six a écrit :

Re: [U-Boot] [PATCH v2 00/18] spi: mpc8xxx: DM conversion

On Thu, 2018-04-26 at 11:35 +0530, Jagan Teki wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On Thu, Apr 26, 2018 at 11:24 AM, Mario Six

Re: [U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio

On Tue, 2018-02-27 at 19:30 +, York Sun wrote: > > On 11/21/2017 10:20 AM, Joakim Tjernlund wrote: > > On Tue, 2017-11-21 at 18:04 +, York Sun wrote: > > > > > > > > > On 11/21/2017 09:52 AM, Joakim Tjernlund wrote: > > > >

Re: [U-Boot] [PATCH] drivers/ddr/fsl: Dual-license DDR driver

ntributed to that code for their explicit > > permission. Legally it is a huge difference between actively > > confirming approval and not reacting at all. > > > > All people (except Freescale and NXP employees) contributed to this code > are in

Re: [U-Boot] [PATCH v3 09/15] env: Support multiple environments

On Thu, 1970-01-01 at 00:00 +, Simon Goldschmidt wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On 06.02.2018 09:20, Joakim Tjernlund

Re: [U-Boot] [PATCH v3 09/15] env: Support multiple environments

On Thu, 1970-01-01 at 00:00 +, Maxime Ripard wrote: > Hi, > > On Tue, Feb 06, 2018 at 08:20:49AM +0000, Joakim Tjernlund wrote: > > On Thu, 1970-01-01 at 00:00 +, Simon Goldschmidt wrote: > > > > . > > > > Reviewed-by: Andre Przywara &l

Re: [U-Boot] [PATCH v3 09/15] env: Support multiple environments

On Thu, 1970-01-01 at 00:00 +, Simon Goldschmidt wrote: . > > Reviewed-by: Andre Przywara > > Reviewed-by: Simon Glass > > Signed-off-by: Maxime Ripard > > --- > > env/env.c | 80

Re: [U-Boot] U-Boot 2015 and u-boot-fw-utils 2017.09

On Thu, 1970-01-01 at 00:00 +, Wolfgang Denk wrote: > > Hello, > > In message <2018000422.7957c7f3@jawa> you wrote: > > > > > I am using U-Boot 2015.04, and the new root file system for my > > > platform includes u-boot-fw-utils 2017.09. I have noticed that > > > fw_{print,set}env

Re: [U-Boot] [PATCH v2 0/9] reduce the size of the mmc core

On Thu, 2018-01-04 at 15:23 +0100, Jean-Jacques Hiblot wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > This series applies on u-boot/next > > It aims at

Re: [U-Boot] U-Boot proper(not SPL) relocate option

On Wed, 2017-11-29 at 19:11 +0900, Masahiro Yamada wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > Hi Simon, > > > 2017-11-28 2:13 GMT+09:00 Simon Glass

Re: [U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio

On Tue, 2017-11-21 at 18:35 +, York Sun wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On 11/21/2017 10:20 AM, Joakim Tjernlund wrote

Re: [U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio

On Tue, 2017-11-21 at 18:04 +, York Sun wrote: > > > On 11/21/2017 09:52 AM, Joakim Tjernlund wrote: > > On Tue, 2017-11-21 at 17:45 +, York Sun wrote: > > > > > > On 11/21/2017 09:41 AM, Joakim Tjernlund wrote: > > > > On T

Re: [U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio

On Tue, 2017-11-21 at 17:45 +, York Sun wrote: > > On 11/21/2017 09:41 AM, Joakim Tjernlund wrote: > > On Tue, 2017-11-21 at 17:32 +, York Sun wrote: > > > CAUTION: This email originated from outside of the organization. Do not > > > click links or open at

Re: [U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio

On Tue, 2017-11-21 at 17:32 +, York Sun wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On 11/21/2017 09:29 AM, Joakim Tjernlund wrote

Re: [U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio

On Tue, 2017-11-21 at 17:23 +, York Sun wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > On 11/21/2017 09:18 AM, Joakim Tjernlund wrote

Re: [U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio

On Tue, 2017-09-12 at 19:56 +0200, Joakim Tjernlund wrote: > Most FSL PCIe controllers expects 333 MHz PCI reference clock. > This clock is derived from the CCB but in many cases the ref. > clock is not 333 MHz and a divisor needs to be configured. > > This adds PEX_CCB_DIV #d

Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state judgement more specific

> > > -Original Message----- > > From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com] > > Sent: Friday, October 20, 2017 9:13 PM > > To: w...@denx.de; Mingkai Hu <mingkai...@nxp.com>; > > tony.obr...@alliedtelesis.co.nz; u-boot@lists.d

Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state judgement more specific

On Fri, 2017-10-20 at 18:16 +0800, Bao Xiaowei wrote: > CAUTION: This email originated from outside of the organization. Do not click > links or open attachments unless you recognize the sender and know the > content is safe. > > > For some special reset times for longer pcie devices, the pcie

[U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio

Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured. This adds PEX_CCB_DIV #define which can be defined for each type of CPU/platform. Signed-off-by: Joakim

Re: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?

On Thu, 2017-09-07 at 06:45 +, Mingkai Hu wrote: > > -Original Message- > > From: Mingkai Hu > > Sent: Wednesday, September 06, 2017 5:37 PM > > To: 'Joakim Tjernlund' <joakim.tjernl...@infinera.com>; Roy Zang > > <roy.z...@nxp.com>;

Re: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?

On Wed, 2017-09-06 at 09:36 +, Mingkai Hu wrote: > > -Original Message- > > From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com] > > Sent: Tuesday, September 05, 2017 8:45 PM > > To: Mingkai Hu <mingkai...@nxp.com>; Roy Zang <roy.z...@nxp.com

Re: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?

On Wed, 2017-08-30 at 15:25 +, York Sun wrote: > On 08/30/2017 06:05 AM, Joakim Tjernlund wrote: > > On Tue, 2017-08-29 at 17:33 +, York Sun wrote: > > > +Roy Zang to comment on PCIe clock source > > > > > > On 08/29/2017 10:06 AM, Joakim Tjernlund wro

Re: [U-Boot] FSL PCIe LTSSM >= PCI_LTSSM_L0 equals link up

On Mon, 2017-08-28 at 17:14 +, York Sun wrote: > +Xiaowei > > On 08/28/2017 10:09 AM, Joakim Tjernlund wrote: > > On Mon, 2017-08-28 at 16:55 +, York Sun wrote: > > > On 08/28/2017 09:48 AM, Joakim Tjernlund wrote: > > > > FSL PCIe controller drivers be

Re: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?

On Wed, 2017-08-30 at 15:25 +, York Sun wrote: > On 08/30/2017 06:05 AM, Joakim Tjernlund wrote: > > On Tue, 2017-08-29 at 17:33 +, York Sun wrote: > > > +Roy Zang to comment on PCIe clock source > > > > > > On 08/29/2017 10:06 AM, Joakim Tjernlund wro

Re: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?

On Tue, 2017-08-29 at 17:33 +, York Sun wrote: > +Roy Zang to comment on PCIe clock source > > On 08/29/2017 10:06 AM, Joakim Tjernlund wrote: > > On Tue, 2017-08-29 at 15:43 +, York Sun wrote: > > > On 08/29/2017 06:21 AM, Joakim Tjernlund wrote: > > > &g

Re: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?

On Tue, 2017-08-29 at 15:43 +, York Sun wrote: > On 08/29/2017 06:21 AM, Joakim Tjernlund wrote: > > On Tue, 2017-08-29 at 12:47 +0200, Joakim Tjernlund wrote: > > > As we are looking at PCI stuff ATM I would like to ask > > > about PEX_GCLK_RATIO in E500 CPUs.

Re: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?

On Tue, 2017-08-29 at 12:47 +0200, Joakim Tjernlund wrote: > As we are looking at PCI stuff ATM I would like to ask > about PEX_GCLK_RATIO in E500 CPUs. I cannot find this is setup > at all for E500 but I THINK this is required. > > In 83xx one do: > get_clocks(); >

Re: [U-Boot] FSL PCIe LTSSM >= PCI_LTSSM_L0 equals link up

in uboot or kernel, this solution is used for layerscape platform. > I am not asking about the layerscape platform, I want to know what to do with FSL. Please read the whole thread. > Thanks > > -Original Message- > From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera

[U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?

As we are looking at PCI stuff ATM I would like to ask about PEX_GCLK_RATIO in E500 CPUs. I cannot find this is setup at all for E500 but I THINK this is required. In 83xx one do: get_clocks(); /* Configure the PCIE controller core clock ratio */ out_le32(hose_cfg_base + PEX_GCLK_RATIO, (((bus ?

Re: [U-Boot] FSL PCIe LTSSM >= PCI_LTSSM_L0 equals link up

FSL u-boot/linux users. > Thanks > > > -Original Message- > From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com] > Sent: Tuesday, August 29, 2017 2:45 PM > To: Xiaowei Bao <xiaowei@nxp.com>; York Sun <york@nxp.com> > Cc: u-boot@lists.

Re: [U-Boot] FSL PCIe LTSSM >= PCI_LTSSM_L0 equals link up

- > From: York Sun > Sent: Tuesday, August 29, 2017 1:15 AM > To: Xiaowei Bao <xiaowei@nxp.com> > Cc: Joakim Tjernlund <joakim.tjernl...@infinera.com>; u-boot@lists.denx.de > Subject: Re: FSL PCIe LTSSM >= PCI_LTSSM_L0 equals link up > > +Xiaowei > >

Re: [U-Boot] FSL PCIe LTSSM >= PCI_LTSSM_L0 equals link up

On Mon, 2017-08-28 at 16:55 +, York Sun wrote: > On 08/28/2017 09:48 AM, Joakim Tjernlund wrote: > > FSL PCIe controller drivers before REV 3 has this test for link up: > >enabled = ltssm >= PCI_LTSSM_L0; > > > > We have a PCIe dev. that stays in LTSSM=0x51

[U-Boot] FSL PCIe LTSSM >= PCI_LTSSM_L0 equals link up

FSL PCIe controller drivers before REV 3 has this test for link up: enabled = ltssm >= PCI_LTSSM_L0; We have a PCIe dev. that stays in LTSSM=0x51 (Polling Compliance) when non ready for PCI transaktions. When FSL PCIe controller tries to access this device, it hangs forever. Is LTSSM=0x51

Re: [U-Boot] Orphan Freescale PowerPC boards

On Wed, 2017-05-17 at 13:25 -0400, Tom Rini wrote: > On Wed, May 17, 2017 at 04:57:57PM +, york sun wrote: > > On 05/09/2017 08:52 AM, York Sun wrote: > > > On 05/09/2017 08:49 AM, Tom Rini wrote: > > > > On Tue, May 09, 2017 at 08:46:46AM -0700, York Sun wrote: > > > > > On 05/09/2017 05:36

Re: [U-Boot] [PATCH] sunxi: Explicitly call fdt_fixup_ethernet() in our ft_board_setup()

On Fri, 2017-04-28 at 11:05 +0200, Maxime Ripard wrote: > On Fri, Apr 28, 2017 at 03:33:53PM +0800, Chen-Yu Tsai wrote: > > The sunxi platform relies on the core boot sequence to load and process > > device tree blobs, including writing back any MAC addresses we generate > > by an implicit call to

Re: [U-Boot] Remove global variable env_t *env_ptr ?

On Tue, 2017-04-04 at 13:27 +0200, Wolfgang Denk wrote: > Dear Joakim, > > In message <1491302640.30240.1.ca...@infinera.com> you wrote: > > > > > That is my exact question - when would this happen? Flash sectors > > > do now wander around in memory or change size :-) > > > > No, but they

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