On 12/31/2015 5:07 PM, Marek Vasut wrote:
> On Thursday, December 31, 2015 at 08:24:45 AM, Peng Fan wrote:
>> From: "Ye.Li"
>>
>> All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI
>> interface. Set to ULPI is not correct, even the controller will
>> reject
On 11/5/2015 1:10 PM, Marek Vasut wrote:
> On Thursday, November 05, 2015 at 04:17:38 AM, Ye.Li wrote:
>> All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI
>> interface. Set to ULPI is not correct, even the controller will reject
>> this
>> setting in PORTSC register.
>>
>>
Hi,
On 2/10/2015 6:51 PM, Stefano Babic wrote:
Hi,
On 12/01/2015 09:46, Ye.Li wrote:
Initial version for mx6sx SABREAUTO board support with features:
PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.
Signed-off-by: Ye.Li b37...@freescale.com
---
arch/arm/Kconfig
Hi Stefano,
On 2/10/2015 6:22 PM, Stefano Babic wrote:
Hi,
On 12/01/2015 09:46, Ye.Li wrote:
The mx6sx has two ENET controllers, some board like mx6sxsabreauto
uses the ENET2 for ethernet. So add ENET2 support to soc level,
including: ENET2 clock enable and MAC address fuse for ENET2.
Hi Stefano,
On 2/10/2015 6:26 PM, Stefano Babic wrote:
Hi Ye,
On 12/01/2015 09:46, Ye.Li wrote:
On mx6sx, the CCM register bits for GPMI are different as other
mx6 platforms. Modify the GPMI clock function to support mx6sx.
Signed-off-by: Ye.Li b37...@freescale.com
---
Hi Stefano, Nikolay,
On 1/30/2015 1:54 AM, Stefano Babic wrote:
Hi,
On 12/01/2015 11:37, Nikolay Dimitrov wrote:
Hi Ye.Li,
On 01/12/2015 10:46 AM, Ye.Li wrote:
The I2C SDA and SCL require the IOMUX SION bit set to get input signal.
Signed-off-by: Ye.Li b37...@freescale.com
---
Hi Fabio,
On 11/4/2014 11:46 PM, Fabio Estevam wrote:
Hi Ye Li,
On Tue, Nov 4, 2014 at 6:27 AM, Ye.Li b37...@freescale.com wrote:
Plugin image is a firmware which can be executed by boot ROM to do
device initialization, custom settings, delay assertion, etc.
Could you please elaborate a bit
Hi Przemyslaw,
On 11/4/2014 10:09 PM, Przemyslaw Marczak wrote:
Hello Ye Li,
On 11/04/2014 10:37 AM, Li Ye-B37916 wrote:
Hi Przemyslaw,
On 11/4/2014 5:24 PM, Li Ye-B37916 wrote:
Hi Przemyslaw,
On 10/30/2014 6:36 PM, Stefano Babic wrote:
Hi Ye,
On 10/09/2014 11:08, Ye.Li wrote
Hi Przemyslaw,
On 11/4/2014 11:56 PM, Przemyslaw Marczak wrote:
Hello Ye Li,
On 09/10/2014 11:08 AM, Ye.Li wrote:
Initialize the Pfuze on I2C1 at board late init. The mx6slevk board
has Pfuze100 or Pfuze200, print the chip type by parsing the ID.
Signed-off-by: Ye.Li b37...@freescale.com
Hi Przemyslaw,
On 11/4/2014 11:57 PM, Przemyslaw Marczak wrote:
Hello Ye Li,
On 09/10/2014 11:08 AM, Ye.Li wrote:
Set all switches APS mode in normal and PFM mode in standby. So when
mx6 entering DSM mode, the power number can be decreased. There is
no impact for mx6 in run mode.
Changes
Hi Przemyslaw,
On 10/30/2014 6:36 PM, Stefano Babic wrote:
Hi Ye,
On 10/09/2014 11:08, Ye.Li wrote:
Initialize the Pfuze on I2C1 at board late init. The mx6slevk board
has Pfuze100 or Pfuze200, print the chip type by parsing the ID.
Signed-off-by: Ye.Li b37...@freescale.com
---
Slowly
Hi Przemyslaw,
On 11/4/2014 5:24 PM, Li Ye-B37916 wrote:
Hi Przemyslaw,
On 10/30/2014 6:36 PM, Stefano Babic wrote:
Hi Ye,
On 10/09/2014 11:08, Ye.Li wrote:
Initialize the Pfuze on I2C1 at board late init. The mx6slevk board
has Pfuze100 or Pfuze200, print the chip type by parsing
Hi Stefano,
On 9/9/2014 2:50 PM, Ye.Li wrote:
To support more iMX6 variants,
1. Make the DDR size configurable based on the defconfig file
2. Make the FDT file configurable based on the defconfig file
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- Rework the short log
Hi Peng,
On 11/1/2014 10:19 AM, Peng Fan wrote:
Add a new function mxc_iomux_set_gpr_register to
set the iomux gpr register.
32-bit general purpose registers according to SoC
requirements for any usage.
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li
Hi Peng,
On 11/1/2014 10:19 AM, Peng Fan wrote:
Add usb support for mx6sxsabresd board.
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
---
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 29
+
Hi Stefano,
On 10/27/2014 7:18 PM, Stefano Babic wrote:
Hi Ye,
On 27/10/2014 05:10, Li Ye-B37916 wrote:
The patch is used to add a choice for GPT clock source to provide high
frequency clock. The configuration CONFIG_MXC_GPT_HCLK is not dependent
on the chip version. Even it is i.MX28
Hi Stefano,
On 10/24/2014 9:18 PM, Stefano Babic wrote:
Hi Ye,
On 24/10/2014 14:32, Ye.Li wrote:
Introduce a new configuration CONFIG_MXC_GPT_HCLK. When it is set,
the GPT will use 24Mhz OSC as clock source. Otherwise, the GPT will
use 32Khz OSC as clock source.
Since only the GPT on iMX6
Hi Stefano,
On 10/22/2014 3:22 PM, Stefano Babic wrote:
Hi Ye,
On 22/10/2014 08:39, Ye.Li wrote:
The bootdata.size should contain the IVT offset part, but the calculation
in imximage tool does not have. This will cause some data at
the end of image not be loaded into memory.
Hi Stefano,
On 10/22/2014 4:14 PM, Stefano Babic wrote:
Hi Ye,
On 22/10/2014 09:38, Li Ye-B37916 wrote:
You can look into the Figure 8-21. Image Vector Table in the system boot
chapter of i.MX6Q manual. The bootdata.start points
to the beginning of the destination memory, which means
On 10/10/2014 7:46 PM, Fabio Estevam wrote:
On Fri, Oct 10, 2014 at 6:01 AM, Ye.Li b37...@freescale.com wrote:
On mx6 sabreauto board, there are two USB ports:
0: OTG
1: HOST
The EHCI driver is enabled for this board, but the IOMUX and VBUS power
control is not implemented, which cause both
On 9/12/2014 4:17 PM, Stefano Babic wrote:
Hi Ye,
On 10/09/2014 07:52, Ye.Li wrote:
Initialize the Pfuze100 at board late init.
Signed-off-by: Ye.Li b37...@freescale.com
---
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 52
-
include/configs/mx6qsabreauto.h
Hi Stefano,
On 9/12/2014 6:08 PM, Stefano Babic wrote:
Hi Ye,
On 11/09/2014 05:13, Ye.Li wrote:
Add I2C1 pin and pad settings, and enable the MXC I2C driver.
I see two different topics in this patch:
1. Add I2C1 pins to mx6sl pins. This is general, and not related to a
specific board.
Hi Stefano,
On 9/12/2014 6:13 PM, Stefano Babic wrote:
Hi Ye,
On 11/09/2014 05:13, Ye.Li wrote:
Add clear print log to show pfuze200 or pfuze100 found on mx6sabresd.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
Changes since v2:
- None
On 9/11/2014 10:28 AM, Fabio Estevam wrote:
On Wed, Sep 10, 2014 at 11:25 PM, Ye.Li b37...@freescale.com wrote:
Set all switches APS mode in normal and PFM mode in standby. So when
mx6 entering DSM mode, the power number can be decreased. There is
no impact for mx6 in run mode.
Changes for
On 9/9/2014 7:41 AM, Otavio Salvador wrote:
On Wed, Sep 3, 2014 at 4:23 AM, Li Ye-B37916 b37...@freescale.com wrote:
On 9/2/2014 10:06 PM, Fabio Estevam wrote:
On Tue, Sep 2, 2014 at 3:11 AM, Ye.Li b37...@freescale.com wrote:
#ifdef CONFIG_SUPPORT_EMMC_BOOT
#define EMMC_ENV
Hi Fabio,
On 9/9/2014 11:56 AM, Fabio Estevam wrote:
Hi Ye,
On Tue, Sep 9, 2014 at 12:35 AM, Li Ye-B37916 b37...@freescale.com wrote:
This is a real mx6solo processor on this board.
Your question reminders me this bootarg is indeed for simulation. In fsl
release, we provide a feature
On 9/5/2014 2:43 AM, Otavio Salvador wrote:
Hello Ye,
On Thu, Sep 4, 2014 at 11:17 AM, Ye.Li b37...@freescale.com wrote:
This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.
The
On 9/2/2014 10:06 PM, Fabio Estevam wrote:
On Tue, Sep 2, 2014 at 3:11 AM, Ye.Li b37...@freescale.com wrote:
#ifdef CONFIG_SUPPORT_EMMC_BOOT
#define EMMC_ENV \
emmcdev=2\0 \
@@ -146,7 +155,8 @@
fi; \
fi\0 \
EMMC_ENV \
On 9/2/2014 8:13 PM, Fabio Estevam wrote:
Hi Ye Li,
On Tue, Sep 2, 2014 at 3:11 AM, Ye.Li b37...@freescale.com wrote:
Add specified mx6dl_4x_mt41j128.cfg DDR script for iMX6DLSABRESD board. Not
share from nitrogen6x. The default boot device also changes to SD card.
Signed-off-by: Ye.Li
On 9/2/2014 10:08 PM, Fabio Estevam wrote:
On Tue, Sep 2, 2014 at 3:11 AM, Ye.Li b37...@freescale.com wrote:
Rename the imximage.cfg to mx6q.cfg.
No function change at all
Signed-off-by: Ye.Li b37...@freescale.com
---
board/freescale/mx6qsabreauto/imximage.cfg | 129
Hi Stefano Babic,
On 8/20/2014 5:44 PM, Stefano Babic wrote:
Hi Ye,
On 20/08/2014 10:55, Ye.Li wrote:
From: Ye.Li ye...@freescale.com
The load region size of EIM-NOR are defined to 0. For this case,
the parameter imximage_init_loadsize must be calculated.
The imximage tool implements the
On 8/21/2014 3:57 PM, Stefano Babic wrote:
Hi,
On 21/08/2014 07:02, Marek Vasut wrote:
On Thursday, August 21, 2014 at 06:11:16 AM, Ye Li wrote:
The TDAR bit is set when the descriptors are all out from TX ring, but the
descriptor properly is in transmitting not READY.
I don't quite
Hi Marek,
On 8/22/2014 1:18 AM, Marek Vasut wrote:
On Thursday, August 21, 2014 at 07:10:32 PM, Fabio Estevam wrote:
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is set in the last BD, which causes
FEC transmission to
Hi Fabio,
I feel the name ARCH_DMA_MINALIGN_MX6SX is not good here. Because the 64
bytes alignment is only required by the DMA engine in FEC controller, not a
ARCH DMA value.
Best regards,
Ye Li
On 8/21/2014 5:24 AM, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
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