[U-Boot] [PATCH] Initialise correct GPMC WAITx irq for AM33xx

Currently WAIT0 irq is reset and then WAIT1 irq is enabled. Fix it such that WAIT0 irq is enabled instead. Signed-off-by: Mark Jackson m...@newflow.co.uk --- arch/arm/cpu/armv7/am33xx/mem.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/am33xx/mem.c

Re: [U-Boot] [PATCH] Initialise correct GPMC WAITx irq for AM33xx

Mark == Mark Jackson mpfj-l...@mimc.co.uk writes: Mark Currently WAIT0 irq is reset and then WAIT1 irq is enabled. Mark Fix it such that WAIT0 irq is enabled instead. Mark Signed-off-by: Mark Jackson m...@newflow.co.uk Mark --- Mark arch/arm/cpu/armv7/am33xx/mem.c |2 +- Mark 1 file