On Feb 7, 2011, at 3:14 PM, haiying.w...@freescale.com
haiying.w...@freescale.com wrote:
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth
On Tue, 2011-02-08 at 10:52 -0600, Kumar Gala wrote:
+#endif
uec = (uec_private_t *)dev-priv;
if (uec-the_first_run == 0) {
+#ifdef CONFIG_P1021
+ /* reset micrel phy for each UEC */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+
On Tue, 2011-02-08 at 12:09 -0500, Haiying Wang wrote:
On Tue, 2011-02-08 at 10:52 -0600, Kumar Gala wrote:
+#endif
uec = (uec_private_t *)dev-priv;
if (uec-the_first_run == 0) {
+#ifdef CONFIG_P1021
+ /* reset micrel phy for each UEC */
+ clrbits_8((u8
On Feb 8, 2011, at 11:11 AM, Haiying Wang wrote:
On Tue, 2011-02-08 at 12:09 -0500, Haiying Wang wrote:
On Tue, 2011-02-08 at 10:52 -0600, Kumar Gala wrote:
+#endif
uec = (uec_private_t *)dev-priv;
if (uec-the_first_run == 0) {
+#ifdef CONFIG_P1021
+ /* reset micrel phy for
From: Haiying Wang haiying.w...@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because
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