Please forget the last phrase...
On Mon, Oct 26, 2009 at 5:01 PM, Werner Nedel wmne...@gmail.com wrote:
Sorry for this big mistake and wasting your time :-(
There's a bit between rtt and ocd, that don't match with definition in
jedec ddr2 sdram specification.
On Sat, Oct 24, 2009 at 12:38
Sorry for this big mistake and wasting your time :-(
There's a bit between rtt and ocd, that don't match with definition in jedec
ddr2 sdram specification.
On Sat, Oct 24, 2009 at 12:38 PM, Kumar Gala ga...@kernel.crashing.orgwrote:
5 is correct.
Here's an example:
rtt = 0x3:
esd_mode
5 is correct.
Here's an example:
rtt = 0x3:
esd_mode should be = 0x44:
esdmode = (0
| ((rtt 0x4) 7) /* rtt field is split */
| ((rtt 0x2) 5) /* rtt field is split */
| ((rtt 0x1) 2) /* rtt field is split */
Hi,
I was looking the ctrl_regs.c file at the last release of u-boot,
specifically at sdram_mode register, and checking at AN3369.pdf I think that
Rtt bit position might be wrong. At the code, the bit shifting is 5, but
shouldn't be 6? I think that it overwrites AL register.
Thanks in advance,
On Oct 22, 2009, at 6:48 AM, Werner Nedel wrote:
Hi,
I was looking the ctrl_regs.c file at the last release of u-boot,
specifically at sdram_mode register, and checking at AN3369.pdf I
think that
Rtt bit position might be wrong. At the code, the bit shifting is 5,
but
shouldn't be 6?
Hi,
sorry about that. I'm working on a MPC8548 platform and using the mpc8xxx
common code for DDR configuration.
On Thu, Oct 22, 2009 at 11:36 AM, Kumar Gala ga...@kernel.crashing.orgwrote:
On Oct 22, 2009, at 6:48 AM, Werner Nedel wrote:
Hi,
I was looking the ctrl_regs.c file at the
Sorry again,
and with DDR2.
On Thu, Oct 22, 2009 at 11:42 AM, Werner Nedel wmne...@gmail.com wrote:
Hi,
sorry about that. I'm working on a MPC8548 platform and using the mpc8xxx
common code for DDR configuration.
On Thu, Oct 22, 2009 at 11:36 AM, Kumar Gala
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