On Wednesday 19 October 2011 01:46 PM, Sebastian Andrzej Siewior wrote:
* Sebastian Andrzej Siewior | 2011-09-20 16:02:01 [+0200]:
This patch adds support for the Android boot-image format. The header
file is from the Android project and got slightly alterted so the struct +
its defines are
Fix boot issue on ES2.0 Panda by tuning some
IO settings. The CONTROL_EFUSE_2 register has
to be over-ridden in software for 4430 boards.
Commit 23e9f0723e48615332119de4f4ec7a833a282628
wrongly did this for CONTROL_EFUSE_1. Reverting
this and doing it for CONTROL_EFUSE_2.
Signed-off-by: Aneesh V
Hi Raul,
On Monday 26 December 2011 11:38 PM, Raúl Porcel wrote:
Hi,
Following with the issue on
http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/111922
Looks like the 23e9f0723e48615332119de4f4ec7a833a282628 commit was
supposed to fix this, but it doesn't, the problem is still
Hi Stefano,
On Wednesday 04 January 2012 09:25 AM, Stefano Babic wrote:
Signed-off-by: Stefano Babicsba...@denx.de
CC: Tom Rinitom.r...@gmail.com
CC: Wolfgang Denkw...@denx.de
CC: Simon Schwarzsimonschwarz...@gmail.com
---
Changes since V11:
- enable cache files in Makefile after checking
On Friday 13 January 2012 11:08 PM, Sughosh Ganu wrote:
hi Heiko,
On Fri Jan 13, 2012 at 04:29:29PM +0100, Heiko Schocher wrote:
Hello Sugosh,
Sughosh Ganu wrote:
hi Christian,
On Fri Jan 13, 2012 at 09:06:26AM +0100, Christian Riesch wrote:
Hi Sughosh,
I had a look at the patch and I
Dear Wolfgang,
On Wednesday 23 November 2011 03:33 PM, Sebastian Andrzej Siewior wrote:
* Wolfgang Denk | 2011-11-22 20:04:47 [+0100]:
Dear Sebastian Andrzej Siewior,
In message2022123007.ga5...@linutronix.de you wrote:
+ * Redistribution and use in source and binary forms, with or
Hi Joe,
On Monday 09 January 2012 09:18 PM, Joe Woodward wrote:
snip
(apologies for previous top posting, wasn't paying attention to what I was
doing!)
I'm fairly certain...
If I take the 2011.12 uBoot release the kernel takes about twice the time to
boot (compared to 2011.09), and the
On Tuesday 17 January 2012 08:21 PM, Måns Rullgård wrote:
Aneesh Vane...@ti.com writes:
Hi Joe,
On Monday 09 January 2012 09:18 PM, Joe Woodward wrote:
If I take the 2011.12 uBoot release the kernel takes about twice the
time to boot (compared to 2011.09), and the device is noticably
Hi Sughosh,
On Thursday 19 January 2012 12:23 PM, Sughosh Ganu wrote:
On Tue Jan 17, 2012 at 08:27:58AM -0700, Tom Rini wrote:
On Mon, Jan 16, 2012 at 11:46 PM, Sughosh Ganuurwithsugh...@gmail.com wrote:
Hmm.. how did u-boot work on such boards? How can u-boot work with D-Cache
enabled, if
On Thursday 19 January 2012 05:00 PM, Christian Riesch wrote:
Hi Aneesh,
On Thu, Jan 19, 2012 at 11:17 AM, Aneesh Vane...@ti.com wrote:
On Thursday 19 January 2012 12:23 PM, Sughosh Ganu wrote:
Tried a few things on my end.
* Read the D-cache value in the spl, and confirmed that the
Sughosh,
On Friday 20 January 2012 12:58 PM, Christian Riesch wrote:
On Thu, Jan 19, 2012 at 12:54 PM, Aneesh Vane...@ti.com wrote:
On Thursday 19 January 2012 05:00 PM, Christian Riesch wrote:
On Thu, Jan 19, 2012 at 11:17 AM, Aneesh Vane...@ti.comwrote:
On Thursday 19 January 2012
On Friday 20 January 2012 02:51 PM, Christian Riesch wrote:
Hi Aneesh,
On Fri, Jan 20, 2012 at 9:52 AM, Aneesh Vane...@ti.com wrote:
Sughosh,
[...]
Can you send the value of SCR you found at SPL entry? This will clarify
what's enabled and what's not.
I would like to try that on my board
Hi Christian,
On Friday 20 January 2012 06:18 PM, Christian Riesch wrote:
Hi Aneesh,
On Fri, Jan 20, 2012 at 1:13 PM, Aneesh Vane...@ti.com wrote:
On Friday 20 January 2012 02:51 PM, Christian Riesch wrote:
On Fri, Jan 20, 2012 at 9:52 AM, Aneesh Vane...@ti.comwrote:
Sughosh,
[...]
Dear Wolfgang,
On Tuesday 17 January 2012 02:46 PM, Aneesh V wrote:
Dear Wolfgang,
On Wednesday 23 November 2011 03:33 PM, Sebastian Andrzej Siewior wrote:
* Wolfgang Denk | 2011-11-22 20:04:47 [+0100]:
Dear Sebastian Andrzej Siewior,
In message2022123007.ga5...@linutronix.de you wrote
Tom,
On Thursday 02 February 2012 10:02 PM, Tom Rini wrote:
On Thu, Feb 2, 2012 at 6:04 AM, Balaji T Kbalaj...@ti.com wrote:
spl for OMAP4 does not use mmc read/write.
Add CONFIG_MMC_NO_ERASE, CONFIG_MMC_NO_WRITE to platforms where mmc
write/erase operation is not needed in spl.
Use these
Hi Dirk,
On Friday 03 February 2012 12:55 PM, Dirk Behme wrote:
Hi,
on i.MX6 devices, e.g. ARM2 or SabreLite, the ROM boot loader copies the
U-Boot image from the boot device, e.g. the SD card, to the main memory.
This does mean that U-Boot is started in RAM.
With this, one might wonder why
On Saturday 04 February 2012 04:30 PM, Albert ARIBAUD wrote:
Le 04/02/2012 10:15, Aneesh V a écrit :
Hi Dirk,
On Friday 03 February 2012 12:55 PM, Dirk Behme wrote:
Hi,
on i.MX6 devices, e.g. ARM2 or SabreLite, the ROM boot loader copies the
U-Boot image from the boot device, e.g. the SD
Hi Dirk,
On Saturday 04 February 2012 02:08 PM, Dirk Behme wrote:
Let's discuss how to enable the i.MX5/6 caches in U-Boot:
On 03.02.2012 12:00, Stefano Babic wrote:
On 03/02/2012 11:18, Dirk Behme wrote:
...
As your concerns are surely related to speed up the boot process, IMHO
we can
To enable support for new platforms you just need to add
CONFIG_SYS_THUMB_BUILD in your config file.
Aneesh V (4):
ARM: enable Thumb build
OMAP3+: fix issues with Thumb build
OMAP3+: Use -march=armv7-a and thereby enable Thumb-2
OMAP4: enable Thumb build
README
Enable Thumb build and ARM-Thumb interworking based on the new
config flag CONFIG_SYS_THUMB_BUILD
Signed-off-by: Aneesh V ane...@ti.com
---
README |9 +
arch/arm/config.mk | 29 +
2 files changed, 26 insertions(+), 12 deletions(-)
diff --git
and the real implementation in C.
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/cpu.c |4 ++-
arch/arm/cpu/armv7/omap-common/hwinit-common.c | 25
arch/arm/cpu/armv7/omap-common/lowlevel_init.S |4 +-
3 files changed, 30
Enable -march=armv7-a for OMAP3+ platforms. This in turn
results in Thumb-2 code generated for these platforms if
CONFIG_SYS_THUMB_BUILD is enabled.
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap-common/config.mk |1 -
arch/arm/cpu/armv7/omap3/config.mk |2
Signed-off-by: Aneesh V ane...@ti.com
---
include/configs/omap4_common.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index a989721..01b4d6c 100644
--- a/include/configs/omap4_common.h
+++ b/include
On Monday 06 February 2012 05:07 PM, Aneesh V wrote:
Thumb is an alternate instruction set available in many
ARM processors. Below is a detailed description from ARM
specs:
The Thumb instruction set is a re-encoded subset of the
ARM instruction set. Thumb instructions execute in their
own
On Monday 06 February 2012 05:56 PM, Aneesh V wrote:
On Monday 06 February 2012 05:07 PM, Aneesh V wrote:
Thumb is an alternate instruction set available in many
ARM processors. Below is a detailed description from ARM
specs:
The Thumb instruction set is a re-encoded subset of the
ARM
On Sunday 05 February 2012 11:49 AM, Simon Glass wrote:
Hi,
On Sat, Feb 4, 2012 at 1:15 AM, Aneesh Vane...@ti.com wrote:
Hi Dirk,
On Friday 03 February 2012 12:55 PM, Dirk Behme wrote:
Hi,
on i.MX6 devices, e.g. ARM2 or SabreLite, the ROM boot loader copies the
U-Boot image from the boot
We do not have thermal management or Smartreflex
enabled at U-Boot level. So, it's better to stick
to OPP100 for MPU instead of the OPP Turbo that is
used now. Adjust the VDD_MPU accordingly.
Tested-by: Sebastien Jan s-...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap4
On Tuesday 07 February 2012 04:11 AM, Graeme Russ wrote:
Hi Wolfgang,
On Tue, Feb 7, 2012 at 9:27 AM, Wolfgang Denkw...@denx.de wrote:
Dear Albert ARIBAUD,
In message4f304463.1050...@aribaud.net you wrote:
In my experience, the offset is consistent on a given platform so once
you do the
On Monday 06 February 2012 08:19 PM, Tom Rini wrote:
On Mon, Feb 6, 2012 at 1:43 AM, Graeme Russgraeme.r...@gmail.com wrote:
Hi Wolfgang,
On 02/06/2012 06:51 PM, Wolfgang Denk wrote:
Dear Graeme Russ,
In messageCALButC+==qgs5eaahtqqu4zejqvg-3187ewaqu-fv3dwp5q...@mail.gmail.com
you wrote:
On Tuesday 07 February 2012 12:15 AM, Tom Rini wrote:
On Mon, Feb 6, 2012 at 4:37 AM, Aneesh Vane...@ti.com wrote:
Enable Thumb build and ARM-Thumb interworking based on the new
config flag CONFIG_SYS_THUMB_BUILD
Signed-off-by: Aneesh Vane...@ti.com
[snip]
-# Explicitly specifiy 32-bit ARM
On Tuesday 07 February 2012 02:36 AM, Albert ARIBAUD wrote:
Le 06/02/2012 12:37, Aneesh V a écrit :
When U-Boot/SPL is built using the Thumb instruction set the
toolchain has a potential issue with weakly linked symbols.
If a function has a weakly linked default implementation in C
and a real
Dear Wolfgang,
On Wednesday 08 February 2012 04:56 AM, Wolfgang Denk wrote:
Dear Aneesh V,
In message4f30d06e.8060...@ti.com you wrote:
I agree. Even on some platforms that are not fully static (such as having
variants with different memory sizes) the minimum available memory is
more than
Dear Wolfgang,
On Wednesday 08 February 2012 07:28 PM, Wolfgang Denk wrote:
Dear Aneesh V,
In message4f3219a8.7090...@ti.com you wrote:
As for ignoring comments, I think you are culpable of that more than me
in this specific instance:) (of course I know you are busy person, but
still
On Wednesday 08 February 2012 09:53 PM, Wolfgang Denk wrote:
Dear Aneesh V,
In message4f328b41.2050...@ti.com you wrote:
But since then I changed my mind due to some other factors:
1. Difficulty in debugging. I use JTAG debuggers. The workarounds
available are still painful and not many
Hi Albert,
On Tuesday 07 February 2012 02:36 AM, Albert ARIBAUD wrote:
Le 06/02/2012 12:37, Aneesh V a écrit :
When U-Boot/SPL is built using the Thumb instruction set the
toolchain has a potential issue with weakly linked symbols.
If a function has a weakly linked default implementation in C
On Thursday 09 February 2012 05:14 PM, Wolfgang Denk wrote:
Dear Aneesh V,
In message4f33614d.8020...@ti.com you wrote:
What exactly are you talking about here that was adding a
considerable delay - the memory copy ? Are you really sure about
that?
I didn't measure it part by part
because of the reduced image sizes.
Aneesh V (4):
ARM: enable Thumb build
arm: add %function attribute to assembly functions
armv7: Use -march=armv7-a and thereby enable Thumb-2
OMAP4: enable Thumb build
README |9 +
arch/arm/config.mk
Enable Thumb build and ARM-Thumb interworking based on the new
config flag CONFIG_SYS_THUMB_BUILD
Signed-off-by: Aneesh V ane...@ti.com
---
Changes from RFC to V1:
- Fixed review comments from Tom Rini tr...@ti.com
---
README |9 +
arch/arm/config.mk | 20
Enable -march=armv7-a for armv7 platforms if the tool-chain
supports it. This in turn results in Thumb-2 code generated
for these platforms if CONFIG_SYS_THUMB_BUILD is enabled.
Signed-off-by: Aneesh V ane...@ti.com
---
I believe armv7-a is fine for all the SoCs except Tegra2
and I see
implementation in assembly GCC is confused about the
instruction set of the assembly implementation. As a result
the assembly function that is built in ARM is executed as
if it is Thumb. This results in a crash
Signed-off-by: Aneesh V ane...@ti.com
---
Changes from RFC to V1:
- This change completely replaces
Signed-off-by: Aneesh V ane...@ti.com
---
Changes from RFC to V1:
- None
---
include/configs/omap4_common.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index a989721..01b4d6c 100644
--- a/include/configs
the strongly-linked implementation
of v7_outer_cache_disable() and allowing it to fall
back to the weakly linked implementation that doesn't
do anything.
Signed-off-by: Aneesh V ane...@ti.com
---
I haven't tested this patch as I don't have an OMAP3
board with me right now. Appreciate if anybody
+Tom
Hi Lucas,
On 06/22/2012 04:47 AM, Lucas Stach wrote:
Hi Albert,
Am Freitag, den 22.06.2012, 13:16 +0200 schrieb Albert ARIBAUD:
Hi Lucas,
Linux in particular does reinitialize this state and I expect any
reasonable OS to do so.
Then what is the point of enabling it on U-Boot? Does
On 06/22/2012 03:11 PM, Aneesh V wrote:
+Tom
Hi Lucas,
On 06/22/2012 04:47 AM, Lucas Stach wrote:
Hi Albert,
Am Freitag, den 22.06.2012, 13:16 +0200 schrieb Albert ARIBAUD:
Hi Lucas,
Linux in particular does reinitialize this state and I expect any
reasonable OS to do so.
Then what
Hi Albert,
On 06/25/2012 01:34 PM, Albert ARIBAUD wrote:
Hi Aneesh,
BTW, I agree that enabling un-aligned access is not a bad idea.
Just being not a bad idea is not enough for me to accept this. It
will have to be the sole sound solution to a problem, and at this
point, I do not think it is
Hi Sricharan,
On 06/21/2012 02:25 AM, Sricharan R wrote:
Hi,
[snip..]
On 06/15/2012 07:48 AM, R, Sricharan wrote:
Hi,
On Fri, Jun 15, 2012 at 12:31 AM, Tom Rinitr...@ti.com wrote:
If we are built with D-CACHE enabled but have run 'dcache off' and
then
attempt to flush unaligned regions
Sricharan,
On 06/21/2012 08:23 AM, R, Sricharan wrote:
Hi Aneesh,
On Thu, Jun 21, 2012 at 2:55 PM, Sricharan Rr.sricha...@ti.com wrote:
Hi,
[snip..]
On 06/15/2012 07:48 AM, R, Sricharan wrote:
Hi,
On Fri, Jun 15, 2012 at 12:31 AM, Tom Rinitr...@ti.comwrote:
If we are built with
Hi Marek,
On 07/06/2012 04:32 PM, Tetsuyuki Kobayashi wrote:
Hello,
On 2012/07/07, at 8:02, Marek Vasut wrote:
Dear Aneesh V,
Enable -march=armv7-a for armv7 platforms if the tool-chain
supports it. This in turn results in Thumb-2 code generated
for these platforms
Hi Marek,
On 06/25/2012 04:30 PM, Marek Vasut wrote:
Dear Scott Wood,
On 06/24/2012 07:17 PM, Marek Vasut wrote:
This macro returns 1 if the argument (address) is aligned, returns
zero otherwise. This will be used to test user-supplied address to
various commands to prevent user from loading
On 06/24/2012 05:17 PM, Marek Vasut wrote:
This prevents the scenario where data cache is on and the
device uses DMA to deploy data. In that case, it might not
be possible to flush/invalidate data to RAM properly. The
other option is to use bounce buffer, but that involves a
lot of copying and
Hi Tyler,
On 07/26/2012 11:54 AM, Tyler Olmstead wrote:
Hi Christian,
On Thu, Jul 26, 2012 at 10:03 AM, Christian Riesch
christian.rie...@omicron.at wrote:
[cc'd Prabhakar Lad, Tom Rini, and Scott Wood]
Tyler,
On Thu, Jul 26, 2012 at 5:37 PM, Tyler Olmstead
tyler.j.olmst...@gmail.com
make default implementation of cache_flush() weakly linked so that
sub-architectures can override it
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/lib/cache.c |9 +++--
1 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index
before the invalidate
- If match succeeds it means that flush was successful
- Outer caches were tested with experiments involving making the
function pointers NULL
* Kernel booting on OMAP4430SDP and OMAP3430SDP
Aneesh V (8):
arm: make default implementation
adapt s5pc1xx to the new layered cache maintenance framework
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/s5pc1xx/cache.S| 86 +---
arch/arm/cpu/armv7/s5pc1xx/clock.c| 12
arch/arm/include/asm/arch-s5pc1xx/sys_proto.h |4
:
- Invalidate entire I-cache
- Add maintenance functions for TLB, branch predictor array etc.
- Enable -march=armv7-a so that armv7 assembly instructions can be
used
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/Makefile |2 +-
arch/arm/cpu/armv7/cache_v7.c | 359
issues.
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/lib/cache-cp15.c |9 +++--
arch/arm/lib/cache.c | 13 -
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index ca526fb..20aa993 100644
--- a/arch
adapt omap3 to the new layered cache maintenance framework
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap3/Makefile |1 -
arch/arm/cpu/armv7/omap3/board.c| 151 ++--
arch/arm/cpu/armv7/omap3/cache.S| 263
Add support for some of the key maintenance operations
- Invalidate all
- Invalidate range
- Flush(clean invalidate) all
- Flush range
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/include/asm/pl310.h | 49 ++
arch/arm/lib/Makefile
- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
- Do necessary initialization before enabling d-cache and MMU
- Changes to cleanup_before_linux()
- Make changes according to the new framework
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu
adapt omap4 to the new layered cache maintenance framework
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap4/board.c| 25 -
arch/arm/cpu/armv7/omap4/lowlevel_init.S| 17 +
arch/arm/include/asm/arch-omap4/omap4.h
Dear Minkyu Kang,
On Monday 27 December 2010 12:55 PM, Minkyu Kang wrote:
snip
+
+#ifndef CONFIG_SYS_NO_DCACHE
+void v7_setup_outer_cache_ops(void)
+{
+#ifndef CONFIG_L2_OFF
+ v7_outer_cache.enable = ca8_l2_cache_enable;
+ v7_outer_cache.disable = ca8_l2_cache_disable;
Hello John,
On Tuesday 28 December 2010 06:17 AM, John Rigby wrote:
This patch series adds the ability to boot a beagle board from
nand without x-loader. A future addition will add mmc boot
support.
I had been working on something similar for OMAP4. Basically, I have an
SPL ready for MMC on
Hello John,
On Tuesday 28 December 2010 06:17 AM, John Rigby wrote:
snip
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext
$(CONFIG_SYS_NAND_SPL_TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_PRELOADER
On Wednesday 29 December 2010 05:56 AM, John Rigby wrote:
On Mon, Dec 27, 2010 at 11:50 PM, Aneesh Vane...@ti.com wrote:
Hello John,
On Tuesday 28 December 2010 06:17 AM, John Rigby wrote:
snip
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS = -Bstatic -T
Hi John,
On Tuesday 28 December 2010 06:17 AM, John Rigby wrote:
Signed-off-by: John Rigbyjohn.ri...@linaro.org
+
+void board_init_f(unsigned long bootflag)
+{
+ nand_boot();
+}
+
I see that you have added a call to nand_boot() in start.S too.
Which is the intended one?
If we jump to
Hi Albert,
On Saturday 08 January 2011 12:24 PM, Albert ARIBAUD wrote:
Hi Aneesh,
Le 22/12/2010 12:54, Aneesh V a écrit :
- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
- Do necessary initialization before enabling d-cache and MMU
- Changes
John,
On Saturday 08 January 2011 12:16 PM, John Rigby wrote:
On Fri, Jan 7, 2011 at 11:33 PM, Aneesh Vane...@ti.com wrote:
Hi John,
On Tuesday 28 December 2010 06:17 AM, John Rigby wrote:
Signed-off-by: John Rigbyjohn.ri...@linaro.org
+
+void board_init_f(unsigned long bootflag)
+{
+
Hi Albert,
On Saturday 08 January 2011 12:34 PM, Albert ARIBAUD wrote:
Hi Aneesh,
Le 22/12/2010 12:54, Aneesh V a écrit :
1. make sure that page table setup is not done multiple times
2. flush_dcache_all() is more appropriate while disabling cache
than a range flush on the entire
Hi Albert,
On Saturday 08 January 2011 12:06 PM, Albert ARIBAUD wrote:
Hi Aneesh,
Le 22/12/2010 12:54, Aneesh V a écrit :
- Add a framework for layered cache maintenance
- separate out SOC specific outer cache maintenance from
maintenance of caches known to CPU
- Add generic
On Saturday 08 January 2011 12:06 PM, Albert ARIBAUD wrote:
Hi Aneesh,
Pressed the Send button too fast last time. Missed answering the last
few questions.
snip..
+
+void invalidate_dcache_all(void)
+{
+v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
+if (v7_outer_cache.inval_all)
+
Dear Wolfgang,
On Monday 10 January 2011 04:11 AM, Wolfgang Denk wrote:
Dear Albert ARIBAUD,
In message4d286f58.9010...@free.fr you wrote:
I know we consider multi-board u-boot binaries when boards are variant
of a given SoC, that's one reason why we wanted relocation. I'm not sure
about
Dear Wolfgang,
On Monday 10 January 2011 04:18 AM, Wolfgang Denk wrote:
Dear Aneesh V,
In message1293018898-13253-6-git-send-email-ane...@ti.com you wrote:
Add support for some of the key maintenance operations
- Invalidate all
- Invalidate range
- Flush(clean invalidate
Dear Wolfgang,
On Monday 10 January 2011 04:22 AM, Wolfgang Denk wrote:
Dear Aneesh V,
In message1293018898-13253-7-git-send-email-ane...@ti.com you wrote:
adapt omap4 to the new layered cache maintenance framework
Signed-off-by: Aneesh Vane...@ti.com
+/*
+ * Outer cache related
Dear Wolfgang,
On Monday 10 January 2011 04:27 AM, Wolfgang Denk wrote:
Dear Aneesh V,
In message1293018898-13253-8-git-send-email-ane...@ti.com you wrote:
adapt omap3 to the new layered cache maintenance framework
...
+/* Declarations */
Please drop this comment. Everybody sees what
On Saturday 08 January 2011 07:36 PM, Albert ARIBAUD wrote:
Le 08/01/2011 14:17, Aneesh V a écrit :
snip..
+/* some utility macros */
+#define mask(start, end) \
+ (((1 ((end) - (start) + 1)) - 1) (start))
+
+#define mask_n_get(reg, start, end) \
+ (((reg) mask(start, end)) (start
On Thursday 13 January 2011 12:48 AM, Albert ARIBAUD wrote:
(I realize I did not answer the other ones)
Le 08/01/2011 11:06, Aneesh V a écrit :
Out of curiosity, can you elaborate on why the compiler would optimize
better in these cases?
While counting down the termination condition check
On Thursday 13 January 2011 12:53 AM, Albert ARIBAUD wrote:
Le 12/01/2011 10:08, Aneesh V a écrit :
On Saturday 08 January 2011 07:36 PM, Albert ARIBAUD wrote:
Le 08/01/2011 14:17, Aneesh V a écrit :
snip..
+/* some utility macros */
+#define mask(start, end) \
+ (((1 ((end) - (start) + 1
On Thursday 13 January 2011 12:48 AM, Albert ARIBAUD wrote:
snip ..
+ for (way = num_ways - 1; way= 0 ; way--)
+ for (set = num_sets - 1; set= 0; set--) {
Please fix whitespacing around operators. The best way to ''catch'em
all'' is to run Linux' checkpatch.pl (I do this with option
On Thursday 13 January 2011 06:44 PM, Albert ARIBAUD wrote:
Le 13/01/2011 13:05, Aneesh V a écrit :
What I need is something like below:
#define get_bit_field(nr, start, mask)\
(((nr) (mask)) (start))
#define set_bit_field(nr, start, mask, val)\
(nr) = ((nr) ~(mask)) | (((val) (start
with cortexa9. Both A8 and A9 are
based on armv7 architecture.
The second patch adds minimal support for OMAP4430 SDP. With this patch
OMAP4430 SDP boots up. Other features such as MMC, ethernet etc will be
added in subsequent patches.
Aneesh V (2):
arm: renaming the cpu arm_cortexa8 to armv7
arm
Renaming the cpu arm_cortexa8 to armv7 so that we can share code between
cortexa8
and cortexa9.
Both A8 and A9 belong to the armv7 architecture.
The differences between cortexa8 and cortexa9 do not impact u-boot
initialization.
We can have common code for both the CPUs.
Signed-off-by: Aneesh V
and to copy u-boot directly into SDRAM from a non-XIP device.
More support such as MMC, ethernet etc will be added in subsequent patches.
Signed-off-by: Aneesh V ane...@ti.com
---
Makefile|8 +-
arch/arm/cpu/armv7/omap4/Makefile | 50 +
arch
On 05/08/2012 10:16 PM, R Sricharan wrote:
Signed-off-by: R Sricharanr.sricha...@ti.com
CC: Aneesh Vane...@ti.com
CC: Tom Rinitr...@ti.com
---
MAINTAINERS | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
Acked-by: Aneesh V ane...@ti.com
Hi Jagan,
On 06/19/2012 08:36 AM, jagan wrote:
Hi Albert,
I have observed an issue regarding u-boot relocation, it's working with
_TEXT_BASE address but
for other address in DDR it's not working. Stops at relocation offset.
This is not quite clear to me. What's working and what's not
Hi Sricharan,
On 06/15/2012 07:48 AM, R, Sricharan wrote:
Hi,
On Fri, Jun 15, 2012 at 12:31 AM, Tom Rinitr...@ti.com wrote:
If we are built with D-CACHE enabled but have run 'dcache off' and then
attempt to flush unaligned regions we spam the console with problems
that aren't true (as the
Dear Wolfgang,
On Thursday 10 November 2011 09:36 PM, Aneesh V wrote:
Hi Wolfgang,
On Saturday 05 November 2011 01:13 PM, Aneesh V wrote:
Wolfgang's patch for build time improvement is bringing
out issues due to missing dependencies in the top-level
Makefile. I get errors such as the below
Aneesh V (4):
armv7: disable L2 cache in cleanup_before_linux()
armv7: include armv7/cpu.c in SPL build
armv7: setup vector
start.S: remove omap3 specific code from start.S
arch/arm/cpu/armv7/Makefile |4 +-
arch/arm/cpu/armv7/cpu.c |1 +
arch/arm/cpu
.
Cc: Albert Aribaud albert.u.b...@aribaud.net
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/cpu.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 091e3e0..662c496 100644
--- a/arch/arm/cpu/armv7/cpu.c
This allows SPL to have default implementation of
save_boot_params(), useful for SoCs that do
not intend to override this default implementation
Cc: Albert Aribaud albert.u.b...@aribaud.net
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/Makefile |4 ++--
1 files changed, 2
The vector is not correctly setup in armv7 except for OMAP3.
Correcting this.
Cc: Albert Aribaud albert.u.b...@aribaud.net
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/start.S | 17 +
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap3/lowlevel_init.S |8
arch/arm/cpu/armv7/start.S | 23 ---
arch/arm/include/asm/arch-omap3/omap3.h |1 +
3
Aneesh V (9):
omap: Improve PLL parameter calculation tool
omap4: ttyO2 instead of ttyS2 in default bootargs
omap: fix cache line size for omap3/omap4 boards
omap4460: fix TPS initialization
omap: remove I2C from SPL
omap4: emif: fix error in driver
omap4460: add ES1.1 identification
Improve the tool that finds multiplier and divider for PLLs:
The previous algorithm could get stuck on local maxima
and required the user to specify the tolerance. Improve
the algorithm to go through the entire search space and find
the optimal solution.
Signed-off-by: Aneesh V ane...@ti.com
Set console=ttyO2 instead of ttyS2 in default bootargs
according to latest kernel config
Signed-off-by: Aneesh V ane...@ti.com
---
include/configs/omap4_common.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/omap4_common.h b/include/configs
Cc: Tom Rini tr...@ti.com
Signed-off-by: Aneesh V ane...@ti.com
---
include/configs/omap3_beagle.h |2 ++
include/configs/omap3_evm.h|1 +
include/configs/omap3_evm_common.h |2 ++
include/configs/omap3_mvblx.h |2 ++
include/configs/omap3_overo.h |2
-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c |8
board/ti/panda/panda_mux_data.h|2 +-
board/ti/sdp4430/sdp.c |7 +++
board/ti/sdp4430/sdp4430_mux_data.h|6 +-
4 files changed, 13
Due to some recent changes I2C is no longer required in SPL.
Remove the i2c_init() call to save some space
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap-common/spl.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c
There was a typo in the EMIF driver. It went un-noticed
because it affected only when automatic detection is enabled
and even then half the memory was configured and identified
properly.
Reported-by: Rockefeller rockefeller@innocomm.com
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap4/hwinit.c | 10 +-
arch/arm/include/asm/arch-omap4/omap.h |2 ++
arch/arm/include/asm/omap_common.h |1 +
3 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c
as internal U-Boot doesn't have relocation and 0x8010
used by mainline U-Boot will clash with kernel
3. Assume only a minimum amount of memory that may be available
on any practical OMAP4/5 board in future too. We are assuming
a minimum of 128 MB of memory
Signed-off-by: Aneesh V ane...@ti.com
1 - 100 of 610 matches
Mail list logo
