Hi Steve,
On 08/28/2016 06:22 AM, Steve Rae wrote:
Hi Kever,
On Aug 23, 2016 20:48, "Kever Yang" <kever.y...@rock-chips.com
<mailto:kever.y...@rock-chips.com>> wrote:
>
> To support fastboot, we need to enable the controller first.
> rk3399 is usin
Hi Marek,
On 08/26/2016 05:11 PM, Marek Vasut wrote:
On 08/25/2016 03:07 AM, Kever Yang wrote:
+ Marek
On 08/24/2016 11:46 AM, Kever Yang wrote:
This patch add board_usb_init() and interrupt callback
for dwc3 gadget.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by:
The popmetal board using a HOST_VBUS_DRV gpio signal to control the
USB host port 5V power, add a fix regulator and pinctrl for it, and
enable the USB host1 controller at the same time.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3288-popmetal.dts
RK3288 using the dwc2 USB host controller, enable it and other usb host
funtion like storage and ether.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
configs/popmetal-rk3288_defconfig | 3 +++
include/configs/rk3288_common.h | 7 +++
2 files changed, 10 insertions(+)
Enable the usb host port 5V power by enable the fix regulator.
The PopMetal board have a on board FE1.1 usb 2.0 hub which connect to
the usb host port, we need to de-assert its reset pin at the same time.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
board/chipspark/popmetal_
2016 at 18:56, Kever Yang <kever.y...@rock-chips.com> wrote:
Hi Doug,
Do you mean usb gadget driver or usb host driver?
I mean USB host.
The usb controller for rk3288 is very similar to rk3036, I though the driver
are working on upstream.
Let me double check.
OK, thanks. I don
ee
USB device tree:
1 Hub (480 Mb/s, 0mA)
| U-Boot Root Hub
|
+-2 Hub (480 Mb/s, 100mA)
| USB 2.0 Hub
|
+-3 Mass Storage (480 Mb/s, 300mA)
Kingston DataTraveler G2 001D92AD7612B91113680066
Kever Yang (3):
dts: popmetal: add usb host power supply node
PWM_ROCKCHIP need to enable for PWM regulator, this config
is missing during rebase and new patch set in previous submission.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
configs/evb-rk3399_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/evb-rk3399_defco
Hi Chi,
On 11/10/2016 12:51 AM, Ding, ChiX wrote:
Hi there
I'm having problem getting USB 3.0 controller working properly on the Intel
Denverton x86 board.
First I tried to use xhci driver, but there doesn't seem to be any xhci driver
or generic driver for x86
I only found the following
The size dram node need to be deduced by the same amount of reserved space.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
board/rockchip/evb_rk3399/evb-rk3399.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c
b
enable the vbus for usb host in board_init().
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/mach-rockchip/rk3036-board.c | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3036-board.c
b/arch/arm/mach-rockchip/rk3036-b
rk3036 using dwc2 usb controller, need enable relate configs for it.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
configs/kylin-rk3036_defconfig | 3 +++
include/configs/rk3036_common.h | 7 +++
2 files changed, 10 insertions(+)
diff --git a/configs/kylin-rk3036_defco
add fix regulator node for usb vbus power control.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3036-sdk.dts | 37 +
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/
To enable usb host function, you need:
- enable the host port power, usually controled by a gpio named
vbus_drv;
- enable the controller driver like dwc2;
- enable the usb framework like CONFIG_CMD_USB and CONFIG_USB;
- enable the usb function like storage or ether;
Kever Yang (4):
config
usb host vbus power is using gpio fix regulator, enable it.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
configs/kylin-rk3036_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 5a8b85a..631d1f5
Hi Simon,
On 11/12/2016 12:17 AM, Simon Glass wrote:
Hi Kever,
On 8 November 2016 at 03:13, Kever Yang <kever.y...@rock-chips.com> wrote:
enable the vbus for usb host in board_init().
Note 'borad_init' typo in subject.
Will fix in next version.
Signed-off-by: Kever Yang <kever.
Hi Simon,
On 11/12/2016 12:17 AM, Simon Glass wrote:
Hi Kever,
On 9 November 2016 at 00:30, Kever Yang <kever.y...@rock-chips.com> wrote:
Enable the usb host port 5V power by enable the fix regulator.
The PopMetal board have a on board FE1.1 usb 2.0 hub which connect to
the usb host po
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
drivers/usb/host/dwc2.
The PopMetal board have a on board FE1.1 usb 2.0 hub which connect to
the usb host port, we need to de-assert its reset pin to enable it.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- move the vbus power enable into dwc2 driver
board/chipspark/popmetal_
RK3288 using the dwc2 USB host controller, enable it and other usb host
funtion like storage and ether.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
configs/popmetal-rk3288_defconfig | 3 +++
inc
ee
USB device tree:
1 Hub (480 Mb/s, 0mA)
| U-Boot Root Hub
|
+-2 Hub (480 Mb/s, 100mA)
| USB 2.0 Hub
|
+-3 Mass Storage (480 Mb/s, 300mA)
Kingston DataTraveler G2 001D92AD7612B91113680066
Changes in v2:
- move the vbus power enable into dwc2 driver
Kever Y
The popmetal board using a HOST_VBUS_DRV gpio signal to control the
USB host port 5V power, add a fix regulator and pinctrl for it, and
enable the USB host1 controller with the vbus-supply.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
arch/arm/dts/
Hi Andreas,
On 11/03/2016 09:32 AM, Andreas Färber wrote:
Hello,
Am 25.07.2016 um 05:45 schrieb Kever Yang:
RK3399 needs reserve 0x20 at the beginning of DRAM, for ATF bl31.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- correct some typo on commit m
Hi Doug,
Do you mean usb gadget driver or usb host driver?
The usb controller for rk3288 is very similar to rk3036, I though the
driver are working on upstream.
Let me double check.
Thanks,
- Kever
On 11/02/2016 09:04 AM, Simon Glass wrote:
Hi Kever,
Do you have a USB driver for RK3288
turn -EINVAL;
+ rk3288_clk_configure_cpu(priv->cru, priv->grf);
+ new_rate = rate;
+ break;
case CLK_DDR:
new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
break;
Reviewed-by: Kever Yang <kever.y...@rock-
Hi Jaehoon,
On 10/10/2016 07:01 AM, Jaehoon Chung wrote:
On 10/07/2016 06:23 PM, Kever Yang wrote:
Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
api.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/mmc/rockchip_sdhci.c | 4
1 file c
Hi Simon,
On 11/26/2016 03:39 AM, Simon Glass wrote:
Hi Kever,
On 24 November 2016 at 00:29, Kever Yang <kever.y...@rock-chips.com> wrote:
The PopMetal board have a on board FE1.1 usb 2.0 hub which connect to
the usb host port, we need to de-assert its reset pin to enable it.
Sign
Hi Marek,
On 11/26/2016 12:46 AM, Marek Vasut wrote:
On 11/24/2016 08:29 AM, Kever Yang wrote:
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: Kever Yang <keve
Hi Simon,
On 12/12/2016 04:27 AM, Simon Glass wrote:
Hi Nickey,
On 8 December 2016 at 21:39, Nickey Yang wrote:
isp-camera image will be broken when enter dual screen display mode.
We set isp qos high to solve this problem.
Signed-off-by: Nickey Yang
Hi Stefan,
Thanks for your review comment.
On 12/29/2016 02:35 AM, Stefan Herbrechtsmeier wrote:
Hi,
Am 28.12.2016 um 12:01 schrieb Jaehoon Chung:
On 12/28/2016 12:32 PM, Kever Yang wrote:
Init the clock rate to max-frequency from dts with clock driver api.
Signed-off-by: Kever Yang
for all
other images. Then the SPL handle PC to BL31 with the parameter, the
BL31 will do the rest of work and at last get into U-Boot(BL33).
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
common/spl/Kconfig | 14 +++
common/spl/Makefile | 1 +
common/spl/spl.c | 4 +
RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
coreboot, support 4GB lpddr3 in this version.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 188 +++
arch/arm/mach-rockchip/rk3399/Makefile
Add spl support for rk3399.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/Kconfig| 1 +
arch/arm/dts/rk3399.dtsi| 24
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 118 ++
arch/ar
of comment is welcome for the implementation of spl_atf.c
and the entry in spl.c
Kever Yang (3):
arm64: rk3399: add SPL support
arm64: rk3399: add ddr controller driver
spl: add support to booting with ATF
arch/arm/Kconfig |1 +
arch/arm/dts/rk3399.dtsi
Hi Jaehoon,
On 12/30/2016 02:30 PM, Jaehoon Chung wrote:
It's cleaned the condes related to SDHCI host controller.
Move the callback function into sdhci_ops structure.
And removed the unnecessary things.
My next step should be more clearly than now.
- Support DM feature than now.
- Make
Hi Romain,
Thanks for your report and debug.
On 01/06/2017 06:52 PM, Romain Perier wrote:
Add Rockchip Engineers to Cc:
Le 06/01/2017 à 11:28, Romain Perier a écrit :
Hello,
I have a strange behaviour with the SPL on rk3288.
When I build u-boot-rockchip master for the rock2
Hi Michal,
Thanks for your comments.
On 01/02/2017 11:05 PM, Michal Simek wrote:
On 29.12.2016 11:25, Kever Yang wrote:
ATF(ARM Trust Firmware) is used by ARM arch64 SoCs, find more infomation
about ATF at:
SPL is consider as BL2 in ATF, it needs to load other part of ATF binary
SPL
Thanks,
Michal
On 29.12.2016 11:25, Kever Yang wrote:
RK3399 SPL is not enable bacause of the lack of ATF support in SPL,
after port some source code from ATF, I manage to enable the support for
ATF in SPL. This patch set depends on some patch for SPL support multi
binary in FIT which is from Andre
Hi Jaehoon,
On 12/28/2016 09:34 AM, Jaehoon Chung wrote:
Hi Kever,
On 12/28/2016 10:12 AM, Kever Yang wrote:
Hi Jaehoon,
On 12/28/2016 06:08 AM, Jaehoon Chung wrote:
Hi Kever,
On 12/27/2016 10:09 PM, Kever Yang wrote:
Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
Hi Jaehoon,
On 12/28/2016 06:08 AM, Jaehoon Chung wrote:
Hi Kever,
On 12/27/2016 10:09 PM, Kever Yang wrote:
Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
api.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- using the return
Add 'max-frequency' for sdhci node for clock init.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v3: None
arch/arm/dts/rk3399.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 179860c..22277ff
Init the clock rate to max-frequency from dts with clock driver api.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v3:
- using dt for max-frequency
Series-changes: 2
- using the return value
drivers/mmc/rockchip_sdhci.c | 19 +--
1 file chang
rk3399 has two clock-controller: cru and pmucru, update the
rockchip_get_crui() API, and rockchip_get_clk() do not used for
other module.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 6 +++---
1 file changed, 3 insertions(+), 3 del
.
f798b1dda1c5de818b806189e523d1b75db7e72d
Reported-by: Kever Yang <kever.y...@rock-chips.com>
Reported-by: frostyby...@protonmail.com
Signed-off-by: Stefan Brüns <stefan.bru...@rwth-aachen.de>
---
fs/ext4/ext4_common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/e
Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
api.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- using the return value
drivers/mmc/rockchip_sdhci.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drive
Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
api.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- using the return value
drivers/mmc/rockchip_sdhci.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drive
Hi Stefan, Tom,
I'm using genext2fs command in Linux to generate my boot image for
kernel and its dtb, my command is like this:
$ genext2fs -b 32768 -B $((32*1024*1024/32768)) -d boot/ -i 8192 -U
boot.img
In the latest version of U-Boot, the image from above command is
not able
Hi Rick,
On 01/16/2017 10:50 AM, Simon Glass wrote:
+Kever
Hi Rick,
On 15 January 2017 at 12:05, Rick Bronson wrote:
Hi All,
I updated one of my two RK3288 boards (Viewsonic) with newer Android
factory firmware (using Windows) and now it won't boot mainline u-boot
when I
Hi Simon,
I met two issue when using of-platdata
1. compitable name with '.'
I get compile error as below:
In file included from include/dt-structs.h:16:0,
from spl/dts/dt-platdata.c:3:
include/generated/dt-structs.h:26:35: error: expected identifier or ‘(’
before numeric
struct udevice *dev;
+ int ret;
+
#define EARLY_UART
#ifdef EARLY_UART
/*
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
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define CONFIG_SYS_MAXARGS16
-#define CONFIG_BAUDRATE150
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
Looks good to me.
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Hi Jernej,
On 03/24/2017 08:11 AM, Jernej Skrabec wrote:
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.
Signed-off-by: Jernej Skrabec
---
GPT partition layout to mmc device which fastboot want to use it to
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
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UPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+#define COUNTER_FREQUENCY 2400
+
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x0020
Reveiwed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
__
.
Hi Dan, are you able to provide some information for the header structure,
for example, is it suppose to change/update in the future?
Thanks,
- Kever
Cheers,
Andre.
On 23/03/17 03:00, Kever Yang wrote:
ATF(ARM Trusted Firmware) is used by ARM arch64 SoCs, find more infomation
about ATF
I believe the cache API has some problem on armv7, at least
invalidate_dcache_range()
does not work as expected.
I get one issue on rk3288 dwc2 host driver:
- connect U-Disk and run 'usb start';
- write gpt table to it with 'gpt write usb 0 $partitions'
- check the partition table with
Kever Yang (1):
spl: add support to booting with ATF
common/spl/Kconfig | 14 +++
common/spl/Makefile | 1 +
common/spl/spl.c | 3 +
common/spl/spl_atf.c | 96 ++
include/atf_common.h | 276 +++
include/spl.h| 1
Hi Simon,
On 03/22/2017 09:05 PM, Simon Glass wrote:
Hi Kever,
On 20 March 2017 at 00:41, Kever Yang <kever.y...@rock-chips.com> wrote:
ATF(ARM Trust Firmware) is used by ARM arch64 SoCs, find more infomation
about ATF at:
SPL is consider as BL2 in ATF, it needs to load other part
the parameter for BL31 which including entry and image information
for all other images. Then the SPL handle PC to BL31 with the parameter,
the BL31 will do the rest of work and at last get into U-Boot(BL33).
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- Kconfig c
update with Simon's suggestion
- including file ordering,
- update function comment format,
- use 'if' instead of '#ifdef' for bl31_entry
- add ATF Kconfig option depend on ARM64
Series-changes: 1
- license update
- split out as separate patch
Kever Yang (1):
spl: add support to booting with ATF
the parameter for BL31 which including entry and image information
for all other images. Then the SPL handle PC to BL31 with the parameter,
the BL31 will do the rest of work and at last get into U-Boot(BL33).
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- Kconfig c
hilipp.
On 29 Mar 2017, at 04:31, Kever Yang <kever.y...@rock-chips.com> wrote:
Hi Philipp,
So you got hang in SPL if the DWMMC is no in fifo mode, do you have
any clue for what's the root cause?
+ Ziyuan,
Hi Ziyuan,
Could you double check this issue? Does it also happen at rk3288 dw
Error %d\n", ret);
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
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K=2400
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_ROCKCHIP_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/README.rockchip b/doc/README.rockchip
index a408522346..cdeab2d961 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -36,12 +36,13 @@ You will need:
Building
-At present seven RK3288 boards are supported:
+At present eight RK3288 boards are supported:
- EVB RK3288 - use evb-rk3288 configuration
- Fennec RK3288 - use fennec-rk3288 configuration
- Firefly RK3288 - use firefly-rk3288 configuration
- Hisense Chromebook - use chromebook_jerry configuration
+ - MiQi RK3288 - use miqi-rk3288 configuration
- PopMetal RK3288 - use popmetal-rk3288 configuration
- Radxa Rock 2 - use rock2 configuration
- Tinker RK3288 - use tinker-rk3288 configuration
diff --git a/include/configs/miqi_rk3288.h b/include/configs/miqi_rk3288.h
new file mode 100644
index 00..f686042499
--- /dev/null
+++ b/include/configs/miqi_rk3288.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,cros-ec-keyb\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+
+#endif
Looks good to me,
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
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Firefly RK3288 - use firefly-rk3288 configuration
- Hisense Chromebook - use chromebook_jerry configuration
- - Tinker RK3288 - use tinker-rk3288 configuration
- PopMetal RK3288 - use popmetal-rk3288 configuration
- Radxa Rock 2 - use rock2 configuration
+ - Tinker RK3288 - use t
Hi Jaehoon,
Philipp has send out another patch for disable t he secure region,
and this patch is no need now.
Thanks,
- Kever
On 03/30/2017 01:04 PM, Jaehoon Chung wrote:
On 03/30/2017 12:01 PM, Kever Yang wrote:
Hi Philipp,
On 03/29/2017 08:59 PM, Dr. Philipp Tomsich wrote
Hi Philipp,
So you got hang in SPL if the DWMMC is no in fifo mode, do you have
any clue for what's the root cause?
+ Ziyuan,
Hi Ziyuan,
Could you double check this issue? Does it also happen at rk3288 dwmmc?
Thanks,
- Kever
On 03/29/2017 01:14 AM, Philipp Tomsich wrote:
The RK3399
This patch needs work with some patch for SPL support multi
binary in FIT which is from Andre.
The entry point of bl31 and bl33 is still using hard code because we
still can not get them from the FIT image information.
Changes in v1:
- license update
- split out as separate patch
Kever Yang
Rockchip spl driver needs using spl_early_init().
Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit)
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/mach-rockchip/rk3188-board-spl.c | 4 ++--
arch/arm/mach-rockchip/rk3399-board-spl.c | 4 ++--
2 files c
Hi Marek,
On 03/21/2017 12:33 AM, Marek Vasut wrote:
On 03/20/2017 05:01 PM, Simon Glass wrote:
Hi Marek,
On 20 March 2017 at 06:24, Marek Vasut wrote:
On 03/20/2017 02:53 AM, Eddie Cai wrote:
2017-03-17 5:26 GMT+08:00 Marek Vasut :
On 03/15/2017 08:56 AM,
Hi Eddie,
I recommend you to use ums framework instead of fastboot, because
ums have dual-buffer which improve performance.
Thanks,
- Kever
On 03/15/2017 03:56 PM, Eddie Cai wrote:
this patch implement fastboot protocol on the device side. this is based on USB
download gadget
Hi Eddie, Simon,
Could you help to correct rk3188, rk3399 spl at the same time?
Thanks,
- Kever
On 03/15/2017 10:43 PM, Simon Glass wrote:
From: Eddie Cai
Use spl_early_init() to make sure that early malloc() is initialised. This
fixes booting on firefly-rk3288,
Hi Philipp,
It's great to see your patch fix the align issue in rk3399, reserve
space
for magic tag is a good idea which is the same with our internal code.
In this case, you do not need to separate for rk3399 and other Rockchips
SoCs:
1. SPL code: reserve 4-byte space for all rockchip
for all
other images. Then the SPL handle PC to BL31 with the parameter, the
BL31 will do the rest of work and at last get into U-Boot(BL33).
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v1:
- license update
- split out as separate patch
common/spl/Kconfig | 14 +++
Hi Eddie,
We should only need to do only one time cache operation for a buffer
ready to do DMA transfer, so you need to remove another cache invalidate
operation for the same buffer in the same function.
Thanks,
- Kever
On 04/01/2017 02:51 PM, Eddie Cai wrote:
We should invalidate the
Hi Eric,
1. Please use full name in you signature;
2. add commit message for all your commits;
3. add 'rockchip' and module name for all your patches.
4. 'From: ' in not need for patch from yourself.
Thanks,
- Kever
On 04/01/2017 10:42 PM, eric@rock-chips.com wrote:
From: "eric.gao"
Use regulators_enable_boot_on() instead of init regulators one by one,
the interface can init all the regulators with regulator-boot-on property.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
board/rockchip/evb_rk3399/evb-rk3399.c | 5 ++---
1 file changed, 2 insertions
Hi Simon,
Please ignore this patch, the GMAC RST pin IO number is wrong in
this patch, I will send a new patch for it.
Thanks,
- Kever
On 04/12/2017 11:54 AM, Kever Yang wrote:
Enable gmac for evb-rk3399.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3399-e
Enable gmac for evb-rk3399.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3399-evb.dts | 23 +++
configs/evb-rk3399_defconfig | 4
2 files changed, 27 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-e
Clean the evb-rk3399_defconfig with make savedefconfig.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
configs/evb-rk3399_defconfig | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
Since our sdram driver is ready, we can use the actual size
instead of hard code.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 8
board/rockchip/evb_rk3399/evb-rk3399.c | 19 ++-
2 files chang
- PCIe
- USB 3.0 HOST, type-C port
- sdio, sd-card
- HDMI
- Ethernet
- OPTICAL
- WiFi/BT
- MIPI CSI/DSI
- IR
- EDP/DP
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-firefly.dts | 684 +
The kernel dts has update a lot since the first time we commit rk3399.dtsi,
sync with kernel for further development.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3399.dtsi | 1288 +-
include/dt-bindings/pinctrl/rock
oltage shaking,
which lead to the system not stable.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/power/regulator/pwm_regulator.c | 12 ++--
drivers/pwm/pwm-uclass.c| 10 ++
drivers/pwm/rk_pwm.c| 17 -
i
The lower address is reserved for ATF, do not use it.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
include/configs/rk3399_common.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 8
Need to enablt CONFIG_OF_EMBED if we use separate uboot and dtb
in FIT image for SPL loading.
Run make savedefconfig to make the options order correct.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
configs/evb-rk3399_defconfig | 43
Hi Eddie,
On 04/06/2017 10:14 AM, Marek Vasut wrote:
On 04/06/2017 04:03 AM, Eddie Cai wrote:
We should invalidate the dcache before starting the DMA. In case there are
any dirty lines from the DMA buffer in the cache, subsequent cache-line
replacements may corrupt the buffer in memory while
Hi Simon,
On 04/10/2017 03:28 AM, Simon Glass wrote:
Hi Kever,
On 7 April 2017 at 04:35, Kever Yang <kever.y...@rock-chips.com> wrote:
Need to enablt CONFIG_OF_EMBED if we use separate uboot and dtb
in FIT image for SPL loading.
Can you please explain that a bit more? We shouldn't OF
[] = {
{ .compatible = "rockchip,rk3399-pmugrf", .data =
ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3399-pmusgrf", .data =
ROCKCHIP_SYSCON_PMUSGRF },
{ .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC },
+ { }
This is a copy from kernel.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
doc/device-tree-bindings/pwm/pwm.txt | 69
1 file changed, 69 insertions(+)
create mode 100644 doc/device-tree-bindings/pwm/pwm.txt
diff --git
oltage shaking,
which lead to the system not stable.
Signed-off-by: Elaine Zhang <zhangq...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- use pwm_set_invert() instead of pwm_set_init()
- add comment for polarity
drivers/power/regulator/pw
RK3399 device memory region is 0xf800~0x.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/mach-rockchip/rk3399/rk3399.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c
b/arch/arm/mach-ro
sion which bl31 do not do the relocate already in production for our
rk3399
chromebook and Android project, but I think people won't change there
already
has a lot of discuss on this.
Thanks,
- Kever
Regards,
Philipp.
On 14 Apr 2017, at 12:21, Kever Yang <kever.y...@rock-chips.com> wro
Enable gmac for evb-rk3399.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- correct rst pin number
arch/arm/dts/rk3399-evb.dts | 24
configs/evb-rk3399_defconfig | 4
2 files changed, 28 insertions(+)
diff --git a/arch/arm/dts/
The pwm3 on evb-rk3399 is used for pwm regulator, need to invert
the polarity to make it works correct.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3399-evb.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-evb.dts
Hi Andy,
1. no base address definition in header file, like CRU, GRF base;
2. some comment style need to fix;
3. patches for Makefile seems not correct;
Thanks,
- Kever
On 04/21/2017 10:29 AM, Andy Yan wrote:
The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support
Hi Simon,
When I try to update
rk3399.dtsi(https://patchwork.ozlabs.org/patch/749901/), I get error
report like this:
spl/dts/dt-platdata.c:10:17: error: ‘dtv_clock_controller_at_ff76’
undeclared here (not in a function)
.clocks = {{_clock_controller_at_ff76, 78},
load ATF image.
More detail about cortex-M0 code in ATF:
https://github.com/ARM-software/arm-trusted-firmware/commit/
8382e17c4c6bffd15119dfce1ee4372e3c1a7890
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/boot0.h | 4
1 file changed, 4 inse
load ATF image.
More detail about cortex-M0 code in ATF:
https://github.com/ARM-software/arm-trusted-firmware/commit/
8382e17c4c6bffd15119dfce1ee4372e3c1a7890
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/boot0.h | 4
1 file changed, 4 inse
Add support for rk3328 package header in mkimage tool.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 6cdb749..8803593 100644
--- a/tools/rkcommon.c
+++ b/tools/rkco
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