There are two same gmac node, remove one.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3399-evb.dts | 16
1 file changed, 16 deletions(-)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index f5af75b..f33e165 100644
---
Update the tx_deday and rx_delay to match the timing for
rk3399-firefly board to improve the stability of gmac data
transfer.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3399-firefly.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
The description for eMMC/SDIO/SDMMC src is not correct,
update the CRU_CLKSEL11_CON value definition according to TRM.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
hdr = (struct andr_img_hdr *)hdr_addr;
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
common/fb_mmc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
Enable SPL_FIT_GENERATOR with path for it.
With this patch you can get u-boot.itb for rk3399-evb with:
> make u-boot.itb
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
configs/firefly-rk3399_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/config
Since we support ATF in SPL and add script for it, let's make the
document up to date.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
board/rockchip/evb_rk3399/README | 79
1 file changed, 63 insertions(+), 16 deletions(-)
diff --git a
Add a script to generate binaries from bl31.elf, and generate
u-boot.its file for FIT image including u-boot, dtb and atf binaries.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
board/rockchip/evb_rk3399/mk_fit_atf.sh | 110
1 file change
Philipp,
On 08/17/2017 04:34 PM, Dr. Philipp Tomsich wrote:
On 17 Aug 2017, at 09:17, Kever Yang <kever.y...@rock-chips.com> wrote:
Add sdram driver for rk3229 and other fix like pinctrl and sd node.
Changes in v2:
- split this patch in two patches
Kever Yang (5):
rockchip:
Hi Philipp,
On 08/17/2017 04:27 PM, Dr. Philipp Tomsich wrote:
On 17 Aug 2017, at 09:51, Kever Yang <kever.y...@rock-chips.com> wrote:
Hi Philipp,
On 07/27/2017 09:09 PM, Dr. Philipp Tomsich wrote:
On 27 Jul 2017, at 15:04, Kever Yang <kever.y...@rock-chips.com> wrote:
Philipp
On 08/18/2017 03:36 PM, Dr. Philipp Tomsich wrote:
On 18 Aug 2017, at 08:26, Kever Yang <kever.y...@rock-chips.com> wrote:
Philipp,
On 08/17/2017 04:34 PM, Dr. Philipp Tomsich wrote:
On 17 Aug 2017, at 09:17, Kever Yang <kever.y...@rock-chips.com> wrote:
Add sdram drive
Embeded the shift in mask MACRO definition in cru header file
and clock driver.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- split into two patches
arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 70 +++---
drivers/clk/rockchip/clk_rk
- Add some rk3399 and rk3328 boards;
- use rkdeveloptool instead of rkflashtool;
- use opensource.rock-chips.com instead of wikidot;
- other update.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
doc/README.rockchip | 38 --
1 file chang
- hclk/pclk_div range should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 6 +++
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro
definition in grf header file and pinctrl driver.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- add grf code clean
arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 133
d
Add aliases for mmc controller to get a fixed order with
emmc at index 0 and sdmmc at index 1.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3328.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
Hi Alex,
Thanks for your patch, but this patch is just the same with the one from
Heiko[0], right?
Thanks,
- Kever
[0] https://patchwork.ozlabs.org/patch/758272/
On 05/15/2017 08:01 PM, Alex Hixon wrote:
The config name enabling the rk3399-pinctrl driver is spelled wrong, so
it does
Enable all the boot-on regulator in default.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
board/rockchip/evb_rk3328/evb-rk3328.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c
b/board/rockchip/evb_rk3328/evb-
should not decide which group to use in pinctrl driver,
for it may be different in different board, it should goes to board
file, and the pinctrl file should setting correct iomux depends on
the com_iomux value.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/as
Move pinctrl registers definition in GRF header file,
clean code with prefix like other Rockchip SoCs.
Use Fixed regulator(gpio) for sdmmc-pwren instead of
signal controled by mmc controller.
Kever Yang (6):
rockchip: pinctrl: move rk3328 grf reg definition in header file
rockchip: pinctrl
solution, we can also do this in u-boot.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
b/drivers/pinctrl/ro
Use fixed regulator for sdmmc-pwren for sdmmc power.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3328-evb.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 01794ed..7b14982
Move GRF register bit definition into GRF header file, remove
'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 114 +
drivers/pinctrl/rockchip/pinctrl_rk
should set these IO routing in board file.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
board/rockchip/evb_rk3328/evb-rk3328.c | 12
1 file changed, 12 insertions(+)
diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c
b/board/rockchip/evb_rk3328/evb-rk3328.c
I don't know which patch break Rockchip armv7 SoC on latest source code.
The SPL works fine, but it hang at some unknown place in U-Boot, I can't
get
any log event I enable the DEBUG option.
I test with below commit
4125bbc Merge branch 'master' of git://git.denx.de/u-boot-mmc
armv8 work
Hi Philipp,
This patch makes all the Rockchip SoCs with BACK_TO_BROM enabled can not
work,
does the size correct for the SPL correct?
Thanks,
- Kever
On 04/17/2017 11:47 PM, Philipp Tomsich wrote:
We support booting both from SD/MMC images and SPI images on the
RK3399-Q7 for different
platform like
kernelci for
kernel patches in U-Boot?
Thanks,
- Kever
On 05/17/2017 05:24 PM, Bin Meng wrote:
Hi Kever,
On Wed, May 17, 2017 at 4:43 PM, Kever Yang <kever.y...@rock-chips.com> wrote:
I don't know which patch break Rockchip armv7 SoC on latest source code.
The SPL work
Hi ,
This patch need to split into two patches,
one for rockchip rk3328 and on for dwc2.
Thanks,
- Kever
On 05/17/2017 06:26 PM, Meng Dongyang wrote:
Fix macro error of dwc2 driver, add macro definition to config force mode
and HNP/SRP capability. Add gpio config to control vbus in host
viewed-by: Simon Glass <s...@chromium.org>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Tested-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
---
common/spl/spl_fit.c | 42 -
doc/uImage.FIT/howto.txt | 21 +++
function, which we just call twice.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Reviewed-by: Simon Glass <s...@chromium.org>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Tested-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
---
co
er re-usage, we also generalize the spl_fit_select_index()
function to not return the image location, but just the node offset.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Reviewed-by: Lokesh Vutla <lokeshv...@ti.com>
Reviewed-by: Simon Glass <s...@chromium.org>
Re
<andre.przyw...@arm.com>
Reviewed-by: Simon Glass <s...@chromium.org>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Tested-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
---
common/spl/spl_fit.c | 15 +--
1 file changed, 13 insertions(+), 2
I though I have add review and test tags for the first 5 patches, anyway,
I will add again.
Not sure if some patches for sunxi still need to wait, can we merge patches
for SPL/FIT first?
Thanks,
- Kever
On 04/26/2017 08:32 AM, Andre Przywara wrote:
Another round of smaller fixes for the
On 05/16/2017 02:51 AM, Heiko Stübner wrote:
Hi Kever,
Am Montag, 15. Mai 2017, 21:18:00 CEST schrieb Kever Yang:
- Add some rk3399 and rk3328 boards;
- use rkdeveloptool instead of rkflashtool;
- use opensource.rock-chips.com instead of wikidot;
- other update.
Signed-off-by: Kever Yang
t;lokeshv...@ti.com>
Reviewed-by: Simon Glass <s...@chromium.org>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Tested-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
---
common/spl/spl_fit.c | 88 ++--
1
Embeded the shift in mask MACRO, and a few fix btw:
- hclk/pclk_div range use '<=' instead of '<'
- use GPLL for pd_bus
- peri HCLK/PCLK clock rate should not bigger than ACLK
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/cru_r
- Add some rk3399 and rk3328 boards;
- use rkdeveloptool;
- add link to opensource.rock-chips.com instead of wikidot;
- other update.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- add rkflashtool info back
doc/README.rockchi
.
This suppose to be set in SPL, but the U-Boot is also design to co-work
with Rockchip SPL(miniloader) which may not setting this config, let's set
this config to make sure the UART2 TX/RX working in U-Boot.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- remove SD
solution, we can also do this in u-boot.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/dri
Use fixed regulator for sdmmc-pwren for sdmmc power.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
arch/arm/dts/rk3328-evb.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk33
Enable all the boot-on regulator in default.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
board/rockchip/evb_rk3328/evb-rk3328.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/bo
I get the compiler from Linaro and uncompress the tar ball, then I build
U-Boot with:
CROSS_COMPILE=../toolchain/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-
make evb-rk3288_defconfig all
Any one met this?
log message:
CC spl/lib/panic.o
CC
Simon,
After the long discuss, this patch can be applied without any
update, right?
Thanks,
- Kever
On 05/23/2017 04:26 AM, Simon Glass wrote:
On 18 May 2017 at 02:05, Kever Yang <kever.y...@rock-chips.com> wrote:
Add aliases for mmc controller to get a fixed order with
emmc at i
According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
integer mode, while the '0' means the frac mode.
series-version: 2
series-changes: 2
- fix tpyo interger/integer
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@
Hi Marek,
On 06/07/2017 02:28 PM, Marek Vasut wrote:
On 06/07/2017 04:28 AM, Kever Yang wrote:
Hi Andre, Steve, Marek,
Could you help to check how to make it work with this patch on
sunxi, bcm and socfpga platform?
The socfpga expects the hook at that exact position (0x40 I think) , so
Hi Simon,
On 06/09/2017 08:27 PM, Simon Glass wrote:
Hi Kever,
On 7 June 2017 at 04:55, Kever Yang <kever.y...@rock-chips.com> wrote:
Simon,
On 06/07/2017 11:15 AM, Simon Glass wrote:
Hi Kever,
On 6 June 2017 at 20:41, Kever Yang <kever.y...@rock-chips.com> wrote:
Simon,
Hi Philipp,
On 06/10/2017 02:47 AM, Philipp Tomsich wrote:
On Wed, 31 May 2017, Kever Yang wrote:
The '_start' is using as vector table base address, and will write
to VBAR register, need to align to 0x20 for armv7.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
ar
Hi Simon,
On 06/09/2017 08:28 PM, Simon Glass wrote:
On 7 June 2017 at 19:20, Kever Yang <kever.y...@rock-chips.com> wrote:
According to MMC spec, the write_counter is 4-byte length,
use 'int' instead of 'long' type for the 'long' is not 4-byte
in 64 bit CPU.
Signed-off-by: Jason Zhu
RK3229 is a Quad-core Cortex-A7 SoC, which supports:
- 4K 10bit H.264/H.265,VP9.
- 32KB internal memory;
- eMMC 4.5.1, SD3.0;
- DDR3, LPDDR2, LPDDR3;
- HDMI 2.0 output, 4K@60Hz;
- USB2.0 OTG and USB2.0 host;
Changes in v2:
- update copyright
- fix typo
- some update for sdram common code
Kever
Enable soc support for SPL and U-boot skeleton.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v2:
- some update for sdram common code
arch/arm/include/asm/arch-rockchip/clock.h| 1 +
a
The dts files are from kernel and with modify to adapt U-Boot.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v2: None
arch/arm/dts/rk3229-evb.dts| 77
arch/arm/dts
evb_rk3229 is a RK3229 based board, with:
- 8GB eMMC;
- 1GB DDR SDRAM;
- 2 USB2.0 HOST port;
- 1 MAC port;
- 1 HDMI port;
- IR;
- WiFi;
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v2: Non
Add support for rk322x package header in mkimage tool.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v2: None
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/
Add clock driver init support for:
- cpu, bus clock init;
- emmc, sdmmc clock;
- ddr clock;
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v2:
- update copyright
- fix typo
arch/arm/incl
Add init pinctrl driver support for:
- i2c;
- spi;
- uart;
- pwm;
- emmc/sdmmc;
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v2: None
arch/arm/include/asm/arch-rockchip/grf_rk
Rockchip rk322x sysreset is much like rk3036 and other Rockchip SoCs,
only difference is that the target register address is different.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v2: No
The rv1108 do not have DRAM driver now, so disable it first,
or else it will get conflict with the sdram common code.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
configs/evb-rv1108_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/confi
The bank0 ram size should be the DRAM size minus reserved size,
the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- move the dram_init_banksize() from board file into soc file for we
have the same s
Add dmc node to enable sdram driver.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
arch/arm/dts/rk3368.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index 025dc32..9daf765 100644
---
Hi Philipp,
On 06/12/2017 10:19 PM, Philipp Tomsich wrote:
On Fri, 9 Jun 2017, Kever Yang wrote:
Rockchip rk322x sysreset is much like rk3036 and other Rockchip SoCs,
only difference is that the target register address is different.
Signed-off-by: Kever Yang <kever.y...@rock-chips.
Hi Simon,
On 06/17/2017 11:41 AM, Simon Glass wrote:
On 13 June 2017 at 03:29, Kever Yang <kever.y...@rock-chips.com> wrote:
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capa
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
arch/arm/include/as
There are some functions like sdram_size_mb can be re-used for
different rockchip SoCs, just put them into common file.
Add board_get_usable_ram_top() for ram_top init base on
SDRAM_MAX_SIZE.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- add board_get_usable_r
()
- add evb-px5 and geekbox board
- use CONFIG_SYS_SDRAM_BASE for ram_base
- move the dram_init_banksize() from board file into soc file for we
have the same setting for different board in one SoC now.
Kever Yang (8):
rockchip: add sdram_common for common functions
rockchip: use common sdram
Replace the sdram_init() in board init and rockchip_sdram_size() in
sdram driver for all the Rockchip SoCs which enable CONFIG_RAM.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- add evb-px5 and geekbox board
- use CONFIG_SYS_SDRAM_BASE for ram_base
arch/arm/i
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
arch/arm/mach-rockchip/
Add a dmc node for sdram driver.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
arch/arm/dts/rk3328.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index f18cfc2..50e5df5 100644
--- a/ar
Hi Ziyuan, Simon,
On 05/20/2017 10:29 AM, Simon Glass wrote:
Hi Ziyuan,
On 8 May 2017 at 01:01, Ziyuan wrote:
hi simon,
I need to achieve emmc_phy physical address in driver, so that I can
configure phy in different scenarios (phy register address should be
Tom,
This is not from kernel, seems the kernel mmc driver does not
support aliases now,
thought I hope they both support the aliases for ordering.
Thanks,
- Kever
On 05/23/2017 05:18 AM, Tom Rini wrote:
On Thu, May 18, 2017 at 04:05:20PM +0800, Kever Yang wrote:
Add aliases for mmc
Directory board/rockchip/ are all boards for Rockchip SoCs,
so add it to maintained entry.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0962b47..56dd1f3 100644
--- a/MAINTAINERS
Update maintainer to Kever Yang for William Zhang is not
work for this board now.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
board/rockchip/evb_rk3328/MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS
b
Send patch to Kever Yang instead of Lin Huang for Rockchip patches,
for Lin is not always working on upstream U-Boot.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
doc/git-mailrc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/git-mailrc b/doc/git-
Hi Simon,
On 05/20/2017 10:29 AM, Simon Glass wrote:
Hi Kever,
On 16 May 2017 at 21:44, Kever Yang <kever.y...@rock-chips.com> wrote:
In rk3328, some function pin may have more than one choice, and muxed
with more than one IO, for example, the UART2 controller IO,
TX and RX, have 3
Philipp and Andy,
I will remove the "spl_boot0 == false" case in next version.
Rockchip ddr.bin is always with pre-paded TAG.
Thanks,
- Kever
On 06/01/2017 03:41 PM, Dr. Philipp Tomsich wrote:
On 01 Jun 2017, at 03:11, Andy Yan wrote:
Hi Philipp:
2017-05-31 18:58
oms...@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
---
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c
b/a
Tomsich <philipp.toms...@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.go...@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
---
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
Hi Andre, Steve, Marek,
Could you help to check how to make it work with this patch on
sunxi, bcm and socfpga platform?
Thanks,
- Kever
On 05/31/2017 06:50 PM, Kever Yang wrote:
The boot0 hook suppose to add some data before the SPL data,
let's move it at very begining and before '_start
Simon, Pawel,
On 06/07/2017 05:10 AM, Simon Glass wrote:
On 6 June 2017 at 12:52, Paweł Jarosz wrote:
Commit message?
Signed-off-by: Paweł Jarosz
---
arch/arm/mach-rockchip/rk3066/Makefile | 1 +
Simon,
On 06/01/2017 11:10 AM, Simon Glass wrote:
Hi Kever,
On 23 May 2017 at 20:35, Kever Yang <kever.y...@rock-chips.com> wrote:
Hi Simon,
On 05/20/2017 10:29 AM, Simon Glass wrote:
Hi Kever,
On 16 May 2017 at 21:44, Kever Yang <kever.y...@rock-chips.com> wrote:
In
Simon,
On 06/07/2017 05:08 AM, Simon Glass wrote:
Hi Kever,
On 31 May 2017 at 04:50, Kever Yang <kever.y...@rock-chips.com> wrote:
I think the boot0 hook is suppose to add some data in the very beginning
of the SPL image, am I right?
Rockchip SoCs bootrom design is like this:
- Fir
Simon,
On 06/07/2017 05:10 AM, Simon Glass wrote:
Hi Pawel,
On 6 June 2017 at 12:51, Paweł Jarosz wrote:
rk3066 and rk3288 mmc designware ip's are very similiar. They differ in
internal dma support and max driver frequency.
Signed-off-by: Paweł Jarosz
Simon,
On 06/07/2017 11:15 AM, Simon Glass wrote:
Hi Kever,
On 6 June 2017 at 20:41, Kever Yang <kever.y...@rock-chips.com> wrote:
Simon,
On 06/07/2017 05:08 AM, Simon Glass wrote:
Hi Kever,
On 31 May 2017 at 04:50, Kever Yang <kever.y...@rock-chips.com> wrote:
I think th
According to MMC spec, the write_counter is 4-byte length,
use 'int' instead of 'long' type for the 'long' is not 4-byte
in 64 bit CPU.
Signed-off-by: Jason Zhu <jason@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/mmc/rpmb.c | 2 +-
1 fil
When CONFIG_BLK is enabled, the hwpart id is different with legacy
interface, update it to kame driver work with CONFIG_BLK.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
cmd/mmc.c | 4
1 file changed, 4 insertions(+)
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 832eeb0..c
Enable the spl_boot0 in SPL and use the pre-padding TAG memory,
the mkimage do not need to pad it but only need to replace the value
with correct TAG value.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
tools/rkcommon.c | 8
1 file changed, 4 insertions(+), 4 del
to reserve the first 4-byte tag for all
the Rockchip SoCs.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/mach-rockchip/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 740dbdf..82aa2d2
' are filled with 'nop' instruction.
This patch set does not provide patch for socfpga, bcm and sunxi SoCs which also
enable BOOT0_HOOK, so this is a RFC patch, please advice how to make it
compatible with those three platforms.
Kever Yang (5):
armv7: move boot hook before '_start'
rockchip
The '_start' is using as vector table base address, and will write
to VBAR register, need to align to 0x20 for armv7.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/boot0.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff
The boot0 hook suppose to add some data before the SPL data,
let's move it at very begining and before '_start'.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/lib/vectors.S | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/a
After we use boot0 hook, we can use offset '000' instead of '004' as
SPL_TEXT_BASE.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
include/configs/rk3036_common.h | 2 +-
include/configs/rk3288_common.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/i
According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
interger mode, while the '0' means the frac mode.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3036.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drive
Some function like the dram capability decode and dram_init() are
the same for all Rockchip SoCs, maybe alaso cap detect function later,
add sdram_common.c for all SoC driver.
Kever Yang (7):
rockchip: add sdram_common for common functions
rockchip: use common sdram function
rockchip
Add dmc node to enable sdram driver.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3368.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index 025dc32..9daf765 100644
--- a/arch/arm/dts/rk336
Add a dmc node for sdram driver.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3328.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index f18cfc2..50e5df5 100644
--- a/arch/arm/dts/rk3328.dtsi
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/grf_rk
rk3036 sdram driver does not use DM, remove CONFIG_RAM first.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
configs/evb-rk3036_defconfig | 1 -
configs/kylin-rk3036_defconfig | 1 -
2 files changed, 2 deletions(-)
diff --git a/configs/evb-rk3036_defconfig b/confi
Rockchip using the same bit definition for dram info and write
to os_reg, the col and bw info is not correct and let's fix it.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
Replace the sdram_init() in board init and rockchip_sdram_size() in
sdram driver for all the Rockchip SoCs which enable CONFIG_RAM.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 48 ---
arch/arm/mach-rockchip/rk3188-b
,
Philipp.
On 13 Jun 2017, at 11:29, Kever Yang <kever.y...@rock-chips.com> wrote:
Some function like the dram capability decode and dram_init() are
the same for all Rockchip SoCs, maybe alaso cap detect function later,
add sdram_common.c for all SoC driver.
Kever Yang (7):
rockchi
There are some functions like sdram_size_mb can be re-used for
different rockchip SoCs, just put them into common file.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 58 ++
arch/arm/mach-rockchip/Ma
The bank0 ram size should be the DRAM size minus reserved size,
the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
board/rockchip/evb_rk3328/evb-rk3328.c| 2 +-
board/rockchip/evb_rk3399/evb-rk3399.c
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