Hi,
On 18.2.2012 14:01, Bert Vermeulen wrote:
> On 02/14/2012 03:04 PM, Håvard Espeland wrote:
>
>> Thanks for the report Mikael. I do not have a Sigma at home, but I can
>> try to reproduce this during the weekend. If you have the new SIGMA2, we
>> have not yet updated the firmware for this device, and it will not work.
>> I'll try do update the firmware this weekend as well.
>
> That reminds me -- Håvard, can you please revisit the issue we had regarding
> the zlib dependency? The problem was that the Asix firmware images are
> zipped, and the resulting zlib dependency in libsigrok is actually only
> there for for the Asix Sigma driver. We'd like to get rid of it, any chance
> of providing the images uncompressed? Does the Asix license permit this?

It seems that zlib dependency is kind of painful. Let's say it is not 
required to keep the images compressed, only xored with lsfr.

>
> Also, another question: there is some reference to frequency counter
> functionality that the Sigma driver apparently has. What's the story there,
> can we support this? Because this is something I'd very much like to start
> doing in sigrok as well.

It is special configuration (you already have it) and it is quite simple 
to use it. Each frequency measuring unit (there are four of them in the 
FPGA, more did not fit in it) has three 32-bit counters, first is time 
(counter running at 50MHz), second is amount of time when input was high 
(to compute duty cycle) and third is number of rising edges of the input 
during the period. Start and stop is always aligned to input edge and 
measuring time is kept to be around 100ms, all this is done by the 
hardware, software only periodically reads these three registers and 
does the calculation. I will eventually provide the documentation of the 
register map. But I don't have it in document yet and I cannot do it 
before March.

Ondrej

>
>

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