On Sun, Apr 25, 2010 at 03:25:16PM -0500, H Hartley Sweeten wrote: > With a slow enough clock you can probably get to a point where SFRMOUT > will stay deasserted during the entire 512 byte transfer. But it would > still de-assert during the switch to the next transfer in the message. > > Regardless, I tend to agree with you. Because of the chip design, it's > impossible (or at least you can't guarantee) to keep the SFRMOUT low > during a transfer. Some devices can live with this others can't. Oh well.
One more thing I forgot to mention. With DMA there are 2 buffers per channel which means that the controller can continue right to the next transfer so SFRMOUT might work better. Regards, MW ------------------------------------------------------------------------------ _______________________________________________ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
