2.6.32-longterm review patch. If anyone has any objections, please let us know.
------------------
From: Carolyn Wyborny <carolyn.wybo...@intel.com>
commit 064b43304ed8ede8e13ff7b4338d09fd37bcffb1 upstream.
Register writes followed by a delay are required to have a flush
before the delay in order to commit the values to the register. Without
the flush, the code following the delay may not function correctly.
Reported-by: Tong Ho <tong...@ericsson.com>
Reported-by: Guenter Roeck <guenter.ro...@ericsson.com>
Signed-off-by: Carolyn Wyborny <carolyn.wybo...@intel.com>
Tested-by: Aaron Brown <aaron.f.br...@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirs...@intel.com>
Signed-off-by: Greg Kroah-Hartman <gre...@suse.de>
---
drivers/net/igb/e1000_82575.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -941,6 +941,7 @@ static s32 igb_setup_copper_link_82575(s
ctrl |= E1000_CTRL_SLU;
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
wr32(E1000_CTRL, ctrl);
+ wrfl();
ret_val = igb_setup_serdes_link_82575(hw);
if (ret_val)
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