Hi all!
I'm in the process to add a CAN interface to the 393. For this we use
the sensor ports 0 and 1 because we will later reuse them for other
things like UART, display controller and so on. The other two sensor
ports are connected to image sensors. We have added entries for the CAN
controllers to the device tree so the Linux kernel recognizes them and
enables the driver. For the bitstream two ports are added and routed to
the CAN controller via EMIO.
Sadly this doesn't work and the signal seems to be broken (screenshot
here https://www.mikrocontroller.net/attachment/328506/SCR03.PNG). The
CAN device is enabled with the following commands:
root@elphel393:~# ip link set can0 type can bitrate 500000
root@elphel393:~# ip link set can0 up
root@elphel393:~# cansend can0 404#09FA05
It seems to me that the controller isn't fully enabled or the routing is
broken. My guess is that there is some configuration or flag missing in
the bitstream. I know that Vivado enables the controller in a block
design with
set_property -dict [list CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {1}]
[get_bd_cells processing_system7_0]
so I added to the x393_placement.tcl:
set_property -dict [list CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {1}]
[get_cells ps7_i]
which doesn't synthesize with the error message "ERROR: [Netlist 29-69]
Cannot set property 'CONFIG.PCW_CAN0_PERIPHERAL_ENABLE', because the
property does not exist for objects of type 'cell'. "
So what do I need to change to use the CAN controller?
Thanks in advance,
Fabjan Sukalia
PS: Below are the changes made to the x393 repository:
diff --git a/x393.v b/x393.v
index 927bb42..832850e 100644
--- a/x393.v
+++ b/x393.v
@@ -47,8 +47,8 @@ module x393 #(
input [3:0] sns1_dn,
inout [7:4] sns1_dp74, // other non-diff signals
inout [7:4] sns1_dn74, // other non-diff signals
- input sns1_clkp,
- input sns1_clkn,
+ //input sns1_clkp,
+ //input sns1_clkn,
inout sns1_scl,
inout sns1_sda,
inout sns1_ctl,
@@ -89,8 +89,8 @@ module x393 #(
`else
inout [7:0] sns1_dp,
inout [7:0] sns1_dn,
- inout sns1_clkp,
- inout sns1_clkn,
+ //inout sns1_clkp,
+ //inout sns1_clkn,
inout sns1_scl,
inout sns1_sda,
inout sns1_ctl,
@@ -158,7 +158,10 @@ module x393 #(
output TXP,
// sata clocking iface
input EXTCLK_P,
input EXTCLK_N
+ // CAN interface
+ output can_tx,
+ input can_rx
);
`include "fpga_version.vh"
@@ -1616,6 +1619,9 @@ assign axi_grst = axi_rst_pre;
wire saxi1_bready;
wire [ 5:0] saxi1_bid;
wire [ 1:0] saxi1_bresp;
+
+ wire sns1_clkp;
+ wire sns1_clkn;
sensors393 #(
.SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
@@ -2755,8 +2761,8 @@ sata_ahci_top sata_top(
PS7 ps7_i (
// EMIO interface
// CAN interface
- .EMIOCAN0PHYTX(), // CAN 0 TX, output
- .EMIOCAN0PHYRX(), // CAN 0 RX, input
+ .EMIOCAN0PHYTX(can_tx), // CAN 0 TX, output
+ .EMIOCAN0PHYRX(can_rx), // CAN 0 RX, input
.EMIOCAN1PHYTX(), // Can 1 TX, output
.EMIOCAN1PHYRX(), // CAN 1 RX, input
// GMII 0
diff --git a/x393_placement.tcl b/x393_placement.tcl
index 629d797..c2b730d 100644
--- a/x393_placement.tcl
+++ b/x393_placement.tcl
@@ -154,8 +154,11 @@ if { $HISPI } {
set_property PACKAGE_PIN W11 [get_ports {sns1_dp[7]}]
set_property PACKAGE_PIN W10 [get_ports {sns1_dn[7]}]
}
-set_property PACKAGE_PIN AA10 [get_ports {sns1_clkp}]
-set_property PACKAGE_PIN AB10 [get_ports {sns1_clkn}]
+set_property -dict { PACKAGE_PIN AA10 IOSTANDARD LVCMOS25 } [get_ports
{ can_tx }]
+set_property -dict { PACKAGE_PIN AB10 IOSTANDARD LVCMOS25 } [get_ports
{ can_rx }]
+
set_property PACKAGE_PIN Y9 [get_ports {sns1_scl}]
set_property PACKAGE_PIN AA9 [get_ports {sns1_sda}]
set_property PACKAGE_PIN U9 [get_ports {sns1_ctl}]
diff --git a/x393_timing.tcl b/x393_timing.tcl
index 463c164..ab2108f 100644
--- a/x393_timing.tcl
+++ b/x393_timing.tcl
@@ -74,8 +74,8 @@ if ($HISPI) {
} else {
#Sensor-synchronous clocks
- create_generated_clock -name iclk0 [get_nets
sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre
]
- create_generated_clock -name iclk2x0 [get_nets
sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre
]
+ #create_generated_clock -name iclk0 [get_nets
sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre
]
+ #create_generated_clock -name iclk2x0 [get_nets
sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre
]
create_generated_clock -name iclk1 [get_nets
sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk_pre
]
create_generated_clock -name iclk2x1 [get_nets
sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre
]
@@ -86,7 +86,7 @@ if ($HISPI) {
create_generated_clock -name iclk3 [get_nets
sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk_pre
]
create_generated_clock -name iclk2x3 [get_nets
sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre
]
- set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous
-group {iclk0 iclk2x0}
+ #set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous
-group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous
-group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous
-group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous
-group {iclk3 iclk2x3}
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