On Tue, Aug 06, 2013 at 12:37:49AM +0200, Mark Kettenis wrote:
> The atomic_setbits_int() and atomic_clearbits_int() implementations
> use stwcx., which touches the condition code register. This means we
> need to tell GCC that it gets clobbered. Fixes issues with
> uvm_page_physload() which currently gets miscompiled.
>
> ok?
>
>
> Index: atomic.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/powerpc/include/atomic.h,v
> retrieving revision 1.4
> diff -u -p -r1.4 atomic.h
> --- atomic.h 23 Mar 2011 16:54:36 -0000 1.4
> +++ atomic.h 5 Aug 2013 22:34:00 -0000
> @@ -17,7 +17,7 @@ atomic_setbits_int(__volatile unsigned i
> " or %0, %1, %0 \n"
> " stwcx. %0, 0, %2 \n"
> " bne- 1b \n"
> - " sync" : "=&r" (tmp) : "r" (v), "r" (uip) : "memory");
> + " sync" : "=&r" (tmp) : "r" (v), "r" (uip) : "cc", "memory");
> }
>
> static __inline void
> @@ -30,7 +30,7 @@ atomic_clearbits_int(__volatile unsigned
> " andc %0, %0, %1 \n"
> " stwcx. %0, 0, %2 \n"
> " bne- 1b \n"
> - " sync" : "=&r" (tmp) : "r" (v), "r" (uip) : "memory");
> + " sync" : "=&r" (tmp) : "r" (v), "r" (uip) : "cc", "memory");
> }
>
> #endif /* defined(_KERNEL) */
Obviously okay.
