I patched this against (1st) the latest anoncvs tree and (2nd) against your
cpsw patch from 04/12/14 (2).
Both times it works (compile, boot) and so I tested the timeout bug
described at
http://marc.info/?l=openbsd-bugs&m=138275913126582&w=2
First i can reproduce the timeout bug with the latest snapshot kernel
OpenBSD 5.5 (GENERIC-OMAP) #11: Sat Mar 8 12:52:57 EST 2014
With the patched kernels (1) and (2) the timeout shiftet.
# ping -f -n -c100 -s289 <ip>
runs with 0% packet loss
# ping -f -n -c100 -s225 <ip>
runs with 0% packet loss
# ping -f -n -c100 -s221 <ip>
runs with complete packet loss (100%), sometimes I get 1 return packet.
All others -s1 up to -s1000 come back mixed, with 1/3rd coming back with
max. 1 lost packet and 2/3rd coming back with 0% packet loss.
- Ben
On 04/14/14 20:18, Brandon Mercer wrote:
whoops, small typo in the previous diff:
cvs diff: Diffing sys/arch/armv7/omap/
Index: sys/arch/armv7/omap//if_cpsw.c
===================================================================
RCS file: /cvs/src/sys/arch/armv7/omap/if_cpsw.c,v
retrieving revision 1.21
diff -u -p -u -r1.21 if_cpsw.c
--- sys/arch/armv7/omap//if_cpsw.c 26 Nov 2013 20:33:11 -0000
1.21
+++ sys/arch/armv7/omap//if_cpsw.c 14 Apr 2014 17:37:27 -0000
@@ -816,6 +816,8 @@ cpsw_init(struct ifnet *ifp)
cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
while(cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1);
+
+ cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
for (i = 0; i < 8; i++) {
cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
Index: sys/arch/armv7/omap//if_cpswreg.h
===================================================================
RCS file: /cvs/src/sys/arch/armv7/omap/if_cpswreg.h,v
retrieving revision 1.5
diff -u -p -u -r1.5 if_cpswreg.h
--- sys/arch/armv7/omap//if_cpswreg.h 15 Nov 2013 14:31:52 -0000
1.5
+++ sys/arch/armv7/omap//if_cpswreg.h 14 Apr 2014 18:08:52 -0000
@@ -39,6 +39,7 @@
#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
+#define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
#define CPSW_PORT_OFFSET 0x0100
#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 +
((p-1) * 0x100))
