On Sat, Jul 01, 2017 at 10:53:14AM +0300, Artturi Alm wrote: > Hi, > > just in case i didn't make it clear what it is for, here's diff "fixing" > current uses below, compile-tested. > > -Artturi >
Hi, ping? Noone up for bikeshedding, or seen useless/worse than handcrafting? I think this would alleviate from some of the complementary commenting, regarding the CP15 reg usage, that is currently somewhat of necessity. -Artturi > > diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c > index c91108e7066..fcb56627af7 100644 > --- a/sys/arch/arm/arm/cpufunc.c > +++ b/sys/arch/arm/arm/cpufunc.c > @@ -55,6 +55,7 @@ > #include <machine/pmap.h> > #include <arm/cpuconf.h> > #include <arm/cpufunc.h> > +#include <arm/sysreg.h> > > #if defined(PERFCTRS) > struct arm_pmc_funcs *arm_pmc; > @@ -176,8 +177,7 @@ arm_get_cachetype_cp15v7(void) > uint32_t sel, level; > > /* CTR - Cache Type Register */ > - __asm volatile("mrc p15, 0, %0, c0, c0, 1" > - : "=r" (ctype)); > + __asm volatile("mrc " SR_STR(CP15_CTR(%0)) "\n" : "=r"(ctype)); > > arm_dcache_min_line_size = 1 << (CPU_CT_DMINLINE(ctype) + 2); > arm_icache_min_line_size = 1 << (CPU_CT_IMINLINE(ctype) + 2); > @@ -185,8 +185,8 @@ arm_get_cachetype_cp15v7(void) > min(arm_icache_min_line_size, arm_dcache_min_line_size); > > /* CLIDR - Cache Level ID Register */ > - __asm volatile("mrc p15, 1, %0, c0, c0, 1" > - : "=r" (cache_level_id) :); > + __asm volatile("mrc " SR_STR(CP15_CLIDR(%0)) > + : "=r"(cache_level_id)); > cpu_drain_writebuf(); > > /* L1 Cache available. */ > @@ -201,17 +201,18 @@ arm_get_cachetype_cp15v7(void) > cache_level_id & (0x2 << level)) { > sel = level << 1 | 0 << 0; /* L1 | unified/data cache */ > /* CSSELR - Cache Size Selection Register */ > - __asm volatile("mcr p15, 2, %0, c0, c0, 0" > - :: "r" (sel)); > + __asm volatile("mcr " SR_STR(CP15_CSSELR(%0)) "\n" > + :: "r"(sel)); > cpu_drain_writebuf(); > /* CCSIDR - Cache Size Identification Register */ > - __asm volatile("mrc p15, 1, %0, c0, c0, 0" > - : "=r" (cachereg) :); > + __asm volatile("mcr " SR_STR(CP15_CCSIDR(%0)) "\n" > + : "=r"(cachereg)); > cpu_drain_writebuf(); > sets = ((cachereg >> 13) & 0x7fff) + 1; > arm_pdcache_line_size = 1 << ((cachereg & 0x7) + 4); > arm_pdcache_ways = ((cachereg >> 3) & 0x3ff) + 1; > - arm_pdcache_size = arm_pdcache_line_size * > arm_pdcache_ways * sets; > + arm_pdcache_size = > + arm_pdcache_line_size * arm_pdcache_ways * sets; > switch (cachereg & 0xc0000000) { > case 0x00000000: > arm_pcache_type = 0; > @@ -230,24 +231,26 @@ arm_get_cachetype_cp15v7(void) > if (cache_level_id & (0x1 << level)) { > sel = level << 1 | 1 << 0; /* L1 | instruction cache */ > /* CSSELR - Cache Size Selection Register */ > - __asm volatile("mcr p15, 2, %0, c0, c0, 0" > - :: "r" (sel)); > + __asm volatile("mcr " SR_STR(CP15_CSSELR(%0)) "\n" > + :: "r"(sel)); > cpu_drain_writebuf(); > /* CCSIDR - Cache Size Identification Register */ > - __asm volatile("mrc p15, 1, %0, c0, c0, 0" > - : "=r" (cachereg) :); > + __asm volatile("mcr " SR_STR(CP15_CCSIDR(%0)) "\n" > + : "=r"(cachereg)); > cpu_drain_writebuf(); > sets = ((cachereg >> 13) & 0x7fff) + 1; > arm_picache_line_size = 1 << ((cachereg & 0x7) + 4); > arm_picache_ways = ((cachereg >> 3) & 0x3ff) + 1; > - arm_picache_size = arm_picache_line_size * > arm_picache_ways * sets; > + arm_picache_size = > + arm_picache_line_size * arm_picache_ways * sets; > } > } > > arm_dcache_align = arm_pdcache_line_size; > arm_dcache_align_mask = arm_dcache_align - 1; > > - arm_dcache_l2_nsets = > arm_pdcache_size/arm_pdcache_ways/arm_pdcache_line_size; > + arm_dcache_l2_nsets = > + arm_pdcache_size / arm_pdcache_ways / arm_pdcache_line_size; > arm_dcache_l2_assoc = log2(arm_pdcache_ways); > arm_dcache_l2_linesize = log2(arm_pdcache_line_size); > } > @@ -255,17 +258,16 @@ arm_get_cachetype_cp15v7(void) > /* > */ > void > -armv7_idcache_wbinv_all() > +armv7_idcache_wbinv_all(void) > { > - uint32_t arg; > - arg = 0; > - __asm volatile("mcr p15, 0, r0, c7, c5, 0" :: "r" (arg)); > + /* Instruction cache invalidate all PoU */ > + __asm volatile("mcr " SR_STR(CP15_ICIALLU) "\n" ::: "memory"); > armv7_dcache_wbinv_all(); > } > > /* brute force cache flushing */ > void > -armv7_dcache_wbinv_all() > +armv7_dcache_wbinv_all(void) > { > int sets, ways, lvl; > int nsets, nways; > @@ -291,9 +293,9 @@ armv7_dcache_wbinv_all() > for (ways = 0; ways < nways; ways++) { > word = wayval | setval | lvl; > > - /* Clean D cache SE with Set/Index */ > - __asm volatile("mcr p15, 0, %0, c7, c10, 2" > - : : "r" (word)); > + /* Clean D cache SE with Set/Way */ > + __asm volatile("mcr " SR_STR(CP15_DCCSW(%0)) "\n" > + :: "r"(word)); > wayval += wayincr; > } > setval += setincr; > @@ -310,7 +312,7 @@ armv7_dcache_wbinv_all() > */ > > int > -set_cpufuncs() > +set_cpufuncs(void) > { > cputype = cpufunc_id(); > cputype &= CPU_ID_CPU_MASK; > @@ -323,8 +325,8 @@ set_cpufuncs() > if ((cputype & CPU_ID_ARCH_MASK) == CPU_ID_ARCH_CPUID) { > uint32_t mmfr0; > > - __asm volatile("mrc p15, 0, %0, c0, c1, 4" > - : "=r" (mmfr0)); > + __asm volatile("mrc " SR_STR(CP15_ID_MMFR0(%0)) > + : "=r"(mmfr0)); > > switch (mmfr0 & ID_MMFR0_VMSA_MASK) { > case VMSA_V7: > @@ -359,7 +361,7 @@ set_cpufuncs() > */ > > void > -armv7_setup() > +armv7_setup(void) > { > uint32_t auxctrl, auxctrlmask; > uint32_t cpuctrl, cpuctrlmask; > @@ -409,7 +411,7 @@ armv7_setup() > * Check for the Virtualization Extensions and enable UWXN of > * those are included. > */ > - __asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); > + __asm volatile("mrc " SR_STR(CP15_ID_PFR1(%0)) : "=r"(id_pfr1)); > if ((id_pfr1 & 0x0000f000) == 0x00001000) { > cpuctrlmask |= CPU_CONTROL_UWXN; > cpuctrl |= CPU_CONTROL_UWXN; > diff --git a/sys/arch/arm/arm/pmap7.c b/sys/arch/arm/arm/pmap7.c > index f99ee582e00..a4264ab1a04 100644 > --- a/sys/arch/arm/arm/pmap7.c > +++ b/sys/arch/arm/arm/pmap7.c > @@ -193,6 +193,7 @@ > #include <machine/pcb.h> > #include <machine/param.h> > #include <arm/cpufunc.h> > +#include <arm/sysreg.h> > > //#define PMAP_DEBUG > #ifdef PMAP_DEBUG > @@ -1822,9 +1823,10 @@ pmap_activate(struct proc *p) > if (p == curproc) { > u_int cur_ttb; > > - __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); > + __asm volatile("mrc " SR_STR(CP15_TTBR0(%0)) "\n" > + : "=r"(cur_ttb)); > > - cur_ttb &= ~(L1_TABLE_SIZE - 1); > + cur_ttb &= L1_TABLE_FRAME; > > if (cur_ttb == (u_int)pcb->pcb_pagedir) { > /* > @@ -2813,7 +2815,7 @@ void (*pmap_zero_page_func)(struct vm_page > *); > void > pmap_pte_init_armv7(void) > { > - uint32_t id_mmfr0, id_mmfr3; > + u_int mmfr; > > /* > * XXX We want to use proper TEX settings eventually. > @@ -2863,13 +2865,13 @@ pmap_pte_init_armv7(void) > pmap_zero_page_func = pmap_zero_page_generic; > > /* Check if the PXN bit is supported. */ > - __asm volatile("mrc p15, 0, %0, c0, c1, 4" : "=r"(id_mmfr0)); > - if ((id_mmfr0 & ID_MMFR0_VMSA_MASK) >= VMSA_V7_PXN) > + __asm volatile("mrc " SR_STR(CP15_ID_MMFR0(%0)) "\n" : "=r"(mmfr)); > + if ((mmfr & ID_MMFR0_VMSA_MASK) >= VMSA_V7_PXN) > l1_c_pxn = L1_C_V7_PXN; > > /* Check for coherent walk. */ > - __asm volatile("mrc p15, 0, %0, c0, c1, 7" : "=r"(id_mmfr3)); > - if ((id_mmfr3 & 0x00f00000) == 0x00100000) > + __asm volatile("mrc " SR_STR(CP15_ID_MMFR3(%0)) "\n" : "=r"(mmfr)); > + if ((mmfr & 0x00f00000) == 0x00100000) > pmap_needs_pte_sync = 0; > } > > diff --git a/sys/arch/arm/cortex/agtimer.c b/sys/arch/arm/cortex/agtimer.c > index 8d622c058a4..935a7ece026 100644 > --- a/sys/arch/arm/cortex/agtimer.c > +++ b/sys/arch/arm/cortex/agtimer.c > @@ -30,6 +30,7 @@ > #include <machine/fdt.h> > > #include <arm/cpufunc.h> > +#include <arm/sysreg.h> > #include <arm/cortex/cortex.h> > > #include <dev/ofw/fdt.h> > @@ -98,7 +99,8 @@ agtimer_readcnt64(void) > { > uint64_t val; > > - __asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (val)); > + __asm volatile("mrrc " SR_STR(CP15_CNTPCT(%Q0, %R0)) "\n" > + : "=r"(val)); > > return (val); > } > @@ -108,7 +110,7 @@ agtimer_get_ctrl(void) > { > uint32_t val; > > - __asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); > + __asm volatile("mrc " SR_STR(CP15_CNTP_CTL(%0)) "\n" : "=r"(val)); > > return (val); > } > @@ -116,11 +118,8 @@ agtimer_get_ctrl(void) > static inline int > agtimer_set_ctrl(uint32_t val) > { > - __asm volatile("mcr p15, 0, %[val], c14, c2, 1" : : > - [val] "r" (val)); > - > + __asm volatile("mcr " SR_STR(CP15_CNTP_CTL(%0)) "\n" :: "r"(val)); > cpu_drain_writebuf(); > - //isb(); > > return (0); > } > @@ -128,10 +127,8 @@ agtimer_set_ctrl(uint32_t val) > static inline int > agtimer_set_tval(uint32_t val) > { > - __asm volatile("mcr p15, 0, %[val], c14, c2, 0" : : > - [val] "r" (val)); > + __asm volatile("mcr " SR_STR(CP15_CNTP_TVAL(%0)) "\n" :: "r"(val)); > cpu_drain_writebuf(); > - //isb(); > > return (0); > } > @@ -387,9 +384,11 @@ agtimer_init(void) > uint32_t id_pfr1, cntfrq = 0; > > /* Check for Generic Timer support. */ > - __asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); > + __asm volatile("mrc " SR_STR(CP15_ID_PFR1(%0)) "\n" > + : "=r"(id_pfr1)); > if ((id_pfr1 & 0x000f0000) == 0x00010000) > - __asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (cntfrq)); > + __asm volatile("mrc " SR_STR(CP15_CNTFRQ(%0)) "\n" > + : "=r"(cntfrq)); > > if (cntfrq != 0) { > agtimer_frequency = cntfrq; > diff --git a/sys/arch/arm/include/cpu.h b/sys/arch/arm/include/cpu.h > index 312c2f6c9c9..e09bfd49570 100644 > --- a/sys/arch/arm/include/cpu.h > +++ b/sys/arch/arm/include/cpu.h > @@ -101,6 +101,7 @@ > #endif > #include <machine/frame.h> > #include <machine/pcb.h> > +#include <arm/sysreg.h> > #endif /* !_LOCORE */ > > #include <arm/armreg.h> > @@ -215,7 +216,7 @@ static inline struct cpu_info * > curcpu(void) > { > struct cpu_info *__ci; > - __asm volatile("mrc p15, 0, %0, c13, c0, 4" : "=r" (__ci)); > + __asm volatile("mrc " SR_STR(CP15_TPIDRPRW(%0)) "\n" : "=r"(__ci)); > return (__ci); > } > > diff --git a/sys/arch/arm/include/pte.h b/sys/arch/arm/include/pte.h > index 53b6cc8831f..ac80e32379a 100644 > --- a/sys/arch/arm/include/pte.h > +++ b/sys/arch/arm/include/pte.h > @@ -118,7 +118,10 @@ typedef uint32_t pt_entry_t; /* L2 table entry */ > #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */ > > #define L1_TABLE_SIZE 0x4000 /* 16K */ > +#define L1_TABLE_OFFSET (L1_TABLE_SIZE - 1) > +#define L1_TABLE_FRAME (~L1_TABLE_OFFSET) > #define L2_TABLE_SIZE 0x1000 /* 4K */ > + > /* > * The new pmap deals with the 1KB coarse L2 tables by > * allocating them from a pool. Until every port has been converted, > diff --git a/sys/arch/arm/include/sysreg.h b/sys/arch/arm/include/sysreg.h > index c2aab7d6667..f41a3b362ec 100644 > --- a/sys/arch/arm/include/sysreg.h > +++ b/sys/arch/arm/include/sysreg.h > @@ -269,4 +269,20 @@ > */ > #define CP15_CBAR(rr) p15, 4, rr, c15, c0, 0 /* Configuration > Base Address Register */ > > +/* > + * SysRegSTRing-Macro to be used within asm(), to allow using macros above. > + * like: > + * > + * u_int > + * cpu_mpidr(void) > + * { > + * u_int mpidr; > + * asm volatile("mrc " SR_STR(CP15_MPIDR(%0)) "\n" : "=r"(mpidr)); > + * return mpidr; > + * } > + * > + */ > +#define __SRSTR(...) #__VA_ARGS__ > +#define SR_STR(x) __SRSTR(x) > + > #endif /* !MACHINE_SYSREG_H */ > diff --git a/sys/arch/arm/mainbus/mainbus.c b/sys/arch/arm/mainbus/mainbus.c > index 3d36366c95b..2b65d2b9ba7 100644 > --- a/sys/arch/arm/mainbus/mainbus.c > +++ b/sys/arch/arm/mainbus/mainbus.c > @@ -26,6 +26,7 @@ > #include <dev/ofw/fdt.h> > > #include <arm/mainbus/mainbus.h> > +#include <arm/sysreg.h> > > int mainbus_match(struct device *, void *, void *); > void mainbus_attach(struct device *, struct device *, void *); > @@ -253,7 +254,7 @@ mainbus_match_primary(struct device *parent, void *match, > void *aux) > struct cfdata *cf = match; > uint32_t mpidr; > > - __asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r " (mpidr)); > + __asm volatile("mrc " SR_STR(CP15_MPIDR(%0)) "\n" : "=r"(mpidr)); > > if (fa->fa_nreg < 1 || fa->fa_reg[0].addr != (mpidr & MPIDR_AFF)) > return 0; > @@ -268,7 +269,7 @@ mainbus_match_secondary(struct device *parent, void > *match, void *aux) > struct cfdata *cf = match; > uint32_t mpidr; > > - __asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r " (mpidr)); > + __asm volatile("mrc " SR_STR(CP15_MPIDR(%0)) "\n" : "=r"(mpidr)); > > if (fa->fa_nreg < 1 || fa->fa_reg[0].addr == (mpidr & MPIDR_AFF)) > return 0; > diff --git a/sys/arch/armv7/armv7/armv7_machdep.c > b/sys/arch/armv7/armv7/armv7_machdep.c > index aa1c549b29b..b4ae9a36174 100644 > --- a/sys/arch/armv7/armv7/armv7_machdep.c > +++ b/sys/arch/armv7/armv7/armv7_machdep.c > @@ -119,6 +119,7 @@ > > #include <arm/undefined.h> > #include <arm/machdep.h> > +#include <arm/sysreg.h> > #include <arm/armv7/armv7var.h> > #include <armv7/armv7/armv7_machdep.h> > > @@ -293,12 +294,9 @@ static __inline > pd_entry_t * > read_ttb(void) > { > - long ttb; > - > - __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb)); > - > - > - return (pd_entry_t *)(ttb & ~((1<<14)-1)); > + u_int ttb; > + __asm volatile("mrc " SR_STR(CP15_TTBR0(%0)) "\n" : "=r"(ttb)); > + return (pd_entry_t *)(ttb & L1_TABLE_FRAME); > } > > #define VERBOSE_INIT_ARM