ix(4): align rx payloads to the end of the cluster

[David Gwynne]

the mcl2k2 pool, aka the intel mbuf cluster pool, gets set up to allocate
at least 2048 + 2 bytes, which gets rounded up by 64 bytes to 2112
bytes. this diff makes ix move the reception of packets to the end of
the 2112 byte allocation so there's space left at the front of the mbuf.

this in turn makes it more likely that an m_prepend at another point in
the system will work without an extra mbuf allocation. eg, if you're
bridging or routing between vlans and vlans on svlans somewhere else,
this will be a bit faster with this diff.

thoughts? ok?

Index: dev/pci/if_ix.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_ix.c,v
retrieving revision 1.152
diff -u -p -r1.152 if_ix.c
--- dev/pci/if_ix.c     22 Jun 2017 02:44:37 -0000      1.152
+++ dev/pci/if_ix.c     25 Feb 2019 00:40:47 -0000
@@ -2445,7 +2445,7 @@ ixgbe_get_buf(struct rx_ring *rxr, int i
                return (ENOBUFS);
 
        mp->m_len = mp->m_pkthdr.len = sc->rx_mbuf_sz;
-       m_adj(mp, ETHER_ALIGN);
+       m_adj(mp, mp->m_ext.ext_size - sc->rx_mbuf_sz);
 
        error = bus_dmamap_load_mbuf(rxr->rxdma.dma_tag, rxbuf->map,
            mp, BUS_DMA_NOWAIT);