Hal Murray wrote: >> Driving a full 5V TTL signal into a 50 ohm load is another matter - >> you need a lot of DC power (1/2 watt) to do that. I was just using a >> Liner Tech LT1010 for a similar job - it would get the job done, but >> folks here might complain about the phase noise. >> > > Where does that phase noise come from and/or what should I do to minimize it > if I need some sort of buffering? > > Is there a general rule about digital chips vs analog chips? > > Phase noise is produced by the internal noise of the active devices employed as well as the passive components such as resistors. Poor quality components like some capacitors can also generate significant excess phase noise. In the final analysis everything is analog during switching transitions, even digital chips. The jitter in the timing of a logic edge transition is determined by the input signal jitter plus any noise on the finite risetime input as well as internal noise in the logic circuit. Using the same chip to buffer other unrelated logic signals will produce ground bounce that may affect the effective switching threshold for a PPS signal should a transition of the unrelated logic signal occur too close to a PPS transition. The inductance of the chips power and ground connections along with the load on the unrelated signal buffer output together with the PPS input signal risetme determines the significance of this effect. The noise contributed by a device itself depends more on on the characteristics of the devices used not whether the intended application is digital or analog. Bipolar devices tend to have lower 1/f noise corner frequencies than MOSFETS, GaAs devices tend to have very high 1/f noise corner frequencies. SiGe devices have lower 1/f noise corner frequencies than GaAs devices.
Negative feedback can be used to reduce 1/f noise in analog cicuitry, such feedback is difficult to impossible to use with digital circuits so well designed analog circuitry can have lower 1/f noise than digital circuitry employing the same devices. Even after correction for sawtooth timing error the PPS output of a GPS timing receiver has a residual jitter of a few nanoseconds As long as one doesn't use a long cascaded chain of slow buffers it is very difficult to significantly degrade the jitter of the PPS output produced by a GPS timing receiver. Using a ground plane (and preferably a VCC plane) together with a good supply bypassing scheme is essential to reduce the interaction (via the impedance of the power supply system) between unrelated signals on a PCB. In a low phase noise oscillator using analog techniques is essential as it is then possible to provide local negative feedback to suppress 1/f noise generated by the active devices. However even if you are forced to use digital devices in an oscillator it is possible to significantly reduce the phase noise if the principles outlined in the latest extensions to Leeson's theory of oscillator phase noise are used. Indeed it is shown that, as observed in practice, the 1/f phase noise corner frequency of an oscillator is not identical to the 1/f noise corner of the active devices employed. Indeed in a well designed oscillator the 1/f phase noise corner is significantly lower than the 1/f noise corner of the active device used. Bruce _______________________________________________ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts