On 12/6/2012 4:26 AM, Fabio Eboli wrote:
Here are the design documents, if you're curious:
http://hg.partiallystapled.com/circuits/serafine/raw-file/d75ab09ca163/out/production.PDF
Thank you very much, I will study it with interest,
it will be very helpul to see what you have done.
Can I ask you more details? I didnt's understand
how you are using the timers: are you timestamping
each pps transistion using the internal clock?
Are you using the pll to obtain 72MHz (x9) for the clock?
Yes, the crystal oscillator is multiplied up to 72MHz which then drives
the timer. Even though the particular timer peripheral I chose happens
to be on the APB1 bus which is restricted to 36MHz, the timer itself is
still fed with the 72MHz clock. Both PPS signals (generated from OCXO
and received from GPS) are then independently timestamped. The
timestamps are extended to 64 bits by adding the value captured from the
IC to an "epoch" variable that is incremented every time the timer
itself rolls over. This works fairly well but my implementation is
slightly buggy, occasionally the timestamps will be off by an epoch
(plus or minus 65536 ticks) but such a large deviation is easily
detectable and is discarded. The timestamps are subtracted to get phase
difference which is then fed into the proportional-integral controller
which seeks to zero the phase difference, with two different "speeds"
for early startup and later settling once the oscillations dampen. This
last part is the bit that needs major work since the phase difference
continues oscillating by up to 5 "ticks" (72MHz periods) and sometimes
has excursions to 10 or 15 before it settles down again. NTPns seems to
be self-tuning which could help a great deal. The coefficients I'm using
are experimentally determined which is probably why the settling isn't
very good. There's also the problem of not currently having a TIC or
similar equipment for quantifying the performance of the system as a
whole, I should buy or build one sooner rather than later.
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